linux-core/radeon_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon_drv.h"
  30
  31 extern int atom_debug;
  32
  33 void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
  34                            struct drm_display_mode *mode,
  35                            struct drm_display_mode *adjusted_mode)
  36 {
  37         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  38         if (mode->hdisplay < radeon_encoder->panel_xres ||
  39             mode->vdisplay < radeon_encoder->panel_yres) {
  40                 radeon_encoder->flags |= RADEON_USE_RMX;
  41                 adjusted_mode->hdisplay = radeon_encoder->panel_xres;
  42                 adjusted_mode->vdisplay = radeon_encoder->panel_yres;
  43                 adjusted_mode->htotal = radeon_encoder->panel_xres + radeon_encoder->hblank;
  44                 adjusted_mode->hsync_start = radeon_encoder->panel_xres + radeon_encoder->hoverplus;
  45                 adjusted_mode->hsync_end = adjusted_mode->hsync_start + radeon_encoder->hsync_width;
  46                 adjusted_mode->vtotal = radeon_encoder->panel_yres + radeon_encoder->vblank;
  47                 adjusted_mode->vsync_start = radeon_encoder->panel_yres + radeon_encoder->voverplus;
  48                 adjusted_mode->vsync_end = adjusted_mode->vsync_start + radeon_encoder->vsync_width;
  49                 /* update crtc values */
  50                 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
  51                 /* adjust crtc values */
  52                 adjusted_mode->crtc_hdisplay = radeon_encoder->panel_xres;
  53                 adjusted_mode->crtc_vdisplay = radeon_encoder->panel_yres;
  54                 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + radeon_encoder->hblank;
  55                 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + radeon_encoder->hoverplus;
  56                 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + radeon_encoder->hsync_width;
  57                 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + radeon_encoder->vblank;
  58                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + radeon_encoder->voverplus;
  59                 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + radeon_encoder->vsync_width;
  60         } else {
  61                 adjusted_mode->htotal = radeon_encoder->panel_xres + radeon_encoder->hblank;
  62                 adjusted_mode->hsync_start = radeon_encoder->panel_xres + radeon_encoder->hoverplus;
  63                 adjusted_mode->hsync_end = adjusted_mode->hsync_start + radeon_encoder->hsync_width;
  64                 adjusted_mode->vtotal = radeon_encoder->panel_yres + radeon_encoder->vblank;
  65                 adjusted_mode->vsync_start = radeon_encoder->panel_yres + radeon_encoder->voverplus;
  66                 adjusted_mode->vsync_end = adjusted_mode->vsync_start + radeon_encoder->vsync_width;
  67                 /* update crtc values */
  68                 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
  69                 /* adjust crtc values */
  70                 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + radeon_encoder->hblank;
  71                 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + radeon_encoder->hoverplus;
  72                 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + radeon_encoder->hsync_width;
  73                 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + radeon_encoder->vblank;
  74                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + radeon_encoder->voverplus;
  75                 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + radeon_encoder->vsync_width;
  76         }
  77         adjusted_mode->clock = radeon_encoder->dotclock;
  78         adjusted_mode->flags = radeon_encoder->flags;
  79 }
  80
  81
  82 static int atom_dac_find_atom_type(struct radeon_encoder *radeon_encoder, struct drm_connector *connector)
  83 {
  84         struct drm_device *dev = radeon_encoder->base.dev;
  85         struct drm_connector *connector_find;
  86         int atom_type = -1;
  87
  88         if (!connector) {
  89                 list_for_each_entry(connector_find, &dev->mode_config.connector_list, head) {
  90                         if (connector_find->encoder == &radeon_encoder->base)
  91                                 connector = connector_find;
  92                 }
  93         }
  94         if (connector) {
  95                 /* look for the encoder in the connector list -
  96                    check if we the DAC is enabled on a VGA or STV/CTV or CV connector */
  97                 /* work out the ATOM_DEVICE bits */
  98                 switch (connector->connector_type) {
  99                 case CONNECTOR_VGA:
 100                 case CONNECTOR_DVI_I:
 101                 case CONNECTOR_DVI_A:
 102                         if (radeon_encoder->atom_device & ATOM_DEVICE_CRT1_SUPPORT)
 103                                 atom_type = ATOM_DEVICE_CRT1_INDEX;
 104                         else if (radeon_encoder->atom_device & ATOM_DEVICE_CRT2_SUPPORT)
 105                                 atom_type = ATOM_DEVICE_CRT2_INDEX;
 106                         break;
 107                 case CONNECTOR_STV:
 108                 case CONNECTOR_CTV:
 109                         if (radeon_encoder->atom_device & ATOM_DEVICE_TV1_SUPPORT)
 110                                 atom_type = ATOM_DEVICE_TV1_INDEX;
 111                         break;
 112                 case CONNECTOR_DIN:
 113                         if (radeon_encoder->atom_device & ATOM_DEVICE_TV1_SUPPORT)
 114                                 atom_type = ATOM_DEVICE_TV1_INDEX;
 115                         if (radeon_encoder->atom_device & ATOM_DEVICE_CV_SUPPORT)
 116                                 atom_type = ATOM_DEVICE_CV_INDEX;
 117                         break;
 118                 }
 119         }
 120
 121         return atom_type;
 122 }
 123
 124 /* LVTMA encoder for LVDS usage */
 125 static void atombios_display_device_control(struct drm_encoder *encoder, int index, uint8_t state)
 126 {
 127         struct drm_device *dev = encoder->dev;
 128         struct drm_radeon_private *dev_priv = dev->dev_private;
 129         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
 130
 131         memset(&args, 0, sizeof(args));
 132         args.ucAction = state;
 133
 134         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 135 }
 136
 137 static void atombios_scaler_setup(struct drm_encoder *encoder, struct drm_display_mode *mode)
 138 {
 139         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 140         struct drm_device *dev = encoder->dev;
 141         struct drm_radeon_private *dev_priv = dev->dev_private;
 142         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 143         ENABLE_SCALER_PS_ALLOCATION args;
 144         int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
 145
 146         memset(&args, 0, sizeof(args));
 147         args.ucScaler = radeon_crtc->crtc_id;
 148
 149         if (radeon_encoder->flags & RADEON_USE_RMX) {
 150                 if (radeon_encoder->rmx_type == RMX_FULL)
 151                         args.ucEnable = ATOM_SCALER_EXPANSION;
 152                 else if (radeon_encoder->rmx_type == RMX_CENTER)
 153                         args.ucEnable = ATOM_SCALER_CENTER;
 154         } else
 155                 args.ucEnable = ATOM_SCALER_DISABLE;
 156
 157         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 158 }
 159
 160 void atombios_set_crtc_source(struct drm_encoder *encoder, int source)
 161 {
 162         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
 163         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 164         struct drm_radeon_private *dev_priv = encoder->dev->dev_private;
 165         uint8_t frev, crev;
 166         SELECT_CRTC_SOURCE_PS_ALLOCATION crtc_src_param;
 167         SELECT_CRTC_SOURCE_PARAMETERS_V2 crtc_src_param2;
 168         uint32_t *param = NULL;
 169
 170         atom_parse_cmd_header(dev_priv->mode_info.atom_context, index, &frev, &crev);
 171         switch (frev) {
 172         case 1: {
 173                 switch (crev) {
 174                 case 0:
 175                 case 1:
 176                 default:
 177                         memset(&crtc_src_param, 0, sizeof(crtc_src_param));
 178                         crtc_src_param.ucCRTC = radeon_crtc->crtc_id;
 179                         crtc_src_param.ucDevice = source;
 180                         param = (uint32_t *)&crtc_src_param;
 181                         break;
 182                 case 2:
 183                         memset(&crtc_src_param2, 0, sizeof(crtc_src_param2));
 184                         crtc_src_param2.ucCRTC = radeon_crtc->crtc_id;
 185                         crtc_src_param2.ucEncoderID = source;
 186                         switch (source) {
 187                         case ATOM_DEVICE_CRT1_INDEX:
 188                         case ATOM_DEVICE_CRT2_INDEX:
 189                                 crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
 190                                 break;
 191                         case ATOM_DEVICE_DFP1_INDEX:
 192                         case ATOM_DEVICE_DFP2_INDEX:
 193                         case ATOM_DEVICE_DFP3_INDEX:
 194                                 crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_DVI;
 195                                 // TODO ENCODER MODE
 196                                 break;
 197                         case ATOM_DEVICE_LCD1_INDEX:
 198                                 crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
 199                                 break;
 200                         case ATOM_DEVICE_TV1_INDEX:
 201                                 crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_TV;
 202                                 break;
 203                         case ATOM_DEVICE_CV_INDEX:
 204                                 crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_CV;
 205                                 break;
 206                         }
 207                         param = (uint32_t *)&crtc_src_param2;
 208                         break;
 209                 }
 210         }
 211                 break;
 212         default:
 213                 return;
 214         }
 215
 216         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)param);
 217
 218 }
 219
 220 static void radeon_dfp_disable_dither(struct drm_encoder *encoder, int device)
 221 {
 222         struct drm_device *dev = encoder->dev;
 223         struct drm_radeon_private *dev_priv = dev->dev_private;
 224
 225         switch (device) {
 226         case ATOM_DEVICE_DFP1_INDEX:
 227                 RADEON_WRITE(AVIVO_TMDSA_BIT_DEPTH_CONTROL, 0); /* TMDSA */
 228                 break;
 229         case ATOM_DEVICE_DFP2_INDEX:
 230                 if ((dev_priv->chip_family == CHIP_RS600) ||
 231                     (dev_priv->chip_family == CHIP_RS690) ||
 232                     (dev_priv->chip_family == CHIP_RS740))
 233                         RADEON_WRITE(AVIVO_DDIA_BIT_DEPTH_CONTROL, 0); /* DDIA */
 234                 else
 235                         RADEON_WRITE(AVIVO_DVOA_BIT_DEPTH_CONTROL, 0); /* DVO */
 236                 break;
 237                 /*case ATOM_DEVICE_LCD1_INDEX:*/ /* LVDS panels need dither enabled */
 238         case ATOM_DEVICE_DFP3_INDEX:
 239                 RADEON_WRITE(AVIVO_LVTMA_BIT_DEPTH_CONTROL, 0); /* LVTMA */
 240                 break;
 241         default:
 242                 break;
 243         }
 244 }
 245
 246
 247 static void radeon_lvtma_mode_set(struct drm_encoder *encoder,
 248                                   struct drm_display_mode *mode,
 249                                   struct drm_display_mode *adjusted_mode)
 250 {
 251         struct drm_device *dev = encoder->dev;
 252         struct drm_radeon_private *dev_priv = dev->dev_private;
 253         LVDS_ENCODER_CONTROL_PS_ALLOCATION args;
 254         int index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 255
 256         memset(&args, 0, sizeof(args));
 257         atombios_scaler_setup(encoder, mode);
 258         atombios_set_crtc_source(encoder, ATOM_DEVICE_LCD1_INDEX);
 259
 260         args.ucAction = 1;
 261         if (adjusted_mode->clock > 165000)
 262                 args.ucMisc = 1;
 263         else
 264                 args.ucMisc = 0;
 265         args.usPixelClock = cpu_to_le16(adjusted_mode->clock / 10);
 266
 267         printk("executing set LVDS encoder\n");
 268         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 269 }
 270
 271
 272 static void radeon_lvtma_dpms(struct drm_encoder *encoder, int mode)
 273 {
 274         struct drm_device *dev = encoder->dev;
 275         struct drm_radeon_private *dev_priv = dev->dev_private;
 276         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 277         int index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 278         uint32_t bios_2_scratch, bios_3_scratch;
 279
 280         if (dev_priv->chip_family >= CHIP_R600) {
 281                 bios_2_scratch = RADEON_READ(R600_BIOS_2_SCRATCH);
 282                 bios_3_scratch = RADEON_READ(R600_BIOS_3_SCRATCH);
 283         } else {
 284                 bios_2_scratch = RADEON_READ(RADEON_BIOS_2_SCRATCH);
 285                 bios_3_scratch = RADEON_READ(RADEON_BIOS_3_SCRATCH);
 286         }
 287
 288         bios_2_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
 289         bios_3_scratch |= (radeon_crtc->crtc_id << 17);
 290
 291         switch(mode) {
 292         case DRM_MODE_DPMS_ON:
 293                 atombios_display_device_control(encoder, index, ATOM_ENABLE);
 294                 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
 295                 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
 296                 break;
 297         case DRM_MODE_DPMS_STANDBY:
 298         case DRM_MODE_DPMS_SUSPEND:
 299         case DRM_MODE_DPMS_OFF:
 300                 atombios_display_device_control(encoder, index, ATOM_DISABLE);
 301                 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
 302                 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
 303                 break;
 304         }
 305
 306         if (dev_priv->chip_family >= CHIP_R600) {
 307                 RADEON_WRITE(R600_BIOS_2_SCRATCH, bios_2_scratch);
 308                 RADEON_WRITE(R600_BIOS_3_SCRATCH, bios_3_scratch);
 309         } else {
 310                 RADEON_WRITE(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
 311                 RADEON_WRITE(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
 312         }
 313 }
 314
 315 static bool radeon_lvtma_mode_fixup(struct drm_encoder *encoder,
 316                                     struct drm_display_mode *mode,
 317                                     struct drm_display_mode *adjusted_mode)
 318 {
 319         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 320
 321         radeon_encoder->flags &= ~RADEON_USE_RMX;
 322
 323         if (radeon_encoder->rmx_type != RMX_OFF)
 324                 radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
 325
 326         return true;
 327 }
 328
 329 static void radeon_lvtma_prepare(struct drm_encoder *encoder)
 330 {
 331         radeon_atom_output_lock(encoder, true);
 332         radeon_lvtma_dpms(encoder, DRM_MODE_DPMS_OFF);
 333 }
 334
 335 static void radeon_lvtma_commit(struct drm_encoder *encoder)
 336 {
 337         radeon_lvtma_dpms(encoder, DRM_MODE_DPMS_ON);
 338         radeon_atom_output_lock(encoder, false);
 339 }
 340
 341 static const struct drm_encoder_helper_funcs radeon_atom_lvtma_helper_funcs = {
 342         .dpms = radeon_lvtma_dpms,
 343         .mode_fixup = radeon_lvtma_mode_fixup,
 344         .prepare = radeon_lvtma_prepare,
 345         .mode_set = radeon_lvtma_mode_set,
 346         .commit = radeon_lvtma_commit,
 347 };
 348
 349 void radeon_enc_destroy(struct drm_encoder *encoder)
 350 {
 351         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 352         drm_encoder_cleanup(encoder);
 353         kfree(radeon_encoder);
 354 }
 355
 356 static const struct drm_encoder_funcs radeon_atom_lvtma_enc_funcs = {
 357         .destroy = radeon_enc_destroy,
 358 };
 359
 360 struct drm_encoder *radeon_encoder_lvtma_add(struct drm_device *dev, int bios_index)
 361 {
 362         struct drm_radeon_private *dev_priv = dev->dev_private;
 363         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 364         struct radeon_encoder *radeon_encoder;
 365         struct drm_encoder *encoder;
 366         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 367         if (!radeon_encoder) {
 368                 return NULL;
 369         }
 370
 371         encoder = &radeon_encoder->base;
 372
 373         encoder->possible_crtcs = 0x3;
 374         encoder->possible_clones = 0;
 375         drm_encoder_init(dev, encoder, &radeon_atom_lvtma_enc_funcs,
 376                          DRM_MODE_ENCODER_LVDS);
 377
 378         drm_encoder_helper_add(encoder, &radeon_atom_lvtma_helper_funcs);
 379         radeon_encoder->atom_device = mode_info->bios_connector[bios_index].devices;
 380
 381         /* TODO get the LVDS info from the BIOS for panel size etc. */
 382         /* get the lvds info from the bios */
 383         radeon_get_lvds_info(radeon_encoder);
 384
 385         /* LVDS gets default RMX full scaling */
 386         radeon_encoder->rmx_type = RMX_FULL;
 387
 388         return encoder;
 389 }
 390
 391 static void radeon_atom_dac_dpms(struct drm_encoder *encoder, int mode)
 392 {
 393         struct drm_device *dev = encoder->dev;
 394         struct drm_radeon_private *dev_priv = dev->dev_private;
 395         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 396         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 397         int atom_type = -1;
 398         int index;
 399         uint32_t bios_2_scratch, bios_3_scratch;
 400
 401         atom_type = atom_dac_find_atom_type(radeon_encoder, NULL);
 402         if (atom_type == -1)
 403                 return;
 404
 405         if (dev_priv->chip_family >= CHIP_R600) {
 406                 bios_2_scratch = RADEON_READ(R600_BIOS_2_SCRATCH);
 407                 bios_3_scratch = RADEON_READ(R600_BIOS_3_SCRATCH);
 408         } else {
 409                 bios_2_scratch = RADEON_READ(RADEON_BIOS_2_SCRATCH);
 410                 bios_3_scratch = RADEON_READ(RADEON_BIOS_3_SCRATCH);
 411         }
 412
 413         switch(atom_type) {
 414         case ATOM_DEVICE_CRT1_INDEX:
 415                 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
 416                 bios_2_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
 417                 bios_3_scratch |= (radeon_crtc->crtc_id << 16);
 418                 switch(mode) {
 419                 case DRM_MODE_DPMS_ON:
 420                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
 421                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
 422                         break;
 423                 case DRM_MODE_DPMS_STANDBY:
 424                 case DRM_MODE_DPMS_SUSPEND:
 425                 case DRM_MODE_DPMS_OFF:
 426                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
 427                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
 428                         break;
 429                 }
 430                 break;
 431         case ATOM_DEVICE_CRT2_INDEX:
 432                 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
 433                 bios_2_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
 434                 bios_3_scratch |= (radeon_crtc->crtc_id << 20);
 435                 switch(mode) {
 436                 case DRM_MODE_DPMS_ON:
 437                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
 438                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
 439                         break;
 440                 case DRM_MODE_DPMS_STANDBY:
 441                 case DRM_MODE_DPMS_SUSPEND:
 442                 case DRM_MODE_DPMS_OFF:
 443                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
 444                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
 445                         break;
 446                 }
 447                 break;
 448         case ATOM_DEVICE_TV1_INDEX:
 449                 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
 450                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
 451                 bios_3_scratch |= (radeon_crtc->crtc_id << 18);
 452                 switch(mode) {
 453                 case DRM_MODE_DPMS_ON:
 454                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
 455                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
 456                         break;
 457                 case DRM_MODE_DPMS_STANDBY:
 458                 case DRM_MODE_DPMS_SUSPEND:
 459                 case DRM_MODE_DPMS_OFF:
 460                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
 461                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
 462                         break;
 463                 }
 464                 break;
 465         case ATOM_DEVICE_CV_INDEX:
 466                 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
 467                 bios_2_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
 468                 bios_3_scratch |= (radeon_crtc->crtc_id << 24);
 469                 switch(mode) {
 470                 case DRM_MODE_DPMS_ON:
 471                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
 472                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
 473                         break;
 474                 case DRM_MODE_DPMS_STANDBY:
 475                 case DRM_MODE_DPMS_SUSPEND:
 476                 case DRM_MODE_DPMS_OFF:
 477                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
 478                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
 479                         break;
 480                 }
 481                 break;
 482         default:
 483                 return;
 484         }
 485
 486         switch(mode) {
 487         case DRM_MODE_DPMS_ON:
 488                 atombios_display_device_control(encoder, index, ATOM_ENABLE);
 489                 break;
 490         case DRM_MODE_DPMS_STANDBY:
 491         case DRM_MODE_DPMS_SUSPEND:
 492         case DRM_MODE_DPMS_OFF:
 493                 atombios_display_device_control(encoder, index, ATOM_DISABLE);
 494                 break;
 495         }
 496
 497         if (dev_priv->chip_family >= CHIP_R600) {
 498                 RADEON_WRITE(R600_BIOS_2_SCRATCH, bios_2_scratch);
 499                 RADEON_WRITE(R600_BIOS_3_SCRATCH, bios_3_scratch);
 500         } else {
 501                 RADEON_WRITE(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
 502                 RADEON_WRITE(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
 503         }
 504 }
 505
 506 static bool radeon_atom_dac_mode_fixup(struct drm_encoder *encoder,
 507                                   struct drm_display_mode *mode,
 508                                   struct drm_display_mode *adjusted_mode)
 509 {
 510         return true;
 511 }
 512
 513 static void radeon_atom_dac_prepare(struct drm_encoder *encoder)
 514 {
 515         radeon_atom_output_lock(encoder, true);
 516         radeon_atom_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 517 }
 518
 519 static void radeon_atom_dac_commit(struct drm_encoder *encoder)
 520 {
 521         radeon_atom_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 522         radeon_atom_output_lock(encoder, false);
 523 }
 524
 525 static int atombios_dac_setup(struct drm_encoder *encoder,
 526                               struct drm_display_mode *mode,
 527                               int atom_type)
 528 {
 529         struct drm_device *dev = encoder->dev;
 530         struct drm_radeon_private *dev_priv = dev->dev_private;
 531         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 532         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 533         int id = (radeon_encoder->type.dac == DAC_TVDAC);
 534         int index;
 535
 536         memset(&args, 0, sizeof(args));
 537         if (id == 0)
 538                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 539         else
 540                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 541
 542         args.ucAction = 1;
 543         args.usPixelClock = cpu_to_le16(mode->clock / 10);
 544         if ((atom_type == ATOM_DEVICE_CRT1_INDEX) ||
 545             (atom_type == ATOM_DEVICE_CRT2_INDEX))
 546                 args.ucDacStandard = id ? ATOM_DAC2_PS2 : ATOM_DAC1_PS2;
 547         else if (atom_type == ATOM_DEVICE_CV_INDEX)
 548                 args.ucDacStandard = id ? ATOM_DAC2_CV : ATOM_DAC1_CV;
 549         else if (atom_type == ATOM_DEVICE_TV1_INDEX)
 550                 args.ucDacStandard = id ? ATOM_DAC2_NTSC : ATOM_DAC1_NTSC;
 551         /* TODO PAL */
 552         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 553
 554         return 0;
 555 }
 556
 557 static int atombios_tv1_setup(struct drm_encoder *encoder,
 558                               struct drm_display_mode *mode,
 559                               int atom_type)
 560 {
 561         struct drm_device *dev = encoder->dev;
 562         struct drm_radeon_private *dev_priv = dev->dev_private;
 563         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 564         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 565         int index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 566
 567         memset(&args, 0, sizeof(args));
 568         args.sTVEncoder.ucAction = 1;
 569         if (atom_type == ATOM_DEVICE_CV_INDEX)
 570                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 571         else {
 572                 // TODO PAL
 573                 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 574         }
 575
 576         args.sTVEncoder.usPixelClock = cpu_to_le16(mode->clock / 10);
 577
 578         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 579         return 0;
 580 }
 581
 582 static void radeon_atom_dac_mode_set(struct drm_encoder *encoder,
 583                                      struct drm_display_mode *mode,
 584                                      struct drm_display_mode *adjusted_mode)
 585 {
 586         struct drm_device *dev = encoder->dev;
 587         struct drm_radeon_private *dev_priv = dev->dev_private;
 588         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 589         int atom_type = -1;
 590
 591         atom_type = atom_dac_find_atom_type(radeon_encoder, NULL);
 592         if (atom_type == -1)
 593                 return;
 594
 595         atombios_scaler_setup(encoder, mode);
 596         atombios_set_crtc_source(encoder, atom_type);
 597
 598         atombios_dac_setup(encoder, adjusted_mode, atom_type);
 599         if ((atom_type == ATOM_DEVICE_TV1_INDEX) ||
 600             (atom_type == ATOM_DEVICE_CV_INDEX))
 601                 atombios_tv1_setup(encoder, adjusted_mode, atom_type);
 602
 603 }
 604
 605 static bool atom_dac_load_detect(struct drm_encoder *encoder, int atom_devices)
 606 {
 607         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 608         struct drm_device *dev = encoder->dev;
 609         struct drm_radeon_private *dev_priv = dev->dev_private;
 610         DAC_LOAD_DETECTION_PS_ALLOCATION args;
 611         int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
 612
 613         memset(&args, 0, sizeof(args));
 614         args.sDacload.ucMisc = 0;
 615         args.sDacload.ucDacType = (radeon_encoder->type.dac == DAC_PRIMARY) ? ATOM_DAC_A : ATOM_DAC_B;
 616
 617         if (atom_devices & ATOM_DEVICE_CRT1_SUPPORT)
 618                 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
 619         else if (atom_devices & ATOM_DEVICE_CRT2_SUPPORT)
 620                 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
 621         else if (atom_devices & ATOM_DEVICE_CV_SUPPORT) {
 622                 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
 623                 if (radeon_is_dce3(dev_priv))
 624                         args.sDacload.ucMisc = 1;
 625         } else if (atom_devices & ATOM_DEVICE_TV1_SUPPORT) {
 626                 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
 627                 if (radeon_is_dce3(dev_priv))
 628                         args.sDacload.ucMisc = 1;
 629         } else
 630                 return false;
 631
 632         DRM_DEBUG("writing %x %x\n", args.sDacload.usDeviceID, args.sDacload.ucDacType);
 633         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 634         return true;
 635 }
 636
 637 static enum drm_connector_status radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 638 {
 639         struct drm_device *dev = encoder->dev;
 640         struct drm_radeon_private *dev_priv = dev->dev_private;
 641         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 642         int atom_type = -1;
 643         uint32_t bios_0_scratch;
 644
 645         atom_type = atom_dac_find_atom_type(radeon_encoder, connector);
 646         if (atom_type == -1) {
 647                 DRM_DEBUG("exit after find \n");
 648                 return connector_status_unknown;
 649         }
 650
 651         if(!atom_dac_load_detect(encoder, (1 << atom_type))) {
 652                 DRM_DEBUG("detect returned false \n");
 653                 return connector_status_unknown;
 654         }
 655
 656
 657         if (dev_priv->chip_family >= CHIP_R600)
 658                 bios_0_scratch = RADEON_READ(R600_BIOS_0_SCRATCH);
 659         else
 660                 bios_0_scratch = RADEON_READ(RADEON_BIOS_0_SCRATCH);
 661
 662         DRM_DEBUG("Bios 0 scratch %x\n", bios_0_scratch);
 663         if (radeon_encoder->atom_device & ATOM_DEVICE_CRT1_SUPPORT) {
 664                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
 665                         return connector_status_connected;
 666         } else if (radeon_encoder->atom_device & ATOM_DEVICE_CRT2_SUPPORT) {
 667                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
 668                         return connector_status_connected;
 669         } else if (radeon_encoder->atom_device & ATOM_DEVICE_CV_SUPPORT) {
 670                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
 671                         return connector_status_connected;
 672         } else if (radeon_encoder->atom_device & ATOM_DEVICE_TV1_SUPPORT) {
 673                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
 674                         return connector_status_connected; // CTV
 675                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
 676                         return connector_status_connected; // STV
 677         }
 678         return connector_status_disconnected;
 679 }
 680
 681 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
 682         .dpms = radeon_atom_dac_dpms,
 683         .mode_fixup = radeon_atom_dac_mode_fixup,
 684         .prepare = radeon_atom_dac_prepare,
 685         .mode_set = radeon_atom_dac_mode_set,
 686         .commit = radeon_atom_dac_commit,
 687         .detect = radeon_atom_dac_detect,
 688 };
 689
 690 static const struct drm_encoder_funcs radeon_atom_dac_enc_funcs = {
 691         . destroy = radeon_enc_destroy,
 692 };
 693
 694
 695 static void atombios_tmds1_setup(struct drm_encoder *encoder,
 696                                  struct drm_display_mode *mode)
 697 {
 698         struct drm_device *dev = encoder->dev;
 699         struct drm_radeon_private *dev_priv = dev->dev_private;
 700         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 701         TMDS1_ENCODER_CONTROL_PS_ALLOCATION args;
 702         int index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 703
 704         memset(&args, 0, sizeof(args));
 705         args.ucAction = 1;
 706         if (mode->clock > 165000)
 707                 args.ucMisc = 1;
 708         else
 709                 args.ucMisc = 0;
 710
 711         args.usPixelClock = cpu_to_le16(mode->clock / 10);
 712
 713         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 714 }
 715
 716 static void atombios_tmds2_setup(struct drm_encoder *encoder,
 717                                  struct drm_display_mode *mode)
 718 {
 719         struct drm_device *dev = encoder->dev;
 720         struct drm_radeon_private *dev_priv = dev->dev_private;
 721         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 722         TMDS2_ENCODER_CONTROL_PS_ALLOCATION args;
 723         int index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 724
 725         memset(&args, 0, sizeof(args));
 726         args.ucAction = 1;
 727         if (mode->clock > 165000)
 728                 args.ucMisc = 1;
 729         else
 730                 args.ucMisc = 0;
 731
 732         args.usPixelClock = cpu_to_le16(mode->clock / 10);
 733
 734         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 735 }
 736
 737
 738 static void atombios_ext_tmds_setup(struct drm_encoder *encoder,
 739                                     struct drm_display_mode *mode)
 740 {
 741         struct drm_device *dev = encoder->dev;
 742         struct drm_radeon_private *dev_priv = dev->dev_private;
 743         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 744         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
 745         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 746
 747         memset(&args, 0, sizeof(args));
 748         args.sXTmdsEncoder.ucEnable = 1;
 749
 750         if (mode->clock > 165000)
 751                 args.sXTmdsEncoder.ucMisc = 1;
 752         else
 753                 args.sXTmdsEncoder.ucMisc = 0;
 754
 755         // TODO 6-bit DAC
 756 //      args.usPixelClock = cpu_to_le16(mode->clock / 10);
 757
 758         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 759 }
 760
 761 static void atombios_dig1_setup(struct drm_encoder *encoder,
 762                                 struct drm_display_mode *mode)
 763 {
 764         struct drm_device *dev = encoder->dev;
 765         struct drm_radeon_private *dev_priv = dev->dev_private;
 766         DIG_ENCODER_CONTROL_PS_ALLOCATION args;
 767         int index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 768
 769         args.ucAction = 1;
 770         args.usPixelClock = mode->clock / 10;
 771         args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
 772
 773         // TODO coherent mode
 774 //      if (encoder->coherent_mode)
 775 //              args.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 776
 777         if (mode->clock > 165000) {
 778                 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA_B;
 779                 args.ucLaneNum = 8;
 780         } else {
 781                 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 782                 args.ucLaneNum = 4;
 783         }
 784
 785         // TODO Encoder MODE
 786         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 787 }
 788
 789 static void atombios_ddia_setup(struct drm_encoder *encoder,
 790                                 struct drm_display_mode *mode)
 791 {
 792         struct drm_device *dev = encoder->dev;
 793         struct drm_radeon_private *dev_priv = dev->dev_private;
 794         DVO_ENCODER_CONTROL_PS_ALLOCATION args;
 795         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 796
 797         args.sDVOEncoder.ucAction = ATOM_ENABLE;
 798         args.sDVOEncoder.usPixelClock = mode->clock / 10;
 799
 800         if (mode->clock > 165000)
 801                 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
 802         else
 803                 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = 0;
 804
 805         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 806 }
 807
 808 struct drm_encoder *radeon_encoder_atom_dac_add(struct drm_device *dev, int bios_index, int dac_type, int with_tv)
 809 {
 810         struct drm_radeon_private *dev_priv = dev->dev_private;
 811         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 812         struct radeon_encoder *radeon_encoder = NULL;
 813         struct drm_encoder *encoder;
 814         int type = with_tv ? DRM_MODE_ENCODER_TVDAC : DRM_MODE_ENCODER_DAC;
 815         int found = 0;
 816         int digital_enc_mask = ~(ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT |
 817                                 ATOM_DEVICE_LCD1_SUPPORT);
 818         /* we may already have added this encoder */
 819         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 820                 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC ||
 821                     encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
 822                         continue;
 823
 824                 radeon_encoder = to_radeon_encoder(encoder);
 825                 if (radeon_encoder->type.dac == dac_type) {
 826                         found = 1;
 827                         break;
 828                 }
 829         }
 830
 831         if (found) {
 832                 /* upgrade to a TV controlling DAC */
 833                 if (type == DRM_MODE_ENCODER_TVDAC)
 834                         encoder->encoder_type = type;
 835                 radeon_encoder->atom_device |= mode_info->bios_connector[bios_index].devices;
 836                 radeon_encoder->atom_device &= digital_enc_mask;
 837                 return encoder;
 838         }
 839
 840         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 841         if (!radeon_encoder) {
 842                 return NULL;
 843         }
 844
 845         encoder = &radeon_encoder->base;
 846
 847         encoder->possible_crtcs = 0x3;
 848         encoder->possible_clones = 0;
 849         drm_encoder_init(dev, encoder, &radeon_atom_dac_enc_funcs,
 850                          type);
 851
 852         drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
 853         radeon_encoder->type.dac = dac_type;
 854         radeon_encoder->atom_device = mode_info->bios_connector[bios_index].devices;
 855
 856         /* mask off any digital encoders */
 857         radeon_encoder->atom_device &= digital_enc_mask;
 858         return encoder;
 859 }
 860
 861 static void radeon_atom_tmds_dpms(struct drm_encoder *encoder, int mode)
 862 {
 863         struct drm_device *dev = encoder->dev;
 864         struct drm_radeon_private *dev_priv = dev->dev_private;
 865         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 866         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 867         int atom_type = -1;
 868         int index = -1;
 869         uint32_t bios_2_scratch, bios_3_scratch;
 870
 871         if (radeon_encoder->atom_device & ATOM_DEVICE_DFP1_SUPPORT)
 872                 atom_type = ATOM_DEVICE_DFP1_INDEX;
 873         if (radeon_encoder->atom_device & ATOM_DEVICE_DFP2_SUPPORT)
 874                 atom_type = ATOM_DEVICE_DFP2_INDEX;
 875         if (radeon_encoder->atom_device & ATOM_DEVICE_DFP3_SUPPORT)
 876                 atom_type = ATOM_DEVICE_DFP3_INDEX;
 877
 878         if (atom_type == -1)
 879                 return;
 880
 881         if (dev_priv->chip_family >= CHIP_R600) {
 882                 bios_2_scratch = RADEON_READ(R600_BIOS_2_SCRATCH);
 883                 bios_3_scratch = RADEON_READ(R600_BIOS_3_SCRATCH);
 884         } else {
 885                 bios_2_scratch = RADEON_READ(RADEON_BIOS_2_SCRATCH);
 886                 bios_3_scratch = RADEON_READ(RADEON_BIOS_3_SCRATCH);
 887         }
 888
 889         switch(atom_type) {
 890         case ATOM_DEVICE_DFP1_INDEX:
 891                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
 892                 bios_2_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
 893                 bios_3_scratch |= (radeon_crtc->crtc_id << 19);
 894                 switch(mode) {
 895                 case DRM_MODE_DPMS_ON:
 896                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
 897                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
 898                         break;
 899                 case DRM_MODE_DPMS_STANDBY:
 900                 case DRM_MODE_DPMS_SUSPEND:
 901                 case DRM_MODE_DPMS_OFF:
 902                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
 903                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
 904                         break;
 905                 }
 906                 break;
 907         case ATOM_DEVICE_DFP2_INDEX:
 908                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
 909                 bios_2_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
 910                 bios_3_scratch |= (radeon_crtc->crtc_id << 23);
 911                 switch(mode) {
 912                 case DRM_MODE_DPMS_ON:
 913                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
 914                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
 915                         break;
 916                 case DRM_MODE_DPMS_STANDBY:
 917                 case DRM_MODE_DPMS_SUSPEND:
 918                 case DRM_MODE_DPMS_OFF:
 919                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
 920                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
 921                         break;
 922                 }
 923                 break;
 924         case ATOM_DEVICE_DFP3_INDEX:
 925                 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
 926                 bios_2_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
 927                 bios_3_scratch |= (radeon_crtc->crtc_id << 25);
 928                 switch(mode) {
 929                 case DRM_MODE_DPMS_ON:
 930                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
 931                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
 932                         break;
 933                 case DRM_MODE_DPMS_STANDBY:
 934                 case DRM_MODE_DPMS_SUSPEND:
 935                 case DRM_MODE_DPMS_OFF:
 936                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
 937                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
 938                         break;
 939                 }
 940                 break;
 941         }
 942
 943         if (index == -1)
 944                 return;
 945
 946         switch(mode) {
 947         case DRM_MODE_DPMS_ON:
 948                 atombios_display_device_control(encoder, index, ATOM_ENABLE);
 949                 break;
 950         case DRM_MODE_DPMS_STANDBY:
 951         case DRM_MODE_DPMS_SUSPEND:
 952         case DRM_MODE_DPMS_OFF:
 953                 atombios_display_device_control(encoder, index, ATOM_DISABLE);
 954                 break;
 955         }
 956
 957         if (dev_priv->chip_family >= CHIP_R600) {
 958                 RADEON_WRITE(R600_BIOS_2_SCRATCH, bios_2_scratch);
 959                 RADEON_WRITE(R600_BIOS_3_SCRATCH, bios_3_scratch);
 960         } else {
 961                 RADEON_WRITE(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
 962                 RADEON_WRITE(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
 963         }
 964 }
 965
 966 static bool radeon_atom_tmds_mode_fixup(struct drm_encoder *encoder,
 967                                   struct drm_display_mode *mode,
 968                                   struct drm_display_mode *adjusted_mode)
 969 {
 970         return true;
 971 }
 972
 973 static void radeon_atom_tmds_mode_set(struct drm_encoder *encoder,
 974                                       struct drm_display_mode *mode,
 975                                       struct drm_display_mode *adjusted_mode)
 976 {
 977         struct drm_device *dev = encoder->dev;
 978         struct drm_radeon_private *dev_priv = dev->dev_private;
 979         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 980         int atom_type;
 981
 982         if (radeon_encoder->atom_device & ATOM_DEVICE_DFP1_SUPPORT)
 983                 atom_type = ATOM_DEVICE_DFP1_INDEX;
 984         if (radeon_encoder->atom_device & ATOM_DEVICE_DFP2_SUPPORT)
 985                 atom_type = ATOM_DEVICE_DFP2_INDEX;
 986         if (radeon_encoder->atom_device & ATOM_DEVICE_DFP3_SUPPORT)
 987                 atom_type = ATOM_DEVICE_DFP3_INDEX;
 988
 989         atombios_scaler_setup(encoder, mode);
 990         atombios_set_crtc_source(encoder, atom_type);
 991
 992         if (atom_type == ATOM_DEVICE_DFP1_INDEX)
 993                 atombios_tmds1_setup(encoder, adjusted_mode);
 994         if (atom_type == ATOM_DEVICE_DFP2_INDEX) {
 995                 if ((dev_priv->chip_family == CHIP_RS600) ||
 996                     (dev_priv->chip_family == CHIP_RS690) ||
 997                     (dev_priv->chip_family == CHIP_RS740))
 998                         atombios_ddia_setup(encoder, adjusted_mode);
 999                 else
1000                         atombios_ext_tmds_setup(encoder, adjusted_mode);
1001         }
1002         if (atom_type == ATOM_DEVICE_DFP3_INDEX)
1003                 atombios_tmds2_setup(encoder, adjusted_mode);
1004         radeon_dfp_disable_dither(encoder, atom_type);
1005
1006
1007 }
1008
1009 static void radeon_atom_tmds_prepare(struct drm_encoder *encoder)
1010 {
1011         radeon_atom_output_lock(encoder, true);
1012         radeon_atom_tmds_dpms(encoder, DRM_MODE_DPMS_OFF);
1013 }
1014
1015 static void radeon_atom_tmds_commit(struct drm_encoder *encoder)
1016 {
1017         radeon_atom_tmds_dpms(encoder, DRM_MODE_DPMS_ON);
1018         radeon_atom_output_lock(encoder, false);
1019 }
1020
1021 static const struct drm_encoder_helper_funcs radeon_atom_tmds_helper_funcs = {
1022         .dpms = radeon_atom_tmds_dpms,
1023         .mode_fixup = radeon_atom_tmds_mode_fixup,
1024         .prepare = radeon_atom_tmds_prepare,
1025         .mode_set = radeon_atom_tmds_mode_set,
1026         .commit = radeon_atom_tmds_commit,
1027         /* no detect for TMDS */
1028 };
1029
1030 static const struct drm_encoder_funcs radeon_atom_tmds_enc_funcs = {
1031         . destroy = radeon_enc_destroy,
1032 };
1033
1034 struct drm_encoder *radeon_encoder_atom_tmds_add(struct drm_device *dev, int bios_index, int tmds_type)
1035 {
1036         struct drm_radeon_private *dev_priv = dev->dev_private;
1037         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
1038         struct radeon_encoder *radeon_encoder = NULL;
1039         struct drm_encoder *encoder;
1040         int analog_enc_mask = ~(ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT);
1041
1042                 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1043         if (!radeon_encoder) {
1044                 return NULL;
1045         }
1046
1047         encoder = &radeon_encoder->base;
1048
1049         encoder->possible_crtcs = 0x3;
1050         encoder->possible_clones = 0;
1051         drm_encoder_init(dev, encoder, &radeon_atom_tmds_enc_funcs,
1052                          DRM_MODE_ENCODER_TMDS);
1053
1054         drm_encoder_helper_add(encoder, &radeon_atom_tmds_helper_funcs);
1055
1056         radeon_encoder->atom_device = mode_info->bios_connector[bios_index].devices;
1057
1058         /* mask off any analog encoders */
1059         radeon_encoder->atom_device &= analog_enc_mask;
1060         return encoder;
1061 }