linux-core/radeon_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon_drv.h"
  30
  31 extern int atom_debug;
  32
  33 void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
  34                            struct drm_display_mode *mode,
  35                            struct drm_display_mode *adjusted_mode)
  36 {
  37         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  38         if (mode->hdisplay < radeon_encoder->panel_xres ||
  39             mode->vdisplay < radeon_encoder->panel_yres) {
  40                 radeon_encoder->flags |= RADEON_USE_RMX;
  41                 adjusted_mode->hdisplay = radeon_encoder->panel_xres;
  42                 adjusted_mode->vdisplay = radeon_encoder->panel_yres;
  43                 adjusted_mode->htotal = radeon_encoder->panel_xres + radeon_encoder->hblank;
  44                 adjusted_mode->hsync_start = radeon_encoder->panel_xres + radeon_encoder->hoverplus;
  45                 adjusted_mode->hsync_end = adjusted_mode->hsync_start + radeon_encoder->hsync_width;
  46                 adjusted_mode->vtotal = radeon_encoder->panel_yres + radeon_encoder->vblank;
  47                 adjusted_mode->vsync_start = radeon_encoder->panel_yres + radeon_encoder->voverplus;
  48                 adjusted_mode->vsync_end = adjusted_mode->vsync_start + radeon_encoder->vsync_width;
  49                 /* update crtc values */
  50                 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
  51                 /* adjust crtc values */
  52                 adjusted_mode->crtc_hdisplay = radeon_encoder->panel_xres;
  53                 adjusted_mode->crtc_vdisplay = radeon_encoder->panel_yres;
  54                 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + radeon_encoder->hblank;
  55                 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + radeon_encoder->hoverplus;
  56                 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + radeon_encoder->hsync_width;
  57                 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + radeon_encoder->vblank;
  58                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + radeon_encoder->voverplus;
  59                 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + radeon_encoder->vsync_width;
  60         } else {
  61                 adjusted_mode->htotal = radeon_encoder->panel_xres + radeon_encoder->hblank;
  62                 adjusted_mode->hsync_start = radeon_encoder->panel_xres + radeon_encoder->hoverplus;
  63                 adjusted_mode->hsync_end = adjusted_mode->hsync_start + radeon_encoder->hsync_width;
  64                 adjusted_mode->vtotal = radeon_encoder->panel_yres + radeon_encoder->vblank;
  65                 adjusted_mode->vsync_start = radeon_encoder->panel_yres + radeon_encoder->voverplus;
  66                 adjusted_mode->vsync_end = adjusted_mode->vsync_start + radeon_encoder->vsync_width;
  67                 /* update crtc values */
  68                 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
  69                 /* adjust crtc values */
  70                 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + radeon_encoder->hblank;
  71                 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + radeon_encoder->hoverplus;
  72                 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + radeon_encoder->hsync_width;
  73                 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + radeon_encoder->vblank;
  74                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + radeon_encoder->voverplus;
  75                 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + radeon_encoder->vsync_width;
  76         }
  77         adjusted_mode->clock = radeon_encoder->dotclock;
  78         adjusted_mode->flags = radeon_encoder->flags;
  79 }
  80
  81
  82 static int atom_dac_find_atom_type(struct radeon_encoder *radeon_encoder, struct drm_connector *connector)
  83 {
  84         struct drm_device *dev = radeon_encoder->base.dev;
  85         struct drm_connector *connector_find;
  86         int atom_type = -1;
  87
  88         if (!connector) {
  89                 list_for_each_entry(connector_find, &dev->mode_config.connector_list, head) {
  90                         if (connector_find->encoder == &radeon_encoder->base)
  91                                 connector = connector_find;
  92                 }
  93         }
  94         if (connector) {
  95                 /* look for the encoder in the connector list -
  96                    check if we the DAC is enabled on a VGA or STV/CTV or CV connector */
  97                 /* work out the ATOM_DEVICE bits */
  98                 switch (connector->connector_type) {
  99                 case CONNECTOR_VGA:
 100                 case CONNECTOR_DVI_I:
 101                 case CONNECTOR_DVI_A:
 102                         if (radeon_encoder->atom_device & ATOM_DEVICE_CRT1_SUPPORT)
 103                                 atom_type = ATOM_DEVICE_CRT1_INDEX;
 104                         else if (radeon_encoder->atom_device & ATOM_DEVICE_CRT2_SUPPORT)
 105                                 atom_type = ATOM_DEVICE_CRT2_INDEX;
 106                         break;
 107                 case CONNECTOR_STV:
 108                 case CONNECTOR_CTV:
 109                         if (radeon_encoder->atom_device & ATOM_DEVICE_TV1_SUPPORT)
 110                                 atom_type = ATOM_DEVICE_TV1_INDEX;
 111                         break;
 112                 case CONNECTOR_DIN:
 113                         if (radeon_encoder->atom_device & ATOM_DEVICE_TV1_SUPPORT)
 114                                 atom_type = ATOM_DEVICE_TV1_INDEX;
 115                         if (radeon_encoder->atom_device & ATOM_DEVICE_CV_SUPPORT)
 116                                 atom_type = ATOM_DEVICE_CV_INDEX;
 117                         break;
 118                 }
 119         }
 120
 121         return atom_type;
 122 }
 123
 124 /* LVTMA encoder for LVDS usage */
 125 static void atombios_display_device_control(struct drm_encoder *encoder, int index, uint8_t state)
 126 {
 127         struct drm_device *dev = encoder->dev;
 128         struct drm_radeon_private *dev_priv = dev->dev_private;
 129         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
 130
 131         memset(&args, 0, sizeof(args));
 132         args.ucAction = state;
 133
 134         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 135 }
 136
 137 static void atombios_scaler_setup(struct drm_encoder *encoder, struct drm_display_mode *mode)
 138 {
 139         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 140         struct drm_device *dev = encoder->dev;
 141         struct drm_radeon_private *dev_priv = dev->dev_private;
 142         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 143         ENABLE_SCALER_PS_ALLOCATION args;
 144         int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
 145
 146         memset(&args, 0, sizeof(args));
 147         args.ucScaler = radeon_crtc->crtc_id;
 148
 149         if (radeon_encoder->flags & RADEON_USE_RMX) {
 150                 if (radeon_encoder->rmx_type == RMX_FULL)
 151                         args.ucEnable = ATOM_SCALER_EXPANSION;
 152                 else if (radeon_encoder->rmx_type == RMX_CENTER)
 153                         args.ucEnable = ATOM_SCALER_CENTER;
 154         } else
 155                 args.ucEnable = ATOM_SCALER_DISABLE;
 156
 157         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 158 }
 159
 160 void atombios_set_crtc_source(struct drm_encoder *encoder, int source)
 161 {
 162         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
 163         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 164         struct drm_radeon_private *dev_priv = encoder->dev->dev_private;
 165         uint8_t frev, crev;
 166         SELECT_CRTC_SOURCE_PS_ALLOCATION crtc_src_param;
 167         SELECT_CRTC_SOURCE_PARAMETERS_V2 crtc_src_param2;
 168         uint32_t *param = NULL;
 169
 170         atom_parse_cmd_header(dev_priv->mode_info.atom_context, index, &frev, &crev);
 171         switch (frev) {
 172         case 1: {
 173                 switch (crev) {
 174                 case 0:
 175                 case 1:
 176                 default:
 177                         memset(&crtc_src_param, 0, sizeof(crtc_src_param));
 178                         crtc_src_param.ucCRTC = radeon_crtc->crtc_id;
 179                         crtc_src_param.ucDevice = source;
 180                         param = (uint32_t *)&crtc_src_param;
 181                         break;
 182                 case 2:
 183                         memset(&crtc_src_param2, 0, sizeof(crtc_src_param2));
 184                         crtc_src_param2.ucCRTC = radeon_crtc->crtc_id;
 185                         crtc_src_param2.ucEncoderID = source;
 186                         switch (source) {
 187                         case ATOM_DEVICE_CRT1_INDEX:
 188                         case ATOM_DEVICE_CRT2_INDEX:
 189                                 crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
 190                                 break;
 191                         case ATOM_DEVICE_DFP1_INDEX:
 192                         case ATOM_DEVICE_DFP2_INDEX:
 193                         case ATOM_DEVICE_DFP3_INDEX:
 194                                 crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_DVI;
 195                                 // TODO ENCODER MODE
 196                                 break;
 197                         case ATOM_DEVICE_LCD1_INDEX:
 198                                 crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
 199                                 break;
 200                         case ATOM_DEVICE_TV1_INDEX:
 201                                 crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_TV;
 202                                 break;
 203                         case ATOM_DEVICE_CV_INDEX:
 204                                 crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_CV;
 205                                 break;
 206                         }
 207                         param = (uint32_t *)&crtc_src_param2;
 208                         break;
 209                 }
 210         }
 211                 break;
 212         default:
 213                 return;
 214         }
 215
 216         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)param);
 217
 218 }
 219
 220 static void radeon_dfp_disable_dither(struct drm_encoder *encoder, int device)
 221 {
 222         struct drm_device *dev = encoder->dev;
 223         struct drm_radeon_private *dev_priv = dev->dev_private;
 224
 225         switch (device) {
 226         case ATOM_DEVICE_DFP1_INDEX:
 227                 RADEON_WRITE(AVIVO_TMDSA_BIT_DEPTH_CONTROL, 0); /* TMDSA */
 228                 break;
 229         case ATOM_DEVICE_DFP2_INDEX:
 230                 if ((dev_priv->chip_family == CHIP_RS600) ||
 231                     (dev_priv->chip_family == CHIP_RS690) ||
 232                     (dev_priv->chip_family == CHIP_RS740))
 233                         RADEON_WRITE(AVIVO_DDIA_BIT_DEPTH_CONTROL, 0); /* DDIA */
 234                 else
 235                         RADEON_WRITE(AVIVO_DVOA_BIT_DEPTH_CONTROL, 0); /* DVO */
 236                 break;
 237                 /*case ATOM_DEVICE_LCD1_INDEX:*/ /* LVDS panels need dither enabled */
 238         case ATOM_DEVICE_DFP3_INDEX:
 239                 RADEON_WRITE(AVIVO_LVTMA_BIT_DEPTH_CONTROL, 0); /* LVTMA */
 240                 break;
 241         default:
 242                 break;
 243         }
 244 }
 245
 246
 247 static void radeon_lvtma_mode_set(struct drm_encoder *encoder,
 248                                   struct drm_display_mode *mode,
 249                                   struct drm_display_mode *adjusted_mode)
 250 {
 251         struct drm_device *dev = encoder->dev;
 252         struct drm_radeon_private *dev_priv = dev->dev_private;
 253         LVDS_ENCODER_CONTROL_PS_ALLOCATION args;
 254         int index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 255
 256         memset(&args, 0, sizeof(args));
 257         atombios_scaler_setup(encoder, mode);
 258         atombios_set_crtc_source(encoder, ATOM_DEVICE_LCD1_INDEX);
 259
 260         args.ucAction = 1;
 261         if (adjusted_mode->clock > 165000)
 262                 args.ucMisc = 1;
 263         else
 264                 args.ucMisc = 0;
 265         args.usPixelClock = cpu_to_le16(adjusted_mode->clock / 10);
 266
 267         printk("executing set LVDS encoder\n");
 268         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 269 }
 270
 271
 272 static void radeon_lvtma_dpms(struct drm_encoder *encoder, int mode)
 273 {
 274         struct drm_device *dev = encoder->dev;
 275         struct drm_radeon_private *dev_priv = dev->dev_private;
 276         struct radeon_crtc *radeon_crtc;
 277         int index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 278         uint32_t bios_2_scratch, bios_3_scratch;
 279         int crtc_id = 0;
 280
 281         if (encoder->crtc) {
 282                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 283                 crtc_id = radeon_crtc->crtc_id;
 284         }
 285
 286         if (dev_priv->chip_family >= CHIP_R600) {
 287                 bios_2_scratch = RADEON_READ(R600_BIOS_2_SCRATCH);
 288                 bios_3_scratch = RADEON_READ(R600_BIOS_3_SCRATCH);
 289         } else {
 290                 bios_2_scratch = RADEON_READ(RADEON_BIOS_2_SCRATCH);
 291                 bios_3_scratch = RADEON_READ(RADEON_BIOS_3_SCRATCH);
 292         }
 293
 294         bios_2_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
 295         bios_3_scratch |= (crtc_id << 17);
 296
 297         switch(mode) {
 298         case DRM_MODE_DPMS_ON:
 299                 atombios_display_device_control(encoder, index, ATOM_ENABLE);
 300                 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
 301                 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
 302                 break;
 303         case DRM_MODE_DPMS_STANDBY:
 304         case DRM_MODE_DPMS_SUSPEND:
 305         case DRM_MODE_DPMS_OFF:
 306                 atombios_display_device_control(encoder, index, ATOM_DISABLE);
 307                 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
 308                 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
 309                 break;
 310         }
 311
 312         if (dev_priv->chip_family >= CHIP_R600) {
 313                 RADEON_WRITE(R600_BIOS_2_SCRATCH, bios_2_scratch);
 314                 RADEON_WRITE(R600_BIOS_3_SCRATCH, bios_3_scratch);
 315         } else {
 316                 RADEON_WRITE(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
 317                 RADEON_WRITE(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
 318         }
 319 }
 320
 321 static bool radeon_lvtma_mode_fixup(struct drm_encoder *encoder,
 322                                     struct drm_display_mode *mode,
 323                                     struct drm_display_mode *adjusted_mode)
 324 {
 325         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 326
 327         radeon_encoder->flags &= ~RADEON_USE_RMX;
 328
 329         if (radeon_encoder->rmx_type != RMX_OFF)
 330                 radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
 331
 332         return true;
 333 }
 334
 335 static void radeon_lvtma_prepare(struct drm_encoder *encoder)
 336 {
 337         radeon_atom_output_lock(encoder, true);
 338         radeon_lvtma_dpms(encoder, DRM_MODE_DPMS_OFF);
 339 }
 340
 341 static void radeon_lvtma_commit(struct drm_encoder *encoder)
 342 {
 343         radeon_lvtma_dpms(encoder, DRM_MODE_DPMS_ON);
 344         radeon_atom_output_lock(encoder, false);
 345 }
 346
 347 static const struct drm_encoder_helper_funcs radeon_atom_lvtma_helper_funcs = {
 348         .dpms = radeon_lvtma_dpms,
 349         .mode_fixup = radeon_lvtma_mode_fixup,
 350         .prepare = radeon_lvtma_prepare,
 351         .mode_set = radeon_lvtma_mode_set,
 352         .commit = radeon_lvtma_commit,
 353 };
 354
 355 void radeon_enc_destroy(struct drm_encoder *encoder)
 356 {
 357         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 358         drm_encoder_cleanup(encoder);
 359         kfree(radeon_encoder);
 360 }
 361
 362 static const struct drm_encoder_funcs radeon_atom_lvtma_enc_funcs = {
 363         .destroy = radeon_enc_destroy,
 364 };
 365
 366 struct drm_encoder *radeon_encoder_lvtma_add(struct drm_device *dev, int bios_index)
 367 {
 368         struct drm_radeon_private *dev_priv = dev->dev_private;
 369         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 370         struct radeon_encoder *radeon_encoder;
 371         struct drm_encoder *encoder;
 372         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 373         if (!radeon_encoder) {
 374                 return NULL;
 375         }
 376
 377         encoder = &radeon_encoder->base;
 378
 379         /* Set LVTMA to only use crtc 0 */
 380         encoder->possible_crtcs = 0x1;
 381         encoder->possible_clones = 0;
 382         drm_encoder_init(dev, encoder, &radeon_atom_lvtma_enc_funcs,
 383                          DRM_MODE_ENCODER_LVDS);
 384
 385         drm_encoder_helper_add(encoder, &radeon_atom_lvtma_helper_funcs);
 386         radeon_encoder->atom_device = mode_info->bios_connector[bios_index].devices;
 387
 388         /* TODO get the LVDS info from the BIOS for panel size etc. */
 389         /* get the lvds info from the bios */
 390         radeon_atombios_get_lvds_info(radeon_encoder);
 391
 392         /* LVDS gets default RMX full scaling */
 393         radeon_encoder->rmx_type = RMX_FULL;
 394
 395         return encoder;
 396 }
 397
 398 static void radeon_atom_dac_dpms(struct drm_encoder *encoder, int mode)
 399 {
 400         struct drm_device *dev = encoder->dev;
 401         struct drm_radeon_private *dev_priv = dev->dev_private;
 402         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 403         struct radeon_crtc *radeon_crtc;
 404         int atom_type = -1;
 405         int index;
 406         uint32_t bios_2_scratch, bios_3_scratch;
 407         int crtc_id = 0;
 408
 409         if (encoder->crtc) {
 410                 radeon_crtc = to_radeon_crtc(encoder->crtc);
 411                 crtc_id = radeon_crtc->crtc_id;
 412         }
 413
 414         atom_type = atom_dac_find_atom_type(radeon_encoder, NULL);
 415         if (atom_type == -1)
 416                 return;
 417
 418         if (dev_priv->chip_family >= CHIP_R600) {
 419                 bios_2_scratch = RADEON_READ(R600_BIOS_2_SCRATCH);
 420                 bios_3_scratch = RADEON_READ(R600_BIOS_3_SCRATCH);
 421         } else {
 422                 bios_2_scratch = RADEON_READ(RADEON_BIOS_2_SCRATCH);
 423                 bios_3_scratch = RADEON_READ(RADEON_BIOS_3_SCRATCH);
 424         }
 425
 426         switch(atom_type) {
 427         case ATOM_DEVICE_CRT1_INDEX:
 428                 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
 429                 bios_2_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
 430                 bios_3_scratch |= (crtc_id << 16);
 431                 switch(mode) {
 432                 case DRM_MODE_DPMS_ON:
 433                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
 434                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
 435                         break;
 436                 case DRM_MODE_DPMS_STANDBY:
 437                 case DRM_MODE_DPMS_SUSPEND:
 438                 case DRM_MODE_DPMS_OFF:
 439                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
 440                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
 441                         break;
 442                 }
 443                 break;
 444         case ATOM_DEVICE_CRT2_INDEX:
 445                 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
 446                 bios_2_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
 447                 bios_3_scratch |= (crtc_id << 20);
 448                 switch(mode) {
 449                 case DRM_MODE_DPMS_ON:
 450                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
 451                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
 452                         break;
 453                 case DRM_MODE_DPMS_STANDBY:
 454                 case DRM_MODE_DPMS_SUSPEND:
 455                 case DRM_MODE_DPMS_OFF:
 456                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
 457                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
 458                         break;
 459                 }
 460                 break;
 461         case ATOM_DEVICE_TV1_INDEX:
 462                 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
 463                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
 464                 bios_3_scratch |= (crtc_id << 18);
 465                 switch(mode) {
 466                 case DRM_MODE_DPMS_ON:
 467                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
 468                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
 469                         break;
 470                 case DRM_MODE_DPMS_STANDBY:
 471                 case DRM_MODE_DPMS_SUSPEND:
 472                 case DRM_MODE_DPMS_OFF:
 473                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
 474                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
 475                         break;
 476                 }
 477                 break;
 478         case ATOM_DEVICE_CV_INDEX:
 479                 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
 480                 bios_2_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
 481                 bios_3_scratch |= (crtc_id << 24);
 482                 switch(mode) {
 483                 case DRM_MODE_DPMS_ON:
 484                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
 485                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
 486                         break;
 487                 case DRM_MODE_DPMS_STANDBY:
 488                 case DRM_MODE_DPMS_SUSPEND:
 489                 case DRM_MODE_DPMS_OFF:
 490                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
 491                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
 492                         break;
 493                 }
 494                 break;
 495         default:
 496                 return;
 497         }
 498
 499         switch(mode) {
 500         case DRM_MODE_DPMS_ON:
 501                 atombios_display_device_control(encoder, index, ATOM_ENABLE);
 502                 break;
 503         case DRM_MODE_DPMS_STANDBY:
 504         case DRM_MODE_DPMS_SUSPEND:
 505         case DRM_MODE_DPMS_OFF:
 506                 atombios_display_device_control(encoder, index, ATOM_DISABLE);
 507                 break;
 508         }
 509
 510         if (dev_priv->chip_family >= CHIP_R600) {
 511                 RADEON_WRITE(R600_BIOS_2_SCRATCH, bios_2_scratch);
 512                 RADEON_WRITE(R600_BIOS_3_SCRATCH, bios_3_scratch);
 513         } else {
 514                 RADEON_WRITE(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
 515                 RADEON_WRITE(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
 516         }
 517 }
 518
 519 static bool radeon_atom_dac_mode_fixup(struct drm_encoder *encoder,
 520                                        struct drm_display_mode *mode,
 521                                        struct drm_display_mode *adjusted_mode)
 522 {
 523
 524         /* hw bug */
 525         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 526             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 527                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 528
 529         return true;
 530 }
 531
 532 static void radeon_atom_dac_prepare(struct drm_encoder *encoder)
 533 {
 534         radeon_atom_output_lock(encoder, true);
 535         radeon_atom_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 536 }
 537
 538 static void radeon_atom_dac_commit(struct drm_encoder *encoder)
 539 {
 540         radeon_atom_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 541         radeon_atom_output_lock(encoder, false);
 542 }
 543
 544 static int atombios_dac_setup(struct drm_encoder *encoder,
 545                               struct drm_display_mode *mode,
 546                               int atom_type)
 547 {
 548         struct drm_device *dev = encoder->dev;
 549         struct drm_radeon_private *dev_priv = dev->dev_private;
 550         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 551         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 552         int id = (radeon_encoder->type.dac == DAC_TVDAC);
 553         int index;
 554
 555         memset(&args, 0, sizeof(args));
 556         if (id == 0)
 557                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 558         else
 559                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 560
 561         args.ucAction = 1;
 562         args.usPixelClock = cpu_to_le16(mode->clock / 10);
 563         if ((atom_type == ATOM_DEVICE_CRT1_INDEX) ||
 564             (atom_type == ATOM_DEVICE_CRT2_INDEX))
 565                 args.ucDacStandard = id ? ATOM_DAC2_PS2 : ATOM_DAC1_PS2;
 566         else if (atom_type == ATOM_DEVICE_CV_INDEX)
 567                 args.ucDacStandard = id ? ATOM_DAC2_CV : ATOM_DAC1_CV;
 568         else if (atom_type == ATOM_DEVICE_TV1_INDEX)
 569                 args.ucDacStandard = id ? ATOM_DAC2_NTSC : ATOM_DAC1_NTSC;
 570         /* TODO PAL */
 571         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 572
 573         return 0;
 574 }
 575
 576 static int atombios_tv1_setup(struct drm_encoder *encoder,
 577                               struct drm_display_mode *mode,
 578                               int atom_type)
 579 {
 580         struct drm_device *dev = encoder->dev;
 581         struct drm_radeon_private *dev_priv = dev->dev_private;
 582         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 583         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 584         int index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 585
 586         memset(&args, 0, sizeof(args));
 587         args.sTVEncoder.ucAction = 1;
 588         if (atom_type == ATOM_DEVICE_CV_INDEX)
 589                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 590         else {
 591                 // TODO PAL
 592                 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 593         }
 594
 595         args.sTVEncoder.usPixelClock = cpu_to_le16(mode->clock / 10);
 596
 597         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 598         return 0;
 599 }
 600
 601 static void radeon_atom_dac_mode_set(struct drm_encoder *encoder,
 602                                      struct drm_display_mode *mode,
 603                                      struct drm_display_mode *adjusted_mode)
 604 {
 605         struct drm_device *dev = encoder->dev;
 606         struct drm_radeon_private *dev_priv = dev->dev_private;
 607         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 608         int atom_type = -1;
 609
 610         atom_type = atom_dac_find_atom_type(radeon_encoder, NULL);
 611         if (atom_type == -1)
 612                 return;
 613
 614         atombios_scaler_setup(encoder, mode);
 615         atombios_set_crtc_source(encoder, atom_type);
 616
 617         atombios_dac_setup(encoder, adjusted_mode, atom_type);
 618         if ((atom_type == ATOM_DEVICE_TV1_INDEX) ||
 619             (atom_type == ATOM_DEVICE_CV_INDEX))
 620                 atombios_tv1_setup(encoder, adjusted_mode, atom_type);
 621
 622 }
 623
 624 static bool atom_dac_load_detect(struct drm_encoder *encoder, int atom_devices)
 625 {
 626         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 627         struct drm_device *dev = encoder->dev;
 628         struct drm_radeon_private *dev_priv = dev->dev_private;
 629         DAC_LOAD_DETECTION_PS_ALLOCATION args;
 630         int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
 631
 632         memset(&args, 0, sizeof(args));
 633         args.sDacload.ucMisc = 0;
 634         args.sDacload.ucDacType = (radeon_encoder->type.dac == DAC_PRIMARY) ? ATOM_DAC_A : ATOM_DAC_B;
 635
 636         if (atom_devices & ATOM_DEVICE_CRT1_SUPPORT)
 637                 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
 638         else if (atom_devices & ATOM_DEVICE_CRT2_SUPPORT)
 639                 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
 640         else if (atom_devices & ATOM_DEVICE_CV_SUPPORT) {
 641                 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
 642                 if (radeon_is_dce3(dev_priv))
 643                         args.sDacload.ucMisc = 1;
 644         } else if (atom_devices & ATOM_DEVICE_TV1_SUPPORT) {
 645                 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
 646                 if (radeon_is_dce3(dev_priv))
 647                         args.sDacload.ucMisc = 1;
 648         } else
 649                 return false;
 650
 651         DRM_DEBUG("writing %x %x\n", args.sDacload.usDeviceID, args.sDacload.ucDacType);
 652         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 653         return true;
 654 }
 655
 656 static enum drm_connector_status radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 657 {
 658         struct drm_device *dev = encoder->dev;
 659         struct drm_radeon_private *dev_priv = dev->dev_private;
 660         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 661         int atom_type = -1;
 662         uint32_t bios_0_scratch;
 663
 664         atom_type = atom_dac_find_atom_type(radeon_encoder, connector);
 665         if (atom_type == -1) {
 666                 DRM_DEBUG("exit after find \n");
 667                 return connector_status_unknown;
 668         }
 669
 670         if(!atom_dac_load_detect(encoder, (1 << atom_type))) {
 671                 DRM_DEBUG("detect returned false \n");
 672                 return connector_status_unknown;
 673         }
 674
 675
 676         if (dev_priv->chip_family >= CHIP_R600)
 677                 bios_0_scratch = RADEON_READ(R600_BIOS_0_SCRATCH);
 678         else
 679                 bios_0_scratch = RADEON_READ(RADEON_BIOS_0_SCRATCH);
 680
 681         DRM_DEBUG("Bios 0 scratch %x\n", bios_0_scratch);
 682         if (radeon_encoder->atom_device & ATOM_DEVICE_CRT1_SUPPORT) {
 683                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
 684                         return connector_status_connected;
 685         } else if (radeon_encoder->atom_device & ATOM_DEVICE_CRT2_SUPPORT) {
 686                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
 687                         return connector_status_connected;
 688         } else if (radeon_encoder->atom_device & ATOM_DEVICE_CV_SUPPORT) {
 689                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
 690                         return connector_status_connected;
 691         } else if (radeon_encoder->atom_device & ATOM_DEVICE_TV1_SUPPORT) {
 692                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
 693                         return connector_status_connected; // CTV
 694                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
 695                         return connector_status_connected; // STV
 696         }
 697         return connector_status_disconnected;
 698 }
 699
 700 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
 701         .dpms = radeon_atom_dac_dpms,
 702         .mode_fixup = radeon_atom_dac_mode_fixup,
 703         .prepare = radeon_atom_dac_prepare,
 704         .mode_set = radeon_atom_dac_mode_set,
 705         .commit = radeon_atom_dac_commit,
 706         .detect = radeon_atom_dac_detect,
 707 };
 708
 709 static const struct drm_encoder_funcs radeon_atom_dac_enc_funcs = {
 710         . destroy = radeon_enc_destroy,
 711 };
 712
 713
 714 static void atombios_tmds1_setup(struct drm_encoder *encoder,
 715                                  struct drm_display_mode *mode)
 716 {
 717         struct drm_device *dev = encoder->dev;
 718         struct drm_radeon_private *dev_priv = dev->dev_private;
 719         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 720         TMDS1_ENCODER_CONTROL_PS_ALLOCATION args;
 721         int index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 722
 723         memset(&args, 0, sizeof(args));
 724         args.ucAction = 1;
 725         if (mode->clock > 165000)
 726                 args.ucMisc = 1;
 727         else
 728                 args.ucMisc = 0;
 729
 730         args.usPixelClock = cpu_to_le16(mode->clock / 10);
 731
 732         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 733 }
 734
 735 static void atombios_tmds2_setup(struct drm_encoder *encoder,
 736                                  struct drm_display_mode *mode)
 737 {
 738         struct drm_device *dev = encoder->dev;
 739         struct drm_radeon_private *dev_priv = dev->dev_private;
 740         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 741         TMDS2_ENCODER_CONTROL_PS_ALLOCATION args;
 742         int index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 743
 744         memset(&args, 0, sizeof(args));
 745         args.ucAction = 1;
 746         if (mode->clock > 165000)
 747                 args.ucMisc = 1;
 748         else
 749                 args.ucMisc = 0;
 750
 751         args.usPixelClock = cpu_to_le16(mode->clock / 10);
 752
 753         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 754 }
 755
 756
 757 static void atombios_ext_tmds_setup(struct drm_encoder *encoder,
 758                                     struct drm_display_mode *mode)
 759 {
 760         struct drm_device *dev = encoder->dev;
 761         struct drm_radeon_private *dev_priv = dev->dev_private;
 762         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 763         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
 764         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 765
 766         memset(&args, 0, sizeof(args));
 767         args.sXTmdsEncoder.ucEnable = 1;
 768
 769         if (mode->clock > 165000)
 770                 args.sXTmdsEncoder.ucMisc = 1;
 771         else
 772                 args.sXTmdsEncoder.ucMisc = 0;
 773
 774         // TODO 6-bit DAC
 775 //      args.usPixelClock = cpu_to_le16(mode->clock / 10);
 776
 777         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 778 }
 779
 780 static void atombios_dig1_setup(struct drm_encoder *encoder,
 781                                 struct drm_display_mode *mode)
 782 {
 783         struct drm_device *dev = encoder->dev;
 784         struct drm_radeon_private *dev_priv = dev->dev_private;
 785         DIG_ENCODER_CONTROL_PS_ALLOCATION args;
 786         int index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 787
 788         args.ucAction = 1;
 789         args.usPixelClock = mode->clock / 10;
 790         args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
 791
 792         // TODO coherent mode
 793 //      if (encoder->coherent_mode)
 794 //              args.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 795
 796         if (mode->clock > 165000) {
 797                 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA_B;
 798                 args.ucLaneNum = 8;
 799         } else {
 800                 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 801                 args.ucLaneNum = 4;
 802         }
 803
 804         // TODO Encoder MODE
 805         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 806 }
 807
 808 static void atombios_ddia_setup(struct drm_encoder *encoder,
 809                                 struct drm_display_mode *mode)
 810 {
 811         struct drm_device *dev = encoder->dev;
 812         struct drm_radeon_private *dev_priv = dev->dev_private;
 813         DVO_ENCODER_CONTROL_PS_ALLOCATION args;
 814         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 815
 816         args.sDVOEncoder.ucAction = ATOM_ENABLE;
 817         args.sDVOEncoder.usPixelClock = mode->clock / 10;
 818
 819         if (mode->clock > 165000)
 820                 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
 821         else
 822                 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = 0;
 823
 824         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 825 }
 826
 827 struct drm_encoder *radeon_encoder_atom_dac_add(struct drm_device *dev, int bios_index, int dac_type, int with_tv)
 828 {
 829         struct drm_radeon_private *dev_priv = dev->dev_private;
 830         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 831         struct radeon_encoder *radeon_encoder = NULL;
 832         struct drm_encoder *encoder;
 833         int type = with_tv ? DRM_MODE_ENCODER_TVDAC : DRM_MODE_ENCODER_DAC;
 834         int found = 0;
 835         int digital_enc_mask = ~(ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT |
 836                                 ATOM_DEVICE_LCD1_SUPPORT);
 837         /* we may already have added this encoder */
 838         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 839                 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC ||
 840                     encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
 841                         continue;
 842
 843                 radeon_encoder = to_radeon_encoder(encoder);
 844                 if (radeon_encoder->type.dac == dac_type) {
 845                         found = 1;
 846                         break;
 847                 }
 848         }
 849
 850         if (found) {
 851                 /* upgrade to a TV controlling DAC */
 852                 if (type == DRM_MODE_ENCODER_TVDAC)
 853                         encoder->encoder_type = type;
 854                 radeon_encoder->atom_device |= mode_info->bios_connector[bios_index].devices;
 855                 radeon_encoder->atom_device &= digital_enc_mask;
 856                 return encoder;
 857         }
 858
 859         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 860         if (!radeon_encoder) {
 861                 return NULL;
 862         }
 863
 864         encoder = &radeon_encoder->base;
 865
 866         encoder->possible_crtcs = 0x3;
 867         encoder->possible_clones = 0;
 868         drm_encoder_init(dev, encoder, &radeon_atom_dac_enc_funcs,
 869                          type);
 870
 871         drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
 872         radeon_encoder->type.dac = dac_type;
 873         radeon_encoder->atom_device = mode_info->bios_connector[bios_index].devices;
 874
 875         /* mask off any digital encoders */
 876         radeon_encoder->atom_device &= digital_enc_mask;
 877         return encoder;
 878 }
 879
 880 static void radeon_atom_tmds_dpms(struct drm_encoder *encoder, int mode)
 881 {
 882         struct drm_device *dev = encoder->dev;
 883         struct drm_radeon_private *dev_priv = dev->dev_private;
 884         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 885         struct radeon_crtc *radeon_crtc = NULL;
 886         int crtc_id = 0;
 887         int atom_type = -1;
 888         int index = -1;
 889         uint32_t bios_2_scratch, bios_3_scratch;
 890
 891         if (encoder->crtc) {
 892                 radeon_crtc = to_radeon_crtc(encoder->crtc);
 893                 crtc_id = radeon_crtc->crtc_id;
 894         } else if (mode == DRM_MODE_DPMS_ON)
 895                 return;
 896
 897         if (radeon_encoder->atom_device & ATOM_DEVICE_DFP1_SUPPORT)
 898                 atom_type = ATOM_DEVICE_DFP1_INDEX;
 899         if (radeon_encoder->atom_device & ATOM_DEVICE_DFP2_SUPPORT)
 900                 atom_type = ATOM_DEVICE_DFP2_INDEX;
 901         if (radeon_encoder->atom_device & ATOM_DEVICE_DFP3_SUPPORT)
 902                 atom_type = ATOM_DEVICE_DFP3_INDEX;
 903
 904         if (atom_type == -1)
 905                 return;
 906
 907         if (dev_priv->chip_family >= CHIP_R600) {
 908                 bios_2_scratch = RADEON_READ(R600_BIOS_2_SCRATCH);
 909                 bios_3_scratch = RADEON_READ(R600_BIOS_3_SCRATCH);
 910         } else {
 911                 bios_2_scratch = RADEON_READ(RADEON_BIOS_2_SCRATCH);
 912                 bios_3_scratch = RADEON_READ(RADEON_BIOS_3_SCRATCH);
 913         }
 914
 915         switch(atom_type) {
 916         case ATOM_DEVICE_DFP1_INDEX:
 917                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
 918                 bios_2_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
 919                 bios_3_scratch |= (crtc_id << 19);
 920                 switch(mode) {
 921                 case DRM_MODE_DPMS_ON:
 922                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
 923                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
 924                         break;
 925                 case DRM_MODE_DPMS_STANDBY:
 926                 case DRM_MODE_DPMS_SUSPEND:
 927                 case DRM_MODE_DPMS_OFF:
 928                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
 929                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
 930                         break;
 931                 }
 932                 break;
 933         case ATOM_DEVICE_DFP2_INDEX:
 934                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
 935                 bios_2_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
 936                 bios_3_scratch |= (crtc_id << 23);
 937                 switch(mode) {
 938                 case DRM_MODE_DPMS_ON:
 939                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
 940                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
 941                         break;
 942                 case DRM_MODE_DPMS_STANDBY:
 943                 case DRM_MODE_DPMS_SUSPEND:
 944                 case DRM_MODE_DPMS_OFF:
 945                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
 946                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
 947                         break;
 948                 }
 949                 break;
 950         case ATOM_DEVICE_DFP3_INDEX:
 951                 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
 952                 bios_2_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
 953                 bios_3_scratch |= (crtc_id << 25);
 954                 switch(mode) {
 955                 case DRM_MODE_DPMS_ON:
 956                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
 957                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
 958                         break;
 959                 case DRM_MODE_DPMS_STANDBY:
 960                 case DRM_MODE_DPMS_SUSPEND:
 961                 case DRM_MODE_DPMS_OFF:
 962                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
 963                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
 964                         break;
 965                 }
 966                 break;
 967         }
 968
 969         if (index == -1)
 970                 return;
 971
 972         switch(mode) {
 973         case DRM_MODE_DPMS_ON:
 974                 atombios_display_device_control(encoder, index, ATOM_ENABLE);
 975                 break;
 976         case DRM_MODE_DPMS_STANDBY:
 977         case DRM_MODE_DPMS_SUSPEND:
 978         case DRM_MODE_DPMS_OFF:
 979                 atombios_display_device_control(encoder, index, ATOM_DISABLE);
 980                 break;
 981         }
 982
 983         if (dev_priv->chip_family >= CHIP_R600) {
 984                 RADEON_WRITE(R600_BIOS_2_SCRATCH, bios_2_scratch);
 985                 RADEON_WRITE(R600_BIOS_3_SCRATCH, bios_3_scratch);
 986         } else {
 987                 RADEON_WRITE(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
 988                 RADEON_WRITE(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
 989         }
 990 }
 991
 992 static bool radeon_atom_tmds_mode_fixup(struct drm_encoder *encoder,
 993                                   struct drm_display_mode *mode,
 994                                   struct drm_display_mode *adjusted_mode)
 995 {
 996
 997         /* hw bug */
 998         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 999             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
1000                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
1001
1002         return true;
1003 }
1004
1005 static void radeon_atom_tmds_mode_set(struct drm_encoder *encoder,
1006                                       struct drm_display_mode *mode,
1007                                       struct drm_display_mode *adjusted_mode)
1008 {
1009         struct drm_device *dev = encoder->dev;
1010         struct drm_radeon_private *dev_priv = dev->dev_private;
1011         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1012         int atom_type;
1013
1014         if (radeon_encoder->atom_device & ATOM_DEVICE_DFP1_SUPPORT)
1015                 atom_type = ATOM_DEVICE_DFP1_INDEX;
1016         if (radeon_encoder->atom_device & ATOM_DEVICE_DFP2_SUPPORT)
1017                 atom_type = ATOM_DEVICE_DFP2_INDEX;
1018         if (radeon_encoder->atom_device & ATOM_DEVICE_DFP3_SUPPORT)
1019                 atom_type = ATOM_DEVICE_DFP3_INDEX;
1020
1021         atombios_scaler_setup(encoder, mode);
1022         atombios_set_crtc_source(encoder, atom_type);
1023
1024         if (atom_type == ATOM_DEVICE_DFP1_INDEX)
1025                 atombios_tmds1_setup(encoder, adjusted_mode);
1026         if (atom_type == ATOM_DEVICE_DFP2_INDEX) {
1027                 if ((dev_priv->chip_family == CHIP_RS600) ||
1028                     (dev_priv->chip_family == CHIP_RS690) ||
1029                     (dev_priv->chip_family == CHIP_RS740))
1030                         atombios_ddia_setup(encoder, adjusted_mode);
1031                 else
1032                         atombios_ext_tmds_setup(encoder, adjusted_mode);
1033         }
1034         if (atom_type == ATOM_DEVICE_DFP3_INDEX)
1035                 atombios_tmds2_setup(encoder, adjusted_mode);
1036         radeon_dfp_disable_dither(encoder, atom_type);
1037
1038
1039 }
1040
1041 static void radeon_atom_tmds_prepare(struct drm_encoder *encoder)
1042 {
1043         radeon_atom_output_lock(encoder, true);
1044         radeon_atom_tmds_dpms(encoder, DRM_MODE_DPMS_OFF);
1045 }
1046
1047 static void radeon_atom_tmds_commit(struct drm_encoder *encoder)
1048 {
1049         radeon_atom_tmds_dpms(encoder, DRM_MODE_DPMS_ON);
1050         radeon_atom_output_lock(encoder, false);
1051 }
1052
1053 static const struct drm_encoder_helper_funcs radeon_atom_tmds_helper_funcs = {
1054         .dpms = radeon_atom_tmds_dpms,
1055         .mode_fixup = radeon_atom_tmds_mode_fixup,
1056         .prepare = radeon_atom_tmds_prepare,
1057         .mode_set = radeon_atom_tmds_mode_set,
1058         .commit = radeon_atom_tmds_commit,
1059         /* no detect for TMDS */
1060 };
1061
1062 static const struct drm_encoder_funcs radeon_atom_tmds_enc_funcs = {
1063         . destroy = radeon_enc_destroy,
1064 };
1065
1066 struct drm_encoder *radeon_encoder_atom_tmds_add(struct drm_device *dev, int bios_index, int tmds_type)
1067 {
1068         struct drm_radeon_private *dev_priv = dev->dev_private;
1069         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
1070         struct radeon_encoder *radeon_encoder = NULL;
1071         struct drm_encoder *encoder;
1072         int analog_enc_mask = ~(ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT);
1073
1074                 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1075         if (!radeon_encoder) {
1076                 return NULL;
1077         }
1078
1079         encoder = &radeon_encoder->base;
1080
1081         encoder->possible_crtcs = 0x3;
1082         encoder->possible_clones = 0;
1083         drm_encoder_init(dev, encoder, &radeon_atom_tmds_enc_funcs,
1084                          DRM_MODE_ENCODER_TMDS);
1085
1086         drm_encoder_helper_add(encoder, &radeon_atom_tmds_helper_funcs);
1087
1088         radeon_encoder->atom_device = mode_info->bios_connector[bios_index].devices;
1089
1090         /* mask off any analog encoders */
1091         radeon_encoder->atom_device &= analog_enc_mask;
1092         return encoder;
1093 }