linux-core/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon_drv.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include "drm_crtc_helper.h"
  34 #include "drm_edid.h"
  35
  36 int radeon_ddc_dump(struct drm_connector *connector);
  37
  38
  39
  40 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  41 {
  42         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  43         struct drm_device *dev = crtc->dev;
  44         struct drm_radeon_private *dev_priv = dev->dev_private;
  45         int i;
  46
  47         DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
  48         RADEON_WRITE(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  49
  50         RADEON_WRITE(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  51         RADEON_WRITE(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  52         RADEON_WRITE(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  53
  54         RADEON_WRITE(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  55         RADEON_WRITE(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  56         RADEON_WRITE(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  57
  58         RADEON_WRITE(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  59         RADEON_WRITE(AVIVO_DC_LUT_RW_MODE, 0);
  60         RADEON_WRITE(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  61
  62         for (i = 0; i < 256; i++) {
  63                 RADEON_WRITE8(AVIVO_DC_LUT_RW_INDEX, i);
  64                 RADEON_WRITE(AVIVO_DC_LUT_30_COLOR,
  65                              (radeon_crtc->lut_r[i] << 22) |
  66                              (radeon_crtc->lut_g[i] << 12) |
  67                              (radeon_crtc->lut_b[i] << 2));
  68         }
  69
  70         RADEON_WRITE(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
  71 }
  72
  73 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
  74 {
  75         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  76         struct drm_device *dev = crtc->dev;
  77         struct drm_radeon_private *dev_priv = dev->dev_private;
  78         int i;
  79         uint32_t dac2_cntl;
  80
  81         dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2);
  82         if (radeon_crtc->crtc_id == 0)
  83                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
  84         else
  85                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
  86         RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
  87
  88         for (i = 0; i < 256; i++) {
  89                 RADEON_WRITE8(RADEON_PALETTE_INDEX, i);
  90                 RADEON_WRITE(RADEON_PALETTE_DATA,
  91                              (radeon_crtc->lut_r[i] << 16) |
  92                              (radeon_crtc->lut_g[i] << 8) |
  93                              (radeon_crtc->lut_b[i] << 0));
  94         }
  95 }
  96
  97 void radeon_crtc_load_lut(struct drm_crtc *crtc)
  98 {
  99         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 100         struct drm_device *dev = crtc->dev;
 101         struct drm_radeon_private *dev_priv = dev->dev_private;
 102
 103         if (!crtc->enabled)
 104                 return;
 105
 106         if (radeon_is_avivo(dev_priv))
 107                 avivo_crtc_load_lut(crtc);
 108         else
 109                 legacy_crtc_load_lut(crtc);
 110 }
 111
 112 /** Sets the color ramps on behalf of RandR */
 113 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 114                               u16 blue, int regno)
 115 {
 116         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 117
 118         if (regno==0)
 119                 DRM_DEBUG("gamma set %d\n", radeon_crtc->crtc_id);
 120         radeon_crtc->lut_r[regno] = red >> 8;
 121         radeon_crtc->lut_g[regno] = green >> 8;
 122         radeon_crtc->lut_b[regno] = blue >> 8;
 123 }
 124
 125 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 126                                   u16 *blue, uint32_t size)
 127 {
 128         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 129         int i, j;
 130
 131         if (size != 256)
 132                 return;
 133
 134         if (crtc->fb->depth == 16) {
 135                 for (i = 0; i < 64; i++) {
 136                         if (i <= 31) {
 137                                 for (j = 0; j < 8; j++) {
 138                                         radeon_crtc->lut_r[i * 8 + j] = red[i] >> 8;
 139                                         radeon_crtc->lut_b[i * 8 + j] = blue[i] >> 8;
 140                                 }
 141                         }
 142                         for (j = 0; j < 4; j++)
 143                                 radeon_crtc->lut_g[i * 4 + j] = green[i] >> 8;
 144                 }
 145         } else {
 146                 for (i = 0; i < 256; i++) {
 147                         radeon_crtc->lut_r[i] = red[i] >> 8;
 148                         radeon_crtc->lut_g[i] = green[i] >> 8;
 149                         radeon_crtc->lut_b[i] = blue[i] >> 8;
 150                 }
 151         }
 152
 153         radeon_crtc_load_lut(crtc);
 154 }
 155
 156 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 157 {
 158         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 159
 160         drm_crtc_cleanup(crtc);
 161         kfree(radeon_crtc);
 162 }
 163
 164 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 165         .cursor_set = radeon_crtc_cursor_set,
 166         .cursor_move = radeon_crtc_cursor_move,
 167         .gamma_set = radeon_crtc_gamma_set,
 168         .set_config = drm_crtc_helper_set_config,
 169         .destroy = radeon_crtc_destroy,
 170 };
 171
 172 static void radeon_crtc_init(struct drm_device *dev, int index)
 173 {
 174         struct drm_radeon_private *dev_priv = dev->dev_private;
 175         struct radeon_crtc *radeon_crtc;
 176         int i;
 177
 178         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 179         //      radeon_crtc = kzalloc(sizeof(struct radeon_crtc), GFP_KERNEL);
 180         if (radeon_crtc == NULL)
 181                 return;
 182
 183         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 184
 185         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 186         radeon_crtc->crtc_id = index;
 187
 188         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 189         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 190         radeon_crtc->mode_set.num_connectors = 0;
 191
 192         for (i = 0; i < 256; i++) {
 193                 radeon_crtc->lut_r[i] = i;
 194                 radeon_crtc->lut_g[i] = i;
 195                 radeon_crtc->lut_b[i] = i;
 196         }
 197
 198         if (dev_priv->is_atom_bios && radeon_is_avivo(dev_priv))
 199                 radeon_atombios_init_crtc(dev, radeon_crtc);
 200         else
 201                 radeon_legacy_init_crtc(dev, radeon_crtc);
 202 }
 203
 204 bool radeon_legacy_setup_enc_conn(struct drm_device *dev)
 205 {
 206
 207         radeon_get_legacy_connector_info_from_bios(dev);
 208         return false;
 209 }
 210
 211 bool radeon_setup_enc_conn(struct drm_device *dev)
 212 {
 213         struct drm_radeon_private *dev_priv = dev->dev_private;
 214         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 215         /* do all the mac and stuff */
 216         struct drm_connector *connector;
 217         struct drm_encoder *encoder;
 218         int i;
 219
 220         if (dev_priv->is_atom_bios)
 221                 radeon_get_atom_connector_info_from_bios_connector_table(dev);
 222         else
 223                 radeon_get_legacy_connector_info_from_bios(dev);
 224
 225         for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
 226                 if (!mode_info->bios_connector[i].valid)
 227                         continue;
 228
 229                 /* add a connector for this */
 230                 if (mode_info->bios_connector[i].connector_type == CONNECTOR_NONE)
 231                         continue;
 232
 233                 connector = radeon_connector_add(dev, i);
 234                 if (!connector)
 235                         continue;
 236
 237                 encoder = NULL;
 238                 /* if we find an LVDS connector */
 239                 if (mode_info->bios_connector[i].connector_type == CONNECTOR_LVDS) {
 240                         if (radeon_is_avivo(dev_priv))
 241                                 encoder = radeon_encoder_lvtma_add(dev, i);
 242                         else
 243                                 encoder = radeon_encoder_legacy_lvds_add(dev, i);
 244                         if (encoder)
 245                                 drm_mode_connector_attach_encoder(connector, encoder);
 246                 }
 247
 248                 /* DAC on DVI or VGA */
 249                 if ((mode_info->bios_connector[i].connector_type == CONNECTOR_DVI_I) ||
 250                     (mode_info->bios_connector[i].connector_type == CONNECTOR_DVI_A) ||
 251                     (mode_info->bios_connector[i].connector_type == CONNECTOR_VGA)) {
 252                         if (radeon_is_avivo(dev_priv)) {
 253                                 encoder = radeon_encoder_atom_dac_add(dev, i, mode_info->bios_connector[i].dac_type, 0);
 254                         } else {
 255                                 if (mode_info->bios_connector[i].dac_type == DAC_PRIMARY)
 256                                         encoder = radeon_encoder_legacy_primary_dac_add(dev, i, 0);
 257                                 else if (mode_info->bios_connector[i].dac_type == DAC_TVDAC)
 258                                         encoder = radeon_encoder_legacy_tv_dac_add(dev, i, 0);
 259                         }
 260                         if (encoder)
 261                                 drm_mode_connector_attach_encoder(connector, encoder);
 262                 }
 263
 264                 /* TMDS on DVI */
 265                 if ((mode_info->bios_connector[i].connector_type == CONNECTOR_DVI_I) ||
 266                     (mode_info->bios_connector[i].connector_type == CONNECTOR_DVI_D)) {
 267                         if (radeon_is_avivo(dev_priv))
 268                                 encoder = radeon_encoder_atom_tmds_add(dev, i, mode_info->bios_connector[i].tmds_type);
 269                         else {
 270                                 if (mode_info->bios_connector[i].tmds_type == TMDS_INT)
 271                                         encoder = radeon_encoder_legacy_tmds_int_add(dev, i);
 272                                 else if (mode_info->bios_connector[i].dac_type == TMDS_EXT)
 273                                         encoder = radeon_encoder_legacy_tmds_ext_add(dev, i);
 274                         }
 275                         if (encoder)
 276                                 drm_mode_connector_attach_encoder(connector, encoder);
 277                 }
 278
 279                 /* TVDAC on DIN */
 280                 if (mode_info->bios_connector[i].connector_type == CONNECTOR_DIN) {
 281                         if (radeon_is_avivo(dev_priv))
 282                                 encoder = radeon_encoder_atom_dac_add(dev, i, mode_info->bios_connector[i].dac_type, 1);
 283                         else {
 284                                 if (mode_info->bios_connector[i].dac_type == DAC_TVDAC)
 285                                         encoder = radeon_encoder_legacy_tv_dac_add(dev, i, 0);
 286                         }
 287                         if (encoder)
 288                                 drm_mode_connector_attach_encoder(connector, encoder);
 289                 }
 290         }
 291
 292         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
 293                 radeon_ddc_dump(connector);
 294         return true;
 295 }
 296
 297 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 298 {
 299         struct drm_radeon_private *dev_priv = radeon_connector->base.dev->dev_private;
 300         struct edid *edid;
 301         int ret = 0;
 302
 303         if (!radeon_connector->ddc_bus)
 304                 return -1;
 305         radeon_i2c_do_lock(radeon_connector, 1);
 306         edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
 307         radeon_i2c_do_lock(radeon_connector, 0);
 308         if (edid) {
 309                 /* update digital bits here */
 310                 if (edid->digital)
 311                         radeon_connector->use_digital = 1;
 312                 else
 313                         radeon_connector->use_digital = 0;
 314                 drm_mode_connector_update_edid_property(&radeon_connector->base, edid);
 315                 ret = drm_add_edid_modes(&radeon_connector->base, edid);
 316                 kfree(edid);
 317                 return ret;
 318         }
 319         return -1;
 320 }
 321
 322 int radeon_ddc_dump(struct drm_connector *connector)
 323 {
 324         struct edid *edid;
 325         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 326         int ret = 0;
 327
 328         if (!radeon_connector->ddc_bus)
 329                 return -1;
 330         radeon_i2c_do_lock(radeon_connector, 1);
 331         edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
 332         radeon_i2c_do_lock(radeon_connector, 0);
 333         if (edid) {
 334                 kfree(edid);
 335         }
 336         return ret;
 337 }
 338
 339 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
 340 {
 341         uint64_t x, y, result;
 342         uint64_t mod;
 343
 344         n += d / 2;
 345
 346         mod = do_div(n, d);
 347         return n;
 348 }
 349
 350 void radeon_compute_pll(struct radeon_pll *pll,
 351                         uint64_t freq,
 352                         uint32_t *dot_clock_p,
 353                         uint32_t *fb_div_p,
 354                         uint32_t *ref_div_p,
 355                         uint32_t *post_div_p,
 356                         int flags)
 357 {
 358         uint32_t min_ref_div = pll->min_ref_div;
 359         uint32_t max_ref_div = pll->max_ref_div;
 360         uint32_t best_vco = pll->best_vco;
 361         uint32_t best_post_div = 1;
 362         uint32_t best_ref_div = 1;
 363         uint32_t best_feedback_div = 1;
 364         uint32_t best_freq = -1;
 365         uint32_t best_error = 0xffffffff;
 366         uint32_t best_vco_diff = 1;
 367         uint32_t post_div;
 368
 369         DRM_DEBUG("PLL freq %llu\n", freq);
 370         freq = freq * 1000;
 371
 372         if (flags & RADEON_PLL_USE_REF_DIV)
 373                 min_ref_div = max_ref_div = pll->reference_div;
 374         else {
 375                 while (min_ref_div < max_ref_div-1) {
 376                         uint32_t mid=(min_ref_div+max_ref_div)/2;
 377                         uint32_t pll_in = pll->reference_freq / mid;
 378                         if (pll_in < pll->pll_in_min)
 379                                 max_ref_div = mid;
 380                         else if (pll_in > pll->pll_in_max)
 381                                 min_ref_div = mid;
 382                         else
 383                                 break;
 384                 }
 385         }
 386
 387         for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) {
 388                 uint32_t ref_div;
 389
 390                 if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
 391                         continue;
 392
 393                 /* legacy radeons only have a few post_divs */
 394                 if (flags & RADEON_PLL_LEGACY) {
 395                         if ((post_div == 5) ||
 396                             (post_div == 7) ||
 397                             (post_div == 9) ||
 398                             (post_div == 10) ||
 399                             (post_div == 11) ||
 400                             (post_div == 13) ||
 401                             (post_div == 14) ||
 402                             (post_div == 15))
 403                                 continue;
 404                 }
 405
 406                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
 407                         uint32_t feedback_div, current_freq, error, vco_diff;
 408                         uint32_t pll_in = pll->reference_freq / ref_div;
 409                         uint32_t min_feed_div = pll->min_feedback_div;
 410                         uint32_t max_feed_div = pll->max_feedback_div+1;
 411
 412                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
 413                                 continue;
 414
 415                         while (min_feed_div < max_feed_div) {
 416                                 uint32_t vco;
 417                                 feedback_div = (min_feed_div+max_feed_div)/2;
 418
 419                                 vco = radeon_div((uint64_t)pll->reference_freq * feedback_div,
 420                                                  ref_div);
 421
 422                                 if (vco < pll->pll_out_min) {
 423                                         min_feed_div = feedback_div+1;
 424                                         continue;
 425                                 } else if(vco > pll->pll_out_max) {
 426                                         max_feed_div = feedback_div;
 427                                         continue;
 428                                 }
 429
 430                                 current_freq = radeon_div((uint64_t)pll->reference_freq * 10000 * feedback_div,
 431                                                           ref_div * post_div);
 432
 433                                 error = abs(current_freq - freq);
 434                                 vco_diff = abs(vco - best_vco);
 435
 436                                 if ((best_vco == 0 && error < best_error) ||
 437                                     (best_vco != 0 &&
 438                                      (error < best_error - 100 ||
 439                                       (abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) {
 440                                         best_post_div = post_div;
 441                                         best_ref_div = ref_div;
 442                                         best_feedback_div = feedback_div;
 443                                         best_freq = current_freq;
 444                                         best_error = error;
 445                                         best_vco_diff = vco_diff;
 446                                 } else if (current_freq == freq) {
 447                                         if (best_freq == -1) {
 448                                                 best_post_div = post_div;
 449                                                 best_ref_div = ref_div;
 450                                                 best_feedback_div = feedback_div;
 451                                                 best_freq = current_freq;
 452                                                 best_error = error;
 453                                                 best_vco_diff = vco_diff;
 454                                         } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
 455                                                    ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
 456                                                    ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
 457                                                    ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
 458                                                    ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
 459                                                    ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
 460                                                 best_post_div = post_div;
 461                                                 best_ref_div = ref_div;
 462                                                 best_feedback_div = feedback_div;
 463                                                 best_freq = current_freq;
 464                                                 best_error = error;
 465                                                 best_vco_diff = vco_diff;
 466                                         }
 467                                 }
 468
 469                                 if (current_freq < freq)
 470                                         min_feed_div = feedback_div+1;
 471                                 else
 472                                         max_feed_div = feedback_div;
 473                         }
 474                 }
 475         }
 476
 477         *dot_clock_p = best_freq / 10000;
 478         *fb_div_p = best_feedback_div;
 479         *ref_div_p = best_ref_div;
 480         *post_div_p = best_post_div;
 481 }
 482
 483 void radeon_get_clock_info(struct drm_device *dev)
 484 {
 485         drm_radeon_private_t *dev_priv = dev->dev_private;
 486         struct radeon_pll *p1pll = &dev_priv->mode_info.p1pll;
 487         struct radeon_pll *p2pll = &dev_priv->mode_info.p2pll;
 488         struct radeon_pll *spll = &dev_priv->mode_info.spll;
 489         struct radeon_pll *mpll = &dev_priv->mode_info.mpll;
 490         int ret;
 491
 492         if (dev_priv->is_atom_bios)
 493                 ret = radeon_atom_get_clock_info(dev);
 494         else
 495                 ret = radeon_combios_get_clock_info(dev);
 496
 497         if (ret) {
 498                 if (p1pll->reference_div < 2)
 499                         p1pll->reference_div = 12;
 500                 if (p2pll->reference_div < 2)
 501                         p2pll->reference_div = 12;
 502         } else {
 503                 // TODO FALLBACK
 504         }
 505
 506         /* pixel clocks */
 507         if (radeon_is_avivo(dev_priv)) {
 508                 p1pll->min_post_div = 2;
 509                 p1pll->max_post_div = 0x7f;
 510                 p2pll->min_post_div = 2;
 511                 p2pll->max_post_div = 0x7f;
 512         } else {
 513                 p1pll->min_post_div = 1;
 514                 p1pll->max_post_div = 16;
 515                 p2pll->min_post_div = 1;
 516                 p2pll->max_post_div = 12;
 517         }
 518
 519         p1pll->min_ref_div = 2;
 520         p1pll->max_ref_div = 0x3ff;
 521         p1pll->min_feedback_div = 4;
 522         p1pll->max_feedback_div = 0x7ff;
 523         p1pll->best_vco = 0;
 524
 525         p2pll->min_ref_div = 2;
 526         p2pll->max_ref_div = 0x3ff;
 527         p2pll->min_feedback_div = 4;
 528         p2pll->max_feedback_div = 0x7ff;
 529         p2pll->best_vco = 0;
 530
 531         /* system clock */
 532         spll->min_post_div = 1;
 533         spll->max_post_div = 1;
 534         spll->min_ref_div = 2;
 535         spll->max_ref_div = 0xff;
 536         spll->min_feedback_div = 4;
 537         spll->max_feedback_div = 0xff;
 538         spll->best_vco = 0;
 539
 540         /* memory clock */
 541         mpll->min_post_div = 1;
 542         mpll->max_post_div = 1;
 543         mpll->min_ref_div = 2;
 544         mpll->max_ref_div = 0xff;
 545         mpll->min_feedback_div = 4;
 546         mpll->max_feedback_div = 0xff;
 547         mpll->best_vco = 0;
 548
 549 }
 550
 551 /* not sure of the best place for these */
 552 /* 10 khz */
 553 void radeon_legacy_set_engine_clock(struct drm_device *dev, int eng_clock)
 554 {
 555         struct drm_radeon_private *dev_priv = dev->dev_private;
 556         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 557         struct radeon_pll *spll = &mode_info->spll;
 558         uint32_t ref_div, fb_div;
 559         uint32_t m_spll_ref_fb_div;
 560
 561         /* FIXME wait for idle */
 562
 563         m_spll_ref_fb_div = RADEON_READ_PLL(dev_priv, RADEON_M_SPLL_REF_FB_DIV);
 564         m_spll_ref_fb_div &= ((RADEON_M_SPLL_REF_DIV_MASK << RADEON_M_SPLL_REF_DIV_SHIFT) |
 565                               (RADEON_MPLL_FB_DIV_MASK << RADEON_MPLL_FB_DIV_SHIFT));
 566         ref_div = m_spll_ref_fb_div & RADEON_M_SPLL_REF_DIV_MASK;
 567
 568         fb_div = radeon_div(eng_clock * ref_div, spll->reference_freq);
 569         m_spll_ref_fb_div |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT;
 570         RADEON_WRITE_PLL(dev_priv, RADEON_M_SPLL_REF_FB_DIV, m_spll_ref_fb_div);
 571
 572 }
 573
 574 /* 10 khz */
 575 void radeon_legacy_set_memory_clock(struct drm_device *dev, int mem_clock)
 576 {
 577         struct drm_radeon_private *dev_priv = dev->dev_private;
 578         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 579         struct radeon_pll *mpll = &mode_info->mpll;
 580         uint32_t ref_div, fb_div;
 581         uint32_t m_spll_ref_fb_div;
 582
 583         /* FIXME wait for idle */
 584
 585         m_spll_ref_fb_div = RADEON_READ_PLL(dev_priv, RADEON_M_SPLL_REF_FB_DIV);
 586         m_spll_ref_fb_div &= ((RADEON_M_SPLL_REF_DIV_MASK << RADEON_M_SPLL_REF_DIV_SHIFT) |
 587                               (RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT));
 588         ref_div = m_spll_ref_fb_div & RADEON_M_SPLL_REF_DIV_MASK;
 589
 590         fb_div = radeon_div(mem_clock * ref_div, mpll->reference_freq);
 591         m_spll_ref_fb_div |= (fb_div & RADEON_MPLL_FB_DIV_MASK) << RADEON_MPLL_FB_DIV_SHIFT;
 592         RADEON_WRITE_PLL(dev_priv, RADEON_M_SPLL_REF_FB_DIV, m_spll_ref_fb_div);
 593
 594 }
 595
 596 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
 597 {
 598         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
 599         struct drm_device *dev = fb->dev;
 600
 601         if (fb->fbdev)
 602                 radeonfb_remove(dev, fb);
 603
 604         drm_framebuffer_cleanup(fb);
 605         kfree(radeon_fb);
 606 }
 607
 608 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
 609         .destroy = radeon_user_framebuffer_destroy,
 610 };
 611
 612 struct drm_framebuffer *radeon_user_framebuffer_create(struct drm_device *dev,
 613                                                        struct drm_file *filp,
 614                                                        struct drm_mode_fb_cmd *mode_cmd)
 615 {
 616
 617         struct radeon_framebuffer *radeon_fb;
 618
 619         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
 620         if (!radeon_fb)
 621                 return NULL;
 622
 623         drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs);
 624         drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd);
 625
 626         if (filp) {
 627                 radeon_fb->obj = drm_gem_object_lookup(dev, filp,
 628                                                        mode_cmd->handle);
 629                 if (!radeon_fb->obj) {
 630                         kfree(radeon_fb);
 631                         return NULL;
 632                 }
 633                 drm_gem_object_unreference(radeon_fb->obj);
 634         }
 635         return &radeon_fb->base;
 636 }
 637
 638 static const struct drm_mode_config_funcs radeon_mode_funcs = {
 639         .fb_create = radeon_user_framebuffer_create,
 640         .fb_changed = radeonfb_probe,
 641 };
 642
 643
 644 int radeon_modeset_init(struct drm_device *dev)
 645 {
 646         drm_radeon_private_t *dev_priv = dev->dev_private;
 647         static struct card_info card;
 648         size_t size;
 649         int num_crtc = 2, i;
 650         int ret;
 651
 652         drm_mode_config_init(dev);
 653
 654         dev->mode_config.funcs = (void *)&radeon_mode_funcs;
 655
 656         if (radeon_is_avivo(dev_priv)) {
 657                     dev->mode_config.max_width = 8192;
 658                     dev->mode_config.max_height = 8192;
 659         } else {
 660                     dev->mode_config.max_width = 4096;
 661                     dev->mode_config.max_height = 4096;
 662         }
 663
 664         dev->mode_config.fb_base = dev_priv->fb_aper_offset;
 665
 666         /* allocate crtcs - TODO single crtc */
 667         for (i = 0; i < num_crtc; i++) {
 668                 radeon_crtc_init(dev, i);
 669         }
 670
 671         /* okay we should have all the bios connectors */
 672
 673         ret = radeon_setup_enc_conn(dev);
 674
 675         if (!ret)
 676                 return ret;
 677
 678         drm_helper_initial_config(dev, false);
 679
 680         return 0;
 681 }
 682
 683
 684 int radeon_load_modeset_init(struct drm_device *dev)
 685 {
 686         int ret;
 687         ret = radeon_modeset_init(dev);
 688
 689         return ret;
 690 }
 691
 692 void radeon_modeset_cleanup(struct drm_device *dev)
 693 {
 694         drm_mode_config_cleanup(dev);
 695 }