linux-core/radeon_cursor.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon_drv.h"
  29
  30 #define CURSOR_WIDTH 64
  31 #define CURSOR_HEIGHT 64
  32
  33 static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock)
  34 {
  35         struct drm_radeon_private *dev_priv = crtc->dev->dev_private;
  36         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  37         uint32_t cur_lock;
  38
  39         if (radeon_is_avivo(dev_priv)) {
  40                 cur_lock = RADEON_READ(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
  41                 if (lock)
  42                         cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;
  43                 else
  44                         cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
  45                 RADEON_WRITE(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
  46         } else {
  47                 switch(radeon_crtc->crtc_id) {
  48                 case 0:
  49                         cur_lock = RADEON_READ(RADEON_CUR_OFFSET);
  50                         if (lock)
  51                                 cur_lock |= RADEON_CUR_LOCK;
  52                         else
  53                                 cur_lock &= ~RADEON_CUR_LOCK;
  54                         RADEON_WRITE(RADEON_CUR_OFFSET, cur_lock);
  55                         break;
  56                 case 1:
  57                         cur_lock = RADEON_READ(RADEON_CUR2_OFFSET);
  58                         if (lock)
  59                                 cur_lock |= RADEON_CUR2_LOCK;
  60                         else
  61                                 cur_lock &= ~RADEON_CUR2_LOCK;
  62                         RADEON_WRITE(RADEON_CUR2_OFFSET, cur_lock);
  63                         break;
  64                 default:
  65                         break;
  66                 }
  67         }
  68 }
  69
  70 static void radeon_hide_cursor(struct drm_crtc *crtc)
  71 {
  72         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  73         struct drm_radeon_private *dev_priv = crtc->dev->dev_private;
  74
  75         if (radeon_is_avivo(dev_priv)) {
  76                 RADEON_WRITE(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
  77                 RADEON_WRITE_P(RADEON_MM_DATA, 0, ~AVIVO_D1CURSOR_EN);
  78         } else {
  79                 switch(radeon_crtc->crtc_id) {
  80                 case 0:
  81                         RADEON_WRITE(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
  82                         break;
  83                 case 1:
  84                         RADEON_WRITE(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
  85                         break;
  86                 default:
  87                         return;
  88                 }
  89                 RADEON_WRITE_P(RADEON_MM_DATA, 0, ~RADEON_CRTC_CUR_EN);
  90         }
  91 }
  92
  93 static void radeon_show_cursor(struct drm_crtc *crtc)
  94 {
  95         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  96         struct drm_radeon_private *dev_priv = crtc->dev->dev_private;
  97
  98         if (radeon_is_avivo(dev_priv)) {
  99                 RADEON_WRITE(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
 100                 RADEON_WRITE(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
 101                              (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
 102         } else {
 103                 switch(radeon_crtc->crtc_id) {
 104                 case 0:
 105                         RADEON_WRITE(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
 106                         break;
 107                 case 1:
 108                         RADEON_WRITE(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
 109                         break;
 110                 default:
 111                         return;
 112                 }
 113
 114                 RADEON_WRITE_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |
 115                                                 (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)),
 116                                ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
 117         }
 118 }
 119
 120 static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
 121                               uint32_t width, uint32_t height)
 122 {
 123         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 124         struct drm_radeon_private *dev_priv = crtc->dev->dev_private;
 125         struct drm_radeon_gem_object *obj_priv;
 126
 127         obj_priv = obj->driver_private;
 128
 129         if (radeon_is_avivo(dev_priv)) {
 130                 RADEON_WRITE(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 131                              dev_priv->fb_location + obj_priv->bo->offset);
 132                 RADEON_WRITE(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
 133                              (width - 1) << 16 | (height - 1));
 134         } else {
 135                 switch(radeon_crtc->crtc_id) {
 136                 case 0:
 137                         /* offset is from DISP_BASE_ADDRESS */
 138                         RADEON_WRITE(RADEON_CUR_OFFSET, obj_priv->bo->offset);
 139                         break;
 140                 case 1:
 141                         /* offset is from DISP2_BASE_ADDRESS */
 142                         RADEON_WRITE(RADEON_CUR2_OFFSET, obj_priv->bo->offset);
 143                         break;
 144                 default:
 145                         break;
 146                 }
 147         }
 148 }
 149
 150 int radeon_crtc_cursor_set(struct drm_crtc *crtc,
 151                            struct drm_file *file_priv,
 152                            uint32_t handle,
 153                            uint32_t width,
 154                            uint32_t height)
 155 {
 156         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 157         struct drm_gem_object *obj;
 158
 159         if (!handle) {
 160                 /* turn off cursor */
 161                 radeon_hide_cursor(crtc);
 162                 return 0;
 163         }
 164
 165         obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
 166         if (!obj) {
 167                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);
 168                 return -EINVAL;
 169         }
 170
 171         if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
 172                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
 173                 return -EINVAL;
 174         }
 175
 176         radeon_lock_cursor(crtc, true);
 177         // XXX only 27 bit offset for legacy cursor
 178         radeon_set_cursor(crtc, obj, width, height);
 179         radeon_show_cursor(crtc);
 180         radeon_lock_cursor(crtc, false);
 181
 182         mutex_lock(&crtc->dev->struct_mutex);
 183         drm_gem_object_unreference(obj);
 184         mutex_unlock(&crtc->dev->struct_mutex);
 185
 186         return 0;
 187 }
 188
 189 int radeon_crtc_cursor_move(struct drm_crtc *crtc,
 190                             int x, int y)
 191 {
 192         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 193         struct drm_radeon_private *dev_priv = crtc->dev->dev_private;
 194         int xorigin = 0, yorigin = 0;
 195
 196         if (x < 0)
 197                 xorigin = -x + 1;
 198         if (y < 0)
 199                 yorigin = -x + 1;
 200         if (xorigin >= CURSOR_WIDTH)
 201                 xorigin = CURSOR_WIDTH - 1;
 202         if (yorigin >= CURSOR_WIDTH)
 203                 yorigin = CURSOR_WIDTH - 1;
 204
 205         radeon_lock_cursor(crtc, true);
 206         if (radeon_is_avivo(dev_priv)) {
 207                 RADEON_WRITE(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset,
 208                              ((xorigin ? 0: x) << 16) |
 209                              (yorigin ? 0 : y));
 210                 RADEON_WRITE(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
 211         } else {
 212                 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
 213                         y /= 2;
 214                 else if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
 215                         y *= 2;
 216
 217                 switch(radeon_crtc->crtc_id) {
 218                 case 0:
 219                         RADEON_WRITE(RADEON_CUR_HORZ_VERT_OFF,  (RADEON_CUR_LOCK
 220                                                                  | (xorigin << 16)
 221                                                                  | yorigin));
 222                         RADEON_WRITE(RADEON_CUR_HORZ_VERT_POSN, (RADEON_CUR_LOCK
 223                                                                  | ((xorigin ? 0 : x) << 16)
 224                                                                  | (yorigin ? 0 : y)));
 225                         break;
 226                 case 1:
 227                         RADEON_WRITE(RADEON_CUR2_HORZ_VERT_OFF,  (RADEON_CUR2_LOCK
 228                                                                  | (xorigin << 16)
 229                                                                  | yorigin));
 230                         RADEON_WRITE(RADEON_CUR2_HORZ_VERT_POSN, (RADEON_CUR2_LOCK
 231                                                                  | ((xorigin ? 0 : x) << 16)
 232                                                                  | (yorigin ? 0 : y)));
 233                         break;
 234                 default:
 235                         break;
 236                 }
 237
 238         }
 239         radeon_lock_cursor(crtc, false);
 240
 241         return 0;
 242 }
 243