2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include "radeon_drm.h"
29 #include "radeon_drv.h"
31 /* old legacy ATI BIOS routines */
33 /* COMBIOS table offsets */
34 enum radeon_combios_table_offset
36 /* absolute offset tables */
37 COMBIOS_ASIC_INIT_1_TABLE,
38 COMBIOS_BIOS_SUPPORT_TABLE,
39 COMBIOS_DAC_PROGRAMMING_TABLE,
40 COMBIOS_MAX_COLOR_DEPTH_TABLE,
41 COMBIOS_CRTC_INFO_TABLE,
42 COMBIOS_PLL_INFO_TABLE,
43 COMBIOS_TV_INFO_TABLE,
44 COMBIOS_DFP_INFO_TABLE,
45 COMBIOS_HW_CONFIG_INFO_TABLE,
46 COMBIOS_MULTIMEDIA_INFO_TABLE,
47 COMBIOS_TV_STD_PATCH_TABLE,
48 COMBIOS_LCD_INFO_TABLE,
49 COMBIOS_MOBILE_INFO_TABLE,
50 COMBIOS_PLL_INIT_TABLE,
51 COMBIOS_MEM_CONFIG_TABLE,
52 COMBIOS_SAVE_MASK_TABLE,
53 COMBIOS_HARDCODED_EDID_TABLE,
54 COMBIOS_ASIC_INIT_2_TABLE,
55 COMBIOS_CONNECTOR_INFO_TABLE,
56 COMBIOS_DYN_CLK_1_TABLE,
57 COMBIOS_RESERVED_MEM_TABLE,
58 COMBIOS_EXT_TDMS_INFO_TABLE,
59 COMBIOS_MEM_CLK_INFO_TABLE,
60 COMBIOS_EXT_DAC_INFO_TABLE,
61 COMBIOS_MISC_INFO_TABLE,
62 COMBIOS_CRT_INFO_TABLE,
63 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
64 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
65 COMBIOS_FAN_SPEED_INFO_TABLE,
66 COMBIOS_OVERDRIVE_INFO_TABLE,
67 COMBIOS_OEM_INFO_TABLE,
68 COMBIOS_DYN_CLK_2_TABLE,
69 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
70 COMBIOS_I2C_INFO_TABLE,
71 /* relative offset tables */
72 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
73 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
74 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
75 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
76 COMBIOS_POWERPLAY_TABLE, /* offset from mobile info */
77 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
78 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
79 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
80 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
81 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
84 enum radeon_combios_ddc
95 enum radeon_combios_connector
97 CONNECTOR_NONE_LEGACY,
98 CONNECTOR_PROPRIETARY_LEGACY,
100 CONNECTOR_DVI_I_LEGACY,
101 CONNECTOR_DVI_D_LEGACY,
102 CONNECTOR_CTV_LEGACY,
103 CONNECTOR_STV_LEGACY,
104 CONNECTOR_UNSUPPORTED_LEGACY
107 static uint16_t combios_get_table_offset(struct drm_device *dev, enum radeon_combios_table_offset table)
109 struct drm_radeon_private *dev_priv = dev->dev_private;
111 uint16_t offset = 0, check_offset;
114 /* absolute offset tables */
115 case COMBIOS_ASIC_INIT_1_TABLE:
116 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0xc);
118 offset = check_offset;
120 case COMBIOS_BIOS_SUPPORT_TABLE:
121 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x14);
123 offset = check_offset;
125 case COMBIOS_DAC_PROGRAMMING_TABLE:
126 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x2a);
128 offset = check_offset;
130 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
131 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x2c);
133 offset = check_offset;
135 case COMBIOS_CRTC_INFO_TABLE:
136 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x2e);
138 offset = check_offset;
140 case COMBIOS_PLL_INFO_TABLE:
141 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x30);
143 offset = check_offset;
145 case COMBIOS_TV_INFO_TABLE:
146 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x32);
148 offset = check_offset;
150 case COMBIOS_DFP_INFO_TABLE:
151 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x34);
153 offset = check_offset;
155 case COMBIOS_HW_CONFIG_INFO_TABLE:
156 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x36);
158 offset = check_offset;
160 case COMBIOS_MULTIMEDIA_INFO_TABLE:
161 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x38);
163 offset = check_offset;
165 case COMBIOS_TV_STD_PATCH_TABLE:
166 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x3e);
168 offset = check_offset;
170 case COMBIOS_LCD_INFO_TABLE:
171 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x40);
173 offset = check_offset;
175 case COMBIOS_MOBILE_INFO_TABLE:
176 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x42);
178 offset = check_offset;
180 case COMBIOS_PLL_INIT_TABLE:
181 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x46);
183 offset = check_offset;
185 case COMBIOS_MEM_CONFIG_TABLE:
186 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x48);
188 offset = check_offset;
190 case COMBIOS_SAVE_MASK_TABLE:
191 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x4a);
193 offset = check_offset;
195 case COMBIOS_HARDCODED_EDID_TABLE:
196 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x4c);
198 offset = check_offset;
200 case COMBIOS_ASIC_INIT_2_TABLE:
201 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x4e);
203 offset = check_offset;
205 case COMBIOS_CONNECTOR_INFO_TABLE:
206 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x50);
208 offset = check_offset;
210 case COMBIOS_DYN_CLK_1_TABLE:
211 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x52);
213 offset = check_offset;
215 case COMBIOS_RESERVED_MEM_TABLE:
216 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x54);
218 offset = check_offset;
220 case COMBIOS_EXT_TDMS_INFO_TABLE:
221 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x58);
223 offset = check_offset;
225 case COMBIOS_MEM_CLK_INFO_TABLE:
226 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x5a);
228 offset = check_offset;
230 case COMBIOS_EXT_DAC_INFO_TABLE:
231 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x5c);
233 offset = check_offset;
235 case COMBIOS_MISC_INFO_TABLE:
236 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x5e);
238 offset = check_offset;
240 case COMBIOS_CRT_INFO_TABLE:
241 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x60);
243 offset = check_offset;
245 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
246 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x62);
248 offset = check_offset;
250 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
251 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x64);
253 offset = check_offset;
255 case COMBIOS_FAN_SPEED_INFO_TABLE:
256 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x66);
258 offset = check_offset;
260 case COMBIOS_OVERDRIVE_INFO_TABLE:
261 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x68);
263 offset = check_offset;
265 case COMBIOS_OEM_INFO_TABLE:
266 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x6a);
268 offset = check_offset;
270 case COMBIOS_DYN_CLK_2_TABLE:
271 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x6c);
273 offset = check_offset;
275 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
276 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x6e);
278 offset = check_offset;
280 case COMBIOS_I2C_INFO_TABLE:
281 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x70);
283 offset = check_offset;
285 /* relative offset tables */
286 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
287 check_offset = combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
289 rev = radeon_bios8(dev_priv, check_offset);
291 check_offset = radeon_bios16(dev_priv, check_offset + 0x3);
293 offset = check_offset;
297 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
298 check_offset = combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
300 rev = radeon_bios8(dev_priv, check_offset);
302 check_offset = radeon_bios16(dev_priv, check_offset + 0x5);
304 offset = check_offset;
308 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
309 check_offset = combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
311 rev = radeon_bios8(dev_priv, check_offset);
313 check_offset = radeon_bios16(dev_priv, check_offset + 0x9);
315 offset = check_offset;
319 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
320 check_offset = combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
322 while (radeon_bios8(dev_priv, check_offset++));
325 offset = check_offset;
328 case COMBIOS_POWERPLAY_TABLE: /* offset from mobile info */
329 check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
331 check_offset = radeon_bios16(dev_priv, check_offset + 0x11);
333 offset = check_offset;
336 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
337 check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
339 check_offset = radeon_bios16(dev_priv, check_offset + 0x13);
341 offset = check_offset;
344 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
345 check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
347 check_offset = radeon_bios16(dev_priv, check_offset + 0x15);
349 offset = check_offset;
352 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
353 check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
355 check_offset = radeon_bios16(dev_priv, check_offset + 0x17);
357 offset = check_offset;
360 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
361 check_offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
363 check_offset = radeon_bios16(dev_priv, check_offset + 0x2);
365 offset = check_offset;
368 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
369 check_offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
371 check_offset = radeon_bios16(dev_priv, check_offset + 0x4);
373 offset = check_offset;
384 struct radeon_i2c_bus_rec combios_setup_i2c_bus(int ddc_line)
386 struct radeon_i2c_bus_rec i2c;
388 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
389 i2c.mask_data_mask = RADEON_GPIO_EN_0;
390 i2c.a_clk_mask = RADEON_GPIO_A_1;
391 i2c.a_data_mask = RADEON_GPIO_A_0;
392 i2c.put_clk_mask = RADEON_GPIO_EN_1;
393 i2c.put_data_mask = RADEON_GPIO_EN_0;
394 i2c.get_clk_mask = RADEON_GPIO_Y_1;
395 i2c.get_data_mask = RADEON_GPIO_Y_0;
396 if ((ddc_line == RADEON_LCD_GPIO_MASK) ||
397 (ddc_line == RADEON_MDGPIO_EN_REG)) {
398 i2c.mask_clk_reg = ddc_line;
399 i2c.mask_data_reg = ddc_line;
400 i2c.a_clk_reg = ddc_line;
401 i2c.a_data_reg = ddc_line;
402 i2c.put_clk_reg = ddc_line;
403 i2c.put_data_reg = ddc_line;
404 i2c.get_clk_reg = ddc_line + 4;
405 i2c.get_data_reg = ddc_line + 4;
407 i2c.mask_clk_reg = ddc_line;
408 i2c.mask_data_reg = ddc_line;
409 i2c.a_clk_reg = ddc_line;
410 i2c.a_data_reg = ddc_line;
411 i2c.put_clk_reg = ddc_line;
412 i2c.put_data_reg = ddc_line;
413 i2c.get_clk_reg = ddc_line;
414 i2c.get_data_reg = ddc_line;
425 bool radeon_combios_get_clock_info(struct drm_device *dev)
427 struct drm_radeon_private *dev_priv = dev->dev_private;
428 struct radeon_mode_info *mode_info = &dev_priv->mode_info;
430 struct radeon_pll *pll = &mode_info->pll;
433 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
435 rev = radeon_bios8(dev_priv, pll_info);
437 pll->reference_freq = radeon_bios16(dev_priv, pll_info + 0xe);
438 pll->reference_div = radeon_bios16(dev_priv, pll_info + 0x10);
439 pll->pll_out_min = radeon_bios32(dev_priv, pll_info + 0x12);
440 pll->pll_out_max = radeon_bios32(dev_priv, pll_info + 0x16);
443 pll->pll_in_min = radeon_bios32(dev_priv, pll_info + 0x36);
444 pll->pll_in_max = radeon_bios32(dev_priv, pll_info + 0x3a);
446 pll->pll_in_min = 40;
447 pll->pll_in_max = 500;
450 pll->xclk = radeon_bios16(dev_priv, pll_info + 0x08);
452 // sclk/mclk use fixed point
459 bool radeon_combios_get_lvds_info(struct radeon_encoder *encoder)
461 struct drm_device *dev = encoder->base.dev;
462 struct drm_radeon_private *dev_priv = dev->dev_private;
467 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
470 for (i = 0; i < 24; i++)
471 stmp[i] = radeon_bios8(dev_priv, lcd_info + i + 1);
474 DRM_INFO("Panel ID String: %s\n", stmp);
476 encoder->panel_xres = radeon_bios16(dev_priv, lcd_info + 25);
477 encoder->panel_yres = radeon_bios16(dev_priv, lcd_info + 27);
479 DRM_INFO("Panel Size %dx%d\n", encoder->panel_xres, encoder->panel_yres);
481 encoder->panel_pwr_delay = radeon_bios16(dev_priv, lcd_info + 44);
482 if (encoder->panel_pwr_delay > 2000 || encoder->panel_pwr_delay < 0)
483 encoder->panel_pwr_delay = 2000;
485 for (i = 0; i < 32; i++) {
486 tmp = radeon_bios16(dev_priv, lcd_info + 64 + i * 2);
489 if ((radeon_bios16(dev_priv, tmp) == encoder->panel_xres) &&
490 (radeon_bios16(dev_priv, tmp + 2) == encoder->panel_yres)) {
491 encoder->hblank = (radeon_bios16(dev_priv, tmp + 17) -
492 radeon_bios16(dev_priv, tmp + 19)) * 8;
493 encoder->hoverplus = (radeon_bios16(dev_priv, tmp + 21) -
494 radeon_bios16(dev_priv, tmp + 19) - 1) * 8;
495 encoder->hsync_width = radeon_bios8(dev_priv, tmp + 23) * 8;
497 encoder->vblank = (radeon_bios16(dev_priv, tmp + 24) -
498 radeon_bios16(dev_priv, tmp + 26));
499 encoder->voverplus = ((radeon_bios16(dev_priv, tmp + 28) & 0x7fff) -
500 radeon_bios16(dev_priv, tmp + 26));
501 encoder->vsync_width = ((radeon_bios16(dev_priv, tmp + 28) & 0xf800) >> 11);
502 encoder->dotclock = radeon_bios16(dev_priv, tmp + 9) * 10;
508 DRM_INFO("No panel info found in BIOS\n");
513 bool radeon_combios_get_tmds_info(struct radeon_encoder *encoder)
515 struct drm_device *dev = encoder->base.dev;
516 struct drm_radeon_private *dev_priv = dev->dev_private;
521 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
524 ver = radeon_bios8(dev_priv, tmds_info);
525 DRM_INFO("DFP table revision: %d\n", ver);
527 n = radeon_bios8(dev_priv, tmds_info + 5) + 1;
530 for (i = 0; i < n; i++) {
531 encoder->tmds_pll[i].value = radeon_bios32(dev_priv, tmds_info + i * 10 + 0x08);
532 encoder->tmds_pll[i].freq = radeon_bios16(dev_priv, tmds_info + i * 10 + 0x10);
535 } else if (ver == 4) {
537 n = radeon_bios8(dev_priv, tmds_info + 5) + 1;
540 for (i = 0; i < n; i++) {
541 encoder->tmds_pll[i].value = radeon_bios32(dev_priv, tmds_info + stride + 0x08);
542 encoder->tmds_pll[i].freq = radeon_bios16(dev_priv, tmds_info + stride + 0x10);
552 DRM_INFO("No TMDS info found in BIOS\n");
556 static void radeon_apply_legacy_quirks(struct drm_device *dev, int bios_index)
558 struct drm_radeon_private *dev_priv = dev->dev_private;
559 struct radeon_mode_info *mode_info = &dev_priv->mode_info;
561 /* on XPRESS chips, CRT2_DDC and MONID_DCC both use the
562 * MONID gpio, but use different pins.
563 * CRT2_DDC uses the standard pinout, MONID_DDC uses
566 if ((dev_priv->chip_family == CHIP_RS400 ||
567 dev_priv->chip_family == CHIP_RS480) &&
568 mode_info->bios_connector[bios_index].connector_type == CONNECTOR_VGA &&
569 mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) {
570 mode_info->bios_connector[bios_index].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
573 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
574 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
575 if (dev->pdev->device == 0x515e &&
576 dev->pdev->subsystem_vendor == 0x1014) {
577 if (mode_info->bios_connector[bios_index].connector_type == CONNECTOR_VGA &&
578 mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) {
579 mode_info->bios_connector[bios_index].valid = false;
583 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
584 if (dev->pdev->device == 0x5159 &&
585 dev->pdev->subsystem_vendor == 0x1002 &&
586 dev->pdev->subsystem_device == 0x013a) {
587 if (mode_info->bios_connector[bios_index].connector_type == CONNECTOR_DVI_I)
588 mode_info->bios_connector[bios_index].connector_type = CONNECTOR_VGA;
594 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
596 struct drm_radeon_private *dev_priv = dev->dev_private;
597 struct radeon_mode_info *mode_info = &dev_priv->mode_info;
598 uint32_t conn_info, entry;
600 enum radeon_combios_ddc ddc_type;
601 enum radeon_combios_connector connector_type;
605 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
607 for (i = 0; i < 4; i++) {
608 entry = conn_info + 2 + i * 2;
610 if (!radeon_bios16(dev_priv, entry))
613 mode_info->bios_connector[i].valid = true;
615 tmp = radeon_bios16(dev_priv, entry);
617 connector_type = (tmp >> 12) & 0xf;
618 mode_info->bios_connector[i].connector_type = connector_type;
620 switch(connector_type) {
621 case CONNECTOR_PROPRIETARY_LEGACY:
622 mode_info->bios_connector[i].connector_type = CONNECTOR_DVI_D;
624 case CONNECTOR_CRT_LEGACY:
625 mode_info->bios_connector[i].connector_type = CONNECTOR_VGA;
627 case CONNECTOR_DVI_I_LEGACY:
628 mode_info->bios_connector[i].connector_type = CONNECTOR_DVI_I;
630 case CONNECTOR_DVI_D_LEGACY:
631 mode_info->bios_connector[i].connector_type = CONNECTOR_DVI_D;
633 case CONNECTOR_CTV_LEGACY:
634 mode_info->bios_connector[i].connector_type = CONNECTOR_CTV;
636 case CONNECTOR_STV_LEGACY:
637 mode_info->bios_connector[i].connector_type = CONNECTOR_STV;
640 DRM_ERROR("Unknown connector type: %d\n", connector_type);
641 mode_info->bios_connector[i].valid = false;
645 mode_info->bios_connector[i].ddc_i2c.valid = false;
647 ddc_type = (tmp >> 8) & 0xf;
650 mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
653 mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
656 mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
659 mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
666 mode_info->bios_connector[i].dac_type = DAC_TVDAC;
668 mode_info->bios_connector[i].dac_type = DAC_PRIMARY;
670 if ((dev_priv->chip_family == CHIP_RS300) ||
671 (dev_priv->chip_family == CHIP_RS400) ||
672 (dev_priv->chip_family == CHIP_RS480))
673 mode_info->bios_connector[i].dac_type = DAC_TVDAC;
675 if ((tmp >> 4) & 0x1)
676 mode_info->bios_connector[i].tmds_type = TMDS_EXT;
678 mode_info->bios_connector[i].tmds_type = TMDS_INT;
680 radeon_apply_legacy_quirks(dev, i);
683 uint16_t tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
685 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
687 mode_info->bios_connector[0].valid = true;
688 mode_info->bios_connector[0].connector_type = CONNECTOR_DVI_I;
689 mode_info->bios_connector[0].dac_type = DAC_PRIMARY;
690 mode_info->bios_connector[0].tmds_type = TMDS_INT;
691 mode_info->bios_connector[0].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
693 DRM_DEBUG("No connector info found\n");
698 if (dev_priv->flags & RADEON_IS_MOBILITY ||
699 dev_priv->chip_family == CHIP_RS400 ||
700 dev_priv->chip_family == CHIP_RS480) {
701 uint16_t lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
703 uint16_t lcd_ddc_info = lcd_ddc_info = combios_get_table_offset(dev, COMBIOS_LCD_DDC_INFO_TABLE);
705 mode_info->bios_connector[4].valid = true;
706 mode_info->bios_connector[4].connector_type = CONNECTOR_LVDS;
707 mode_info->bios_connector[4].dac_type = DAC_NONE;
708 mode_info->bios_connector[4].tmds_type = TMDS_NONE;
709 mode_info->bios_connector[4].ddc_i2c.valid = false;
712 ddc_type = radeon_bios8(dev_priv, lcd_ddc_info + 2);
715 mode_info->bios_connector[4].ddc_i2c =
716 combios_setup_i2c_bus(RADEON_GPIO_MONID);
719 mode_info->bios_connector[4].ddc_i2c =
720 combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
723 mode_info->bios_connector[4].ddc_i2c =
724 combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
727 mode_info->bios_connector[4].ddc_i2c =
728 combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
731 mode_info->bios_connector[4].ddc_i2c =
732 combios_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
733 mode_info->bios_connector[4].ddc_i2c.mask_clk_mask =
734 radeon_bios32(dev_priv, lcd_ddc_info + 3);
735 mode_info->bios_connector[4].ddc_i2c.mask_data_mask =
736 radeon_bios32(dev_priv, lcd_ddc_info + 7);
737 mode_info->bios_connector[4].ddc_i2c.a_clk_mask =
738 radeon_bios32(dev_priv, lcd_ddc_info + 3);
739 mode_info->bios_connector[4].ddc_i2c.a_data_mask =
740 radeon_bios32(dev_priv, lcd_ddc_info + 7);
741 mode_info->bios_connector[4].ddc_i2c.put_clk_mask =
742 radeon_bios32(dev_priv, lcd_ddc_info + 3);
743 mode_info->bios_connector[4].ddc_i2c.put_data_mask =
744 radeon_bios32(dev_priv, lcd_ddc_info + 7);
745 mode_info->bios_connector[4].ddc_i2c.get_clk_mask =
746 radeon_bios32(dev_priv, lcd_ddc_info + 3);
747 mode_info->bios_connector[4].ddc_i2c.get_data_mask =
748 radeon_bios32(dev_priv, lcd_ddc_info + 7);
751 mode_info->bios_connector[4].ddc_i2c =
752 combios_setup_i2c_bus(RADEON_MDGPIO_EN_REG);
753 mode_info->bios_connector[4].ddc_i2c.mask_clk_mask =
754 radeon_bios32(dev_priv, lcd_ddc_info + 3);
755 mode_info->bios_connector[4].ddc_i2c.mask_data_mask =
756 radeon_bios32(dev_priv, lcd_ddc_info + 7);
757 mode_info->bios_connector[4].ddc_i2c.a_clk_mask =
758 radeon_bios32(dev_priv, lcd_ddc_info + 3);
759 mode_info->bios_connector[4].ddc_i2c.a_data_mask =
760 radeon_bios32(dev_priv, lcd_ddc_info + 7);
761 mode_info->bios_connector[4].ddc_i2c.put_clk_mask =
762 radeon_bios32(dev_priv, lcd_ddc_info + 3);
763 mode_info->bios_connector[4].ddc_i2c.put_data_mask =
764 radeon_bios32(dev_priv, lcd_ddc_info + 7);
765 mode_info->bios_connector[4].ddc_i2c.get_clk_mask =
766 radeon_bios32(dev_priv, lcd_ddc_info + 3);
767 mode_info->bios_connector[4].ddc_i2c.get_data_mask =
768 radeon_bios32(dev_priv, lcd_ddc_info + 7);
773 DRM_DEBUG("LCD DDC Info Table found!\n");
776 mode_info->bios_connector[4].ddc_i2c.valid = false;
780 if (dev_priv->chip_family != CHIP_R100 &&
781 dev_priv->chip_family != CHIP_R200) {
782 uint32_t tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
784 if (radeon_bios8(dev_priv, tv_info + 6) == 'T') {
785 mode_info->bios_connector[5].valid = true;
786 mode_info->bios_connector[5].connector_type = CONNECTOR_DIN;
787 mode_info->bios_connector[5].dac_type = DAC_TVDAC;
788 mode_info->bios_connector[5].tmds_type = TMDS_NONE;
789 mode_info->bios_connector[5].ddc_i2c.valid = false;
795 DRM_DEBUG("BIOS Connector table\n");
796 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
797 if (!mode_info->bios_connector[i].valid)
800 DRM_DEBUG("Port %d: ddc_type 0x%x, dac_type %d, tmds_type %d, connector type %d, hpd_mask %d\n",
801 i, mode_info->bios_connector[i].ddc_i2c.mask_clk_reg,
802 mode_info->bios_connector[i].dac_type,
803 mode_info->bios_connector[i].tmds_type,
804 mode_info->bios_connector[i].connector_type,
805 mode_info->bios_connector[i].hpd_mask);