linux-core/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon_drv.h"
  30
  31 /* old legacy ATI BIOS routines */
  32
  33 /* COMBIOS table offsets */
  34 enum radeon_combios_table_offset
  35 {
  36         /* absolute offset tables */
  37         COMBIOS_ASIC_INIT_1_TABLE,
  38         COMBIOS_BIOS_SUPPORT_TABLE,
  39         COMBIOS_DAC_PROGRAMMING_TABLE,
  40         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  41         COMBIOS_CRTC_INFO_TABLE,
  42         COMBIOS_PLL_INFO_TABLE,
  43         COMBIOS_TV_INFO_TABLE,
  44         COMBIOS_DFP_INFO_TABLE,
  45         COMBIOS_HW_CONFIG_INFO_TABLE,
  46         COMBIOS_MULTIMEDIA_INFO_TABLE,
  47         COMBIOS_TV_STD_PATCH_TABLE,
  48         COMBIOS_LCD_INFO_TABLE,
  49         COMBIOS_MOBILE_INFO_TABLE,
  50         COMBIOS_PLL_INIT_TABLE,
  51         COMBIOS_MEM_CONFIG_TABLE,
  52         COMBIOS_SAVE_MASK_TABLE,
  53         COMBIOS_HARDCODED_EDID_TABLE,
  54         COMBIOS_ASIC_INIT_2_TABLE,
  55         COMBIOS_CONNECTOR_INFO_TABLE,
  56         COMBIOS_DYN_CLK_1_TABLE,
  57         COMBIOS_RESERVED_MEM_TABLE,
  58         COMBIOS_EXT_TMDS_INFO_TABLE,
  59         COMBIOS_MEM_CLK_INFO_TABLE,
  60         COMBIOS_EXT_DAC_INFO_TABLE,
  61         COMBIOS_MISC_INFO_TABLE,
  62         COMBIOS_CRT_INFO_TABLE,
  63         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  64         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  65         COMBIOS_FAN_SPEED_INFO_TABLE,
  66         COMBIOS_OVERDRIVE_INFO_TABLE,
  67         COMBIOS_OEM_INFO_TABLE,
  68         COMBIOS_DYN_CLK_2_TABLE,
  69         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  70         COMBIOS_I2C_INFO_TABLE,
  71         /* relative offset tables */
  72         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
  73         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
  74         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
  75         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
  76         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
  77         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
  78         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
  79         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
  80         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
  81         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
  82 };
  83
  84 enum radeon_combios_ddc
  85 {
  86     DDC_NONE_DETECTED,
  87     DDC_MONID,
  88     DDC_DVI,
  89     DDC_VGA,
  90     DDC_CRT2,
  91     DDC_LCD,
  92     DDC_GPIO,
  93 };
  94
  95 enum radeon_combios_connector
  96 {
  97     CONNECTOR_NONE_LEGACY,
  98     CONNECTOR_PROPRIETARY_LEGACY,
  99     CONNECTOR_CRT_LEGACY,
 100     CONNECTOR_DVI_I_LEGACY,
 101     CONNECTOR_DVI_D_LEGACY,
 102     CONNECTOR_CTV_LEGACY,
 103     CONNECTOR_STV_LEGACY,
 104     CONNECTOR_UNSUPPORTED_LEGACY
 105 };
 106
 107 static uint16_t combios_get_table_offset(struct drm_device *dev, enum radeon_combios_table_offset table)
 108 {
 109         struct drm_radeon_private *dev_priv = dev->dev_private;
 110         int rev;
 111         uint16_t offset = 0, check_offset;
 112
 113         switch (table) {
 114         /* absolute offset tables */
 115         case COMBIOS_ASIC_INIT_1_TABLE:
 116                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0xc);
 117                 if (check_offset)
 118                         offset = check_offset;
 119                 break;
 120         case COMBIOS_BIOS_SUPPORT_TABLE:
 121                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x14);
 122                 if (check_offset)
 123                         offset = check_offset;
 124                 break;
 125         case COMBIOS_DAC_PROGRAMMING_TABLE:
 126                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x2a);
 127                 if (check_offset)
 128                         offset = check_offset;
 129                 break;
 130         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 131                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x2c);
 132                 if (check_offset)
 133                         offset = check_offset;
 134                 break;
 135         case COMBIOS_CRTC_INFO_TABLE:
 136                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x2e);
 137                 if (check_offset)
 138                         offset = check_offset;
 139                 break;
 140         case COMBIOS_PLL_INFO_TABLE:
 141                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x30);
 142                 if (check_offset)
 143                         offset = check_offset;
 144                 break;
 145         case COMBIOS_TV_INFO_TABLE:
 146                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x32);
 147                 if (check_offset)
 148                         offset = check_offset;
 149                 break;
 150         case COMBIOS_DFP_INFO_TABLE:
 151                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x34);
 152                 if (check_offset)
 153                         offset = check_offset;
 154                 break;
 155         case COMBIOS_HW_CONFIG_INFO_TABLE:
 156                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x36);
 157                 if (check_offset)
 158                         offset = check_offset;
 159                 break;
 160         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 161                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x38);
 162                 if (check_offset)
 163                         offset = check_offset;
 164                 break;
 165         case COMBIOS_TV_STD_PATCH_TABLE:
 166                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x3e);
 167                 if (check_offset)
 168                         offset = check_offset;
 169                 break;
 170         case COMBIOS_LCD_INFO_TABLE:
 171                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x40);
 172                 if (check_offset)
 173                         offset = check_offset;
 174                 break;
 175         case COMBIOS_MOBILE_INFO_TABLE:
 176                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x42);
 177                 if (check_offset)
 178                         offset = check_offset;
 179                 break;
 180         case COMBIOS_PLL_INIT_TABLE:
 181                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x46);
 182                 if (check_offset)
 183                         offset = check_offset;
 184                 break;
 185         case COMBIOS_MEM_CONFIG_TABLE:
 186                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x48);
 187                 if (check_offset)
 188                         offset = check_offset;
 189                 break;
 190         case COMBIOS_SAVE_MASK_TABLE:
 191                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x4a);
 192                 if (check_offset)
 193                         offset = check_offset;
 194                 break;
 195         case COMBIOS_HARDCODED_EDID_TABLE:
 196                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x4c);
 197                 if (check_offset)
 198                         offset = check_offset;
 199                 break;
 200         case COMBIOS_ASIC_INIT_2_TABLE:
 201                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x4e);
 202                 if (check_offset)
 203                         offset = check_offset;
 204                 break;
 205         case COMBIOS_CONNECTOR_INFO_TABLE:
 206                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x50);
 207                 if (check_offset)
 208                         offset = check_offset;
 209                 break;
 210         case COMBIOS_DYN_CLK_1_TABLE:
 211                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x52);
 212                 if (check_offset)
 213                         offset = check_offset;
 214                 break;
 215         case COMBIOS_RESERVED_MEM_TABLE:
 216                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x54);
 217                 if (check_offset)
 218                         offset = check_offset;
 219                 break;
 220         case COMBIOS_EXT_TMDS_INFO_TABLE:
 221                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x58);
 222                 if (check_offset)
 223                         offset = check_offset;
 224                 break;
 225         case COMBIOS_MEM_CLK_INFO_TABLE:
 226                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x5a);
 227                 if (check_offset)
 228                         offset = check_offset;
 229                 break;
 230         case COMBIOS_EXT_DAC_INFO_TABLE:
 231                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x5c);
 232                 if (check_offset)
 233                         offset = check_offset;
 234                 break;
 235         case COMBIOS_MISC_INFO_TABLE:
 236                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x5e);
 237                 if (check_offset)
 238                         offset = check_offset;
 239                 break;
 240         case COMBIOS_CRT_INFO_TABLE:
 241                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x60);
 242                 if (check_offset)
 243                         offset = check_offset;
 244                 break;
 245         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 246                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x62);
 247                 if (check_offset)
 248                         offset = check_offset;
 249                 break;
 250         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 251                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x64);
 252                 if (check_offset)
 253                         offset = check_offset;
 254                 break;
 255         case COMBIOS_FAN_SPEED_INFO_TABLE:
 256                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x66);
 257                 if (check_offset)
 258                         offset = check_offset;
 259                 break;
 260         case COMBIOS_OVERDRIVE_INFO_TABLE:
 261                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x68);
 262                 if (check_offset)
 263                         offset = check_offset;
 264                 break;
 265         case COMBIOS_OEM_INFO_TABLE:
 266                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x6a);
 267                 if (check_offset)
 268                         offset = check_offset;
 269                 break;
 270         case COMBIOS_DYN_CLK_2_TABLE:
 271                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x6c);
 272                 if (check_offset)
 273                         offset = check_offset;
 274                 break;
 275         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 276                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x6e);
 277                 if (check_offset)
 278                         offset = check_offset;
 279                 break;
 280         case COMBIOS_I2C_INFO_TABLE:
 281                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x70);
 282                 if (check_offset)
 283                         offset = check_offset;
 284                 break;
 285         /* relative offset tables */
 286         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 287                 check_offset = combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 288                 if (check_offset) {
 289                         rev = radeon_bios8(dev_priv, check_offset);
 290                         if (rev > 0) {
 291                                 check_offset = radeon_bios16(dev_priv, check_offset + 0x3);
 292                                 if (check_offset)
 293                                         offset = check_offset;
 294                         }
 295                 }
 296                 break;
 297         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 298                 check_offset = combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 299                 if (check_offset) {
 300                         rev = radeon_bios8(dev_priv, check_offset);
 301                         if (rev > 0) {
 302                                 check_offset = radeon_bios16(dev_priv, check_offset + 0x5);
 303                                 if (check_offset)
 304                                         offset = check_offset;
 305                         }
 306                 }
 307                 break;
 308         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 309                 check_offset = combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 310                 if (check_offset) {
 311                         rev = radeon_bios8(dev_priv, check_offset);
 312                         if (rev == 2) {
 313                                 check_offset = radeon_bios16(dev_priv, check_offset + 0x9);
 314                                 if (check_offset)
 315                                         offset = check_offset;
 316                         }
 317                 }
 318                 break;
 319         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 320                 check_offset = combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 321                 if (check_offset) {
 322                         while (radeon_bios8(dev_priv, check_offset++));
 323                         check_offset += 2;
 324                         if (check_offset)
 325                                 offset = check_offset;
 326                 }
 327                 break;
 328         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 329                 check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 330                 if (check_offset) {
 331                         check_offset = radeon_bios16(dev_priv, check_offset + 0x11);
 332                         if (check_offset)
 333                                 offset = check_offset;
 334                 }
 335                 break;
 336         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 337                 check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 338                 if (check_offset) {
 339                         check_offset = radeon_bios16(dev_priv, check_offset + 0x13);
 340                         if (check_offset)
 341                                 offset = check_offset;
 342                 }
 343                 break;
 344         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 345                 check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 346                 if (check_offset) {
 347                         check_offset = radeon_bios16(dev_priv, check_offset + 0x15);
 348                         if (check_offset)
 349                                 offset = check_offset;
 350                 }
 351                 break;
 352         case COMBIOS_TMDS_POWER_TABLE:          /* offset from mobile info */
 353                 check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 354                 if (check_offset) {
 355                         check_offset = radeon_bios16(dev_priv, check_offset + 0x17);
 356                         if (check_offset)
 357                                 offset = check_offset;
 358                 }
 359                 break;
 360         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 361                 check_offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 362                 if (check_offset) {
 363                         check_offset = radeon_bios16(dev_priv, check_offset + 0x2);
 364                         if (check_offset)
 365                                 offset = check_offset;
 366                 }
 367                 break;
 368         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 369                 check_offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 370                 if (check_offset) {
 371                         check_offset = radeon_bios16(dev_priv, check_offset + 0x4);
 372                         if (check_offset)
 373                                 offset = check_offset;
 374                 }
 375                 break;
 376         default:
 377                 break;
 378         }
 379
 380         return offset;
 381
 382 }
 383
 384 struct radeon_i2c_bus_rec combios_setup_i2c_bus(int ddc_line)
 385 {
 386         struct radeon_i2c_bus_rec i2c;
 387
 388         i2c.mask_clk_mask = RADEON_GPIO_EN_1;
 389         i2c.mask_data_mask = RADEON_GPIO_EN_0;
 390         i2c.a_clk_mask = RADEON_GPIO_A_1;
 391         i2c.a_data_mask = RADEON_GPIO_A_0;
 392         i2c.put_clk_mask = RADEON_GPIO_EN_1;
 393         i2c.put_data_mask = RADEON_GPIO_EN_0;
 394         i2c.get_clk_mask = RADEON_GPIO_Y_1;
 395         i2c.get_data_mask = RADEON_GPIO_Y_0;
 396         if ((ddc_line == RADEON_LCD_GPIO_MASK) ||
 397             (ddc_line == RADEON_MDGPIO_EN_REG)) {
 398                 i2c.mask_clk_reg = ddc_line;
 399                 i2c.mask_data_reg = ddc_line;
 400                 i2c.a_clk_reg = ddc_line;
 401                 i2c.a_data_reg = ddc_line;
 402                 i2c.put_clk_reg = ddc_line;
 403                 i2c.put_data_reg = ddc_line;
 404                 i2c.get_clk_reg = ddc_line + 4;
 405                 i2c.get_data_reg = ddc_line + 4;
 406         } else {
 407                 i2c.mask_clk_reg = ddc_line;
 408                 i2c.mask_data_reg = ddc_line;
 409                 i2c.a_clk_reg = ddc_line;
 410                 i2c.a_data_reg = ddc_line;
 411                 i2c.put_clk_reg = ddc_line;
 412                 i2c.put_data_reg = ddc_line;
 413                 i2c.get_clk_reg = ddc_line;
 414                 i2c.get_data_reg = ddc_line;
 415         }
 416
 417         if (ddc_line)
 418                 i2c.valid = true;
 419         else
 420                 i2c.valid = false;
 421
 422         return i2c;
 423 }
 424
 425 bool radeon_combios_get_clock_info(struct drm_device *dev)
 426 {
 427         struct drm_radeon_private *dev_priv = dev->dev_private;
 428         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 429         uint16_t pll_info;
 430         struct radeon_pll *p1pll = &mode_info->p1pll;
 431         struct radeon_pll *p2pll = &mode_info->p2pll;
 432         struct radeon_pll *spll = &mode_info->spll;
 433         struct radeon_pll *mpll = &mode_info->mpll;
 434         int8_t rev;
 435         uint16_t sclk, mclk;
 436
 437         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 438         if (pll_info) {
 439                 rev = radeon_bios8(dev_priv, pll_info);
 440
 441                 /* pixel clocks */
 442                 p1pll->reference_freq = radeon_bios16(dev_priv, pll_info + 0xe);
 443                 p1pll->reference_div = radeon_bios16(dev_priv, pll_info + 0x10);
 444                 p1pll->pll_out_min = radeon_bios32(dev_priv, pll_info + 0x12);
 445                 p1pll->pll_out_max = radeon_bios32(dev_priv, pll_info + 0x16);
 446
 447                 if (rev > 9) {
 448                         p1pll->pll_in_min = radeon_bios32(dev_priv, pll_info + 0x36);
 449                         p1pll->pll_in_max = radeon_bios32(dev_priv, pll_info + 0x3a);
 450                 } else {
 451                         p1pll->pll_in_min = 40;
 452                         p1pll->pll_in_max = 500;
 453                 }
 454                 *p2pll = *p1pll;
 455
 456                 /* system clock */
 457                 spll->reference_freq = radeon_bios16(dev_priv, pll_info + 0x1a);
 458                 spll->reference_div = radeon_bios16(dev_priv, pll_info + 0x1c);
 459                 spll->pll_out_min = radeon_bios32(dev_priv, pll_info + 0x1e);
 460                 spll->pll_out_max = radeon_bios32(dev_priv, pll_info + 0x22);
 461
 462                 if (rev > 10) {
 463                         spll->pll_in_min = radeon_bios32(dev_priv, pll_info + 0x48);
 464                         spll->pll_in_max = radeon_bios32(dev_priv, pll_info + 0x4c);
 465                 } else {
 466                         /* ??? */
 467                         spll->pll_in_min = 40;
 468                         spll->pll_in_max = 500;
 469                 }
 470
 471                 /* memory clock */
 472                 mpll->reference_freq = radeon_bios16(dev_priv, pll_info + 0x26);
 473                 mpll->reference_div = radeon_bios16(dev_priv, pll_info + 0x28);
 474                 mpll->pll_out_min = radeon_bios32(dev_priv, pll_info + 0x2a);
 475                 mpll->pll_out_max = radeon_bios32(dev_priv, pll_info + 0x2e);
 476
 477                 if (rev > 10) {
 478                         mpll->pll_in_min = radeon_bios32(dev_priv, pll_info + 0x5a);
 479                         mpll->pll_in_max = radeon_bios32(dev_priv, pll_info + 0x5e);
 480                 } else {
 481                         /* ??? */
 482                         mpll->pll_in_min = 40;
 483                         mpll->pll_in_max = 500;
 484                 }
 485
 486                 /* default sclk/mclk */
 487                 sclk = radeon_bios16(dev_priv, pll_info + 0x8);
 488                 mclk = radeon_bios16(dev_priv, pll_info + 0xa);
 489                 if (sclk == 0)
 490                         sclk = 200;
 491                 if (mclk == 0)
 492                         mclk = 200;
 493
 494                 mode_info->sclk = sclk;
 495                 mode_info->mclk = mclk;
 496
 497                 return true;
 498         }
 499         return false;
 500 }
 501
 502 bool radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder)
 503 {
 504         struct drm_device *dev = encoder->base.dev;
 505         struct drm_radeon_private *dev_priv = dev->dev_private;
 506         uint16_t dac_info;
 507         uint8_t rev, bg, dac;
 508
 509         /* check CRT table */
 510         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 511         if (dac_info) {
 512                 rev = radeon_bios8(dev_priv, dac_info) & 0x3;
 513                 if (rev < 2) {
 514                         bg = radeon_bios8(dev_priv, dac_info + 0x2) & 0xf;
 515                         dac = (radeon_bios8(dev_priv, dac_info + 0x2) >> 4) & 0xf;
 516                         encoder->ps2_pdac_adj = (bg << 8) | (dac);
 517
 518                         return true;
 519                 } else {
 520                         bg = radeon_bios8(dev_priv, dac_info + 0x2) & 0xf;
 521                         dac = radeon_bios8(dev_priv, dac_info + 0x3) & 0xf;
 522                         encoder->ps2_pdac_adj = (bg << 8) | (dac);
 523
 524                         return true;
 525                 }
 526
 527         }
 528
 529         return false;
 530 }
 531
 532 bool radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder)
 533 {
 534         struct drm_device *dev = encoder->base.dev;
 535         struct drm_radeon_private *dev_priv = dev->dev_private;
 536         uint16_t dac_info;
 537         uint8_t rev, bg, dac;
 538
 539         /* first check TV table */
 540         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 541         if (dac_info) {
 542                 rev = radeon_bios8(dev_priv, dac_info + 0x3);
 543                 if (rev > 4) {
 544                         bg = radeon_bios8(dev_priv, dac_info + 0xc) & 0xf;
 545                         dac = radeon_bios8(dev_priv, dac_info + 0xd) & 0xf;
 546                         encoder->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 547
 548                         bg = radeon_bios8(dev_priv, dac_info + 0xe) & 0xf;
 549                         dac = radeon_bios8(dev_priv, dac_info + 0xf) & 0xf;
 550                         encoder->pal_tvdac_adj = (bg << 16) | (dac << 20);
 551
 552                         bg = radeon_bios8(dev_priv, dac_info + 0x10) & 0xf;
 553                         dac = radeon_bios8(dev_priv, dac_info + 0x11) & 0xf;
 554                         encoder->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 555
 556                         return true;
 557                 } else if (rev > 1) {
 558                         bg = radeon_bios8(dev_priv, dac_info + 0xc) & 0xf;
 559                         dac = (radeon_bios8(dev_priv, dac_info + 0xc) >> 4) & 0xf;
 560                         encoder->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 561
 562                         bg = radeon_bios8(dev_priv, dac_info + 0xd) & 0xf;
 563                         dac = (radeon_bios8(dev_priv, dac_info + 0xd) >> 4) & 0xf;
 564                         encoder->pal_tvdac_adj = (bg << 16) | (dac << 20);
 565
 566                         bg = radeon_bios8(dev_priv, dac_info + 0xe) & 0xf;
 567                         dac = (radeon_bios8(dev_priv, dac_info + 0xe) >> 4) & 0xf;
 568                         encoder->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 569
 570                         return true;
 571                 }
 572         }
 573
 574         /* then check CRT table */
 575         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 576         if (dac_info) {
 577                 rev = radeon_bios8(dev_priv, dac_info) & 0x3;
 578                 if (rev < 2) {
 579                         bg = radeon_bios8(dev_priv, dac_info + 0x3) & 0xf;
 580                         dac = (radeon_bios8(dev_priv, dac_info + 0x3) >> 4) & 0xf;
 581                         encoder->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 582                         encoder->pal_tvdac_adj = encoder->ps2_tvdac_adj;
 583                         encoder->ntsc_tvdac_adj = encoder->ps2_tvdac_adj;
 584
 585                         return true;
 586                 } else {
 587                         bg = radeon_bios8(dev_priv, dac_info + 0x4) & 0xf;
 588                         dac = radeon_bios8(dev_priv, dac_info + 0x5) & 0xf;
 589                         encoder->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 590                         encoder->pal_tvdac_adj = encoder->ps2_tvdac_adj;
 591                         encoder->ntsc_tvdac_adj = encoder->ps2_tvdac_adj;
 592
 593                         return true;
 594                 }
 595
 596         }
 597
 598         return false;
 599 }
 600
 601 bool radeon_combios_get_tv_info(struct radeon_encoder *encoder)
 602 {
 603         struct drm_device *dev = encoder->base.dev;
 604         struct drm_radeon_private *dev_priv = dev->dev_private;
 605         uint16_t tv_info;
 606
 607         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 608         if (tv_info) {
 609                 if (radeon_bios8(dev_priv, tv_info + 6) == 'T') {
 610                         switch (radeon_bios8(dev_priv, tv_info + 7) & 0xf) {
 611                         case 1:
 612                                 encoder->tv_std = TV_STD_NTSC;
 613                                 DRM_INFO("Default TV standard: NTSC\n");
 614                                 break;
 615                         case 2:
 616                                 encoder->tv_std = TV_STD_PAL;
 617                                 DRM_INFO("Default TV standard: PAL\n");
 618                                 break;
 619                         case 3:
 620                                 encoder->tv_std = TV_STD_PAL_M;
 621                                 DRM_INFO("Default TV standard: PAL-M\n");
 622                                 break;
 623                         case 4:
 624                                 encoder->tv_std = TV_STD_PAL_60;
 625                                 DRM_INFO("Default TV standard: PAL-60\n");
 626                                 break;
 627                         case 5:
 628                                 encoder->tv_std = TV_STD_NTSC_J;
 629                                 DRM_INFO("Default TV standard: NTSC-J\n");
 630                                 break;
 631                         case 6:
 632                                 encoder->tv_std = TV_STD_SCART_PAL;
 633                                 DRM_INFO("Default TV standard: SCART-PAL\n");
 634                                 break;
 635                         default:
 636                                 encoder->tv_std = TV_STD_NTSC;
 637                                 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
 638                                 break;
 639                         }
 640
 641                         switch ((radeon_bios8(dev_priv, tv_info + 9) >> 2) & 0x3) {
 642                         case 0:
 643                                 DRM_INFO("29.498928713 MHz TV ref clk\n");
 644                                 break;
 645                         case 1:
 646                                 DRM_INFO("28.636360000 MHz TV ref clk\n");
 647                                 break;
 648                         case 2:
 649                                 DRM_INFO("14.318180000 MHz TV ref clk\n");
 650                                 break;
 651                         case 3:
 652                                 DRM_INFO("27.000000000 MHz TV ref clk\n");
 653                                 break;
 654                         default:
 655                                 break;
 656                         }
 657                         return true;
 658                 }
 659         }
 660         return false;
 661 }
 662
 663 bool radeon_combios_get_lvds_info(struct radeon_encoder *encoder)
 664 {
 665         struct drm_device *dev = encoder->base.dev;
 666         struct drm_radeon_private *dev_priv = dev->dev_private;
 667         uint16_t lcd_info;
 668         uint32_t panel_setup;
 669         char stmp[30];
 670         int tmp, i;
 671
 672         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
 673
 674         if (lcd_info) {
 675                 for (i = 0; i < 24; i++)
 676                         stmp[i] = radeon_bios8(dev_priv, lcd_info + i + 1);
 677                 stmp[24] = 0;
 678
 679                 DRM_INFO("Panel ID String: %s\n", stmp);
 680
 681                 encoder->panel_xres = radeon_bios16(dev_priv, lcd_info + 25);
 682                 encoder->panel_yres = radeon_bios16(dev_priv, lcd_info + 27);
 683
 684                 DRM_INFO("Panel Size %dx%d\n", encoder->panel_xres, encoder->panel_yres);
 685
 686                 encoder->panel_vcc_delay = radeon_bios16(dev_priv, lcd_info + 44);
 687                 if (encoder->panel_vcc_delay > 2000 || encoder->panel_vcc_delay < 0)
 688                         encoder->panel_vcc_delay = 2000;
 689
 690                 encoder->panel_pwr_delay = radeon_bios16(dev_priv, lcd_info + 0x24);
 691                 encoder->panel_digon_delay = radeon_bios16(dev_priv, lcd_info + 0x38) & 0xf;
 692                 encoder->panel_blon_delay = (radeon_bios16(dev_priv, lcd_info + 0x38) >> 4) & 0xf;
 693
 694                 encoder->panel_ref_divider = radeon_bios16(dev_priv, lcd_info + 46);
 695                 encoder->panel_post_divider = radeon_bios8(dev_priv, lcd_info + 48);
 696                 encoder->panel_fb_divider = radeon_bios16(dev_priv, lcd_info + 49);
 697                 if ((encoder->panel_ref_divider != 0) &&
 698                     (encoder->panel_fb_divider > 3))
 699                         encoder->use_bios_dividers = true;
 700
 701                 panel_setup = radeon_bios32(dev_priv, lcd_info + 0x39);
 702                 encoder->lvds_gen_cntl = 0xff00;
 703                 if (panel_setup & 0x1)
 704                         encoder->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
 705
 706                 if ((panel_setup >> 4) & 0x1)
 707                         encoder->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
 708
 709                 switch ((panel_setup >> 8) & 0x7) {
 710                 case 0:
 711                         encoder->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
 712                         break;
 713                 case 1:
 714                         encoder->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
 715                         break;
 716                 case 2:
 717                         encoder->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
 718                         break;
 719                 default:
 720                         break;
 721                 }
 722
 723                 if ((panel_setup >> 16) & 0x1)
 724                         encoder->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
 725
 726                 if ((panel_setup >> 17) & 0x1)
 727                         encoder->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
 728
 729                 if ((panel_setup >> 18) & 0x1)
 730                         encoder->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
 731
 732                 if ((panel_setup >> 23) & 0x1)
 733                         encoder->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
 734
 735                 encoder->lvds_gen_cntl |= (panel_setup & 0xf0000000);
 736
 737
 738                 for (i = 0; i < 32; i++) {
 739                         tmp = radeon_bios16(dev_priv, lcd_info + 64 + i * 2);
 740                         if (tmp == 0) break;
 741
 742                         if ((radeon_bios16(dev_priv, tmp) == encoder->panel_xres) &&
 743                             (radeon_bios16(dev_priv, tmp + 2) == encoder->panel_yres)) {
 744                                 encoder->hblank = (radeon_bios16(dev_priv, tmp + 17) -
 745                                                    radeon_bios16(dev_priv, tmp + 19)) * 8;
 746                                 encoder->hoverplus = (radeon_bios16(dev_priv, tmp + 21) -
 747                                                       radeon_bios16(dev_priv, tmp + 19) - 1) * 8;
 748                                 encoder->hsync_width = radeon_bios8(dev_priv, tmp + 23) * 8;
 749
 750                                 encoder->vblank = (radeon_bios16(dev_priv, tmp + 24) -
 751                                                    radeon_bios16(dev_priv, tmp + 26));
 752                                 encoder->voverplus = ((radeon_bios16(dev_priv, tmp + 28) & 0x7ff) -
 753                                                       radeon_bios16(dev_priv, tmp + 26));
 754                                 encoder->vsync_width = ((radeon_bios16(dev_priv, tmp + 28) & 0xf800) >> 11);
 755                                 encoder->dotclock = radeon_bios16(dev_priv, tmp + 9) * 10;
 756                                 encoder->flags = 0;
 757                         }
 758                 }
 759                 return true;
 760         }
 761         DRM_INFO("No panel info found in BIOS\n");
 762         return false;
 763
 764 }
 765
 766 bool radeon_combios_get_tmds_info(struct radeon_encoder *encoder)
 767 {
 768         struct drm_device *dev = encoder->base.dev;
 769         struct drm_radeon_private *dev_priv = dev->dev_private;
 770         uint16_t tmds_info;
 771         int i, n;
 772         uint8_t ver;
 773
 774         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
 775
 776         if (tmds_info) {
 777                 ver = radeon_bios8(dev_priv, tmds_info);
 778                 DRM_INFO("DFP table revision: %d\n", ver);
 779                 if (ver == 3) {
 780                         n = radeon_bios8(dev_priv, tmds_info + 5) + 1;
 781                         if (n > 4)
 782                                 n = 4;
 783                         for (i = 0; i < n; i++) {
 784                                 encoder->tmds_pll[i].value = radeon_bios32(dev_priv, tmds_info + i * 10 + 0x08);
 785                                 encoder->tmds_pll[i].freq = radeon_bios16(dev_priv, tmds_info + i * 10 + 0x10);
 786                         }
 787                         return true;
 788                 } else if (ver == 4) {
 789                         int stride = 0;
 790                         n = radeon_bios8(dev_priv, tmds_info + 5) + 1;
 791                         if (n > 4)
 792                                 n = 4;
 793                         for (i = 0; i < n; i++) {
 794                                 encoder->tmds_pll[i].value = radeon_bios32(dev_priv, tmds_info + stride + 0x08);
 795                                 encoder->tmds_pll[i].freq = radeon_bios16(dev_priv, tmds_info + stride + 0x10);
 796                                 if (i == 0)
 797                                         stride += 10;
 798                                 else
 799                                         stride += 6;
 800                         }
 801                         return true;
 802                 }
 803         }
 804
 805         DRM_INFO("No TMDS info found in BIOS\n");
 806         return false;
 807 }
 808
 809 void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder)
 810 {
 811         struct drm_device *dev = encoder->base.dev;
 812         struct drm_radeon_private *dev_priv = dev->dev_private;
 813         uint16_t ext_tmds_info;
 814         uint8_t ver;
 815
 816         ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
 817         if (ext_tmds_info) {
 818                 ver = radeon_bios8(dev_priv, ext_tmds_info);
 819                 DRM_INFO("External TMDS Table revision: %d\n", ver);
 820                 // TODO
 821         }
 822 }
 823
 824 static void radeon_apply_legacy_quirks(struct drm_device *dev, int bios_index)
 825 {
 826         struct drm_radeon_private *dev_priv = dev->dev_private;
 827         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 828
 829         /* XPRESS DDC quirks */
 830         if ((dev_priv->chip_family == CHIP_RS400 ||
 831              dev_priv->chip_family == CHIP_RS480) &&
 832             mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) {
 833                 mode_info->bios_connector[bios_index].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
 834         } else if ((dev_priv->chip_family == CHIP_RS400 ||
 835                     dev_priv->chip_family == CHIP_RS480) &&
 836                    mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_reg == RADEON_GPIO_MONID) {
 837                 mode_info->bios_connector[bios_index].ddc_i2c.valid = true;
 838                 mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_mask = (0x20 << 8);
 839                 mode_info->bios_connector[bios_index].ddc_i2c.mask_data_mask = 0x80;
 840                 mode_info->bios_connector[bios_index].ddc_i2c.a_clk_mask = (0x20 << 8);
 841                 mode_info->bios_connector[bios_index].ddc_i2c.a_data_mask = 0x80;
 842                 mode_info->bios_connector[bios_index].ddc_i2c.put_clk_mask = (0x20 << 8);
 843                 mode_info->bios_connector[bios_index].ddc_i2c.put_data_mask = 0x80;
 844                 mode_info->bios_connector[bios_index].ddc_i2c.get_clk_mask = (0x20 << 8);
 845                 mode_info->bios_connector[bios_index].ddc_i2c.get_data_mask = 0x80;
 846                 mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 847                 mode_info->bios_connector[bios_index].ddc_i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 848                 mode_info->bios_connector[bios_index].ddc_i2c.a_clk_reg = RADEON_GPIOPAD_A;
 849                 mode_info->bios_connector[bios_index].ddc_i2c.a_data_reg = RADEON_GPIOPAD_A;
 850                 mode_info->bios_connector[bios_index].ddc_i2c.put_clk_reg = RADEON_GPIOPAD_EN;
 851                 mode_info->bios_connector[bios_index].ddc_i2c.put_data_reg = RADEON_GPIOPAD_EN;
 852                 mode_info->bios_connector[bios_index].ddc_i2c.get_clk_reg = RADEON_LCD_GPIO_Y_REG;
 853                 mode_info->bios_connector[bios_index].ddc_i2c.get_data_reg = RADEON_LCD_GPIO_Y_REG;
 854         }
 855
 856         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
 857            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
 858         if (dev->pdev->device == 0x515e &&
 859             dev->pdev->subsystem_vendor == 0x1014) {
 860                 if (mode_info->bios_connector[bios_index].connector_type == CONNECTOR_VGA &&
 861                     mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) {
 862                         mode_info->bios_connector[bios_index].valid = false;
 863                 }
 864         }
 865
 866         /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
 867         if (dev->pdev->device == 0x5159 &&
 868             dev->pdev->subsystem_vendor == 0x1002 &&
 869             dev->pdev->subsystem_device == 0x013a) {
 870                 if (mode_info->bios_connector[bios_index].connector_type == CONNECTOR_DVI_I)
 871                         mode_info->bios_connector[bios_index].connector_type = CONNECTOR_VGA;
 872
 873         }
 874
 875         /* X300 card with extra non-existent DVI port */
 876         if (dev->pdev->device == 0x5B60 &&
 877             dev->pdev->subsystem_vendor == 0x17af &&
 878             dev->pdev->subsystem_device == 0x201e &&
 879             bios_index == 2) {
 880                 if (mode_info->bios_connector[bios_index].connector_type == CONNECTOR_DVI_I)
 881                         mode_info->bios_connector[bios_index].valid = false;
 882         }
 883
 884 }
 885
 886 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
 887 {
 888         struct drm_radeon_private *dev_priv = dev->dev_private;
 889         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 890         uint32_t conn_info, entry;
 891         uint16_t tmp;
 892         enum radeon_combios_ddc ddc_type;
 893         enum radeon_combios_connector connector_type;
 894         int i;
 895
 896         DRM_DEBUG("\n");
 897         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
 898         if (conn_info) {
 899                 for (i = 0; i < 4; i++) {
 900                         entry = conn_info + 2 + i * 2;
 901
 902                         if (!radeon_bios16(dev_priv, entry))
 903                                     break;
 904
 905                         mode_info->bios_connector[i].valid = true;
 906
 907                         tmp = radeon_bios16(dev_priv, entry);
 908
 909                         connector_type = (tmp >> 12) & 0xf;
 910                         mode_info->bios_connector[i].connector_type = connector_type;
 911
 912                         switch(connector_type) {
 913                         case CONNECTOR_PROPRIETARY_LEGACY:
 914                                 mode_info->bios_connector[i].connector_type = CONNECTOR_DVI_D;
 915                                 break;
 916                         case CONNECTOR_CRT_LEGACY:
 917                                 mode_info->bios_connector[i].connector_type = CONNECTOR_VGA;
 918                                 break;
 919                         case CONNECTOR_DVI_I_LEGACY:
 920                                 mode_info->bios_connector[i].connector_type = CONNECTOR_DVI_I;
 921                                 break;
 922                         case CONNECTOR_DVI_D_LEGACY:
 923                                 mode_info->bios_connector[i].connector_type = CONNECTOR_DVI_D;
 924                                 break;
 925                         case CONNECTOR_CTV_LEGACY:
 926                                 mode_info->bios_connector[i].connector_type = CONNECTOR_CTV;
 927                                 break;
 928                         case CONNECTOR_STV_LEGACY:
 929                                 mode_info->bios_connector[i].connector_type = CONNECTOR_STV;
 930                                 break;
 931                         default:
 932                                 DRM_ERROR("Unknown connector type: %d\n", connector_type);
 933                                 mode_info->bios_connector[i].valid = false;
 934                                 break;
 935                         }
 936
 937                         mode_info->bios_connector[i].ddc_i2c.valid = false;
 938
 939                         ddc_type = (tmp >> 8) & 0xf;
 940                         switch (ddc_type) {
 941                         case DDC_MONID:
 942                                 mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
 943                                 break;
 944                         case DDC_DVI:
 945                                 mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
 946                                 break;
 947                         case DDC_VGA:
 948                                 mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
 949                                 break;
 950                         case DDC_CRT2:
 951                                 mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
 952                                 break;
 953                         default:
 954                                 break;
 955                         }
 956
 957                         if (tmp & 0x1)
 958                                 mode_info->bios_connector[i].dac_type = DAC_TVDAC;
 959                         else
 960                                 mode_info->bios_connector[i].dac_type = DAC_PRIMARY;
 961
 962                         if ((dev_priv->chip_family == CHIP_RS300) ||
 963                             (dev_priv->chip_family == CHIP_RS400) ||
 964                             (dev_priv->chip_family == CHIP_RS480))
 965                                 mode_info->bios_connector[i].dac_type = DAC_TVDAC;
 966
 967                         if ((tmp >> 4) & 0x1)
 968                                 mode_info->bios_connector[i].tmds_type = TMDS_EXT;
 969                         else
 970                                 mode_info->bios_connector[i].tmds_type = TMDS_INT;
 971
 972                         radeon_apply_legacy_quirks(dev, i);
 973                 }
 974         } else {
 975                 uint16_t tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
 976                 if (tmds_info) {
 977                         DRM_DEBUG("Found DFP table, assuming DVI connector\n");
 978
 979                         mode_info->bios_connector[0].valid = true;
 980                         mode_info->bios_connector[0].connector_type = CONNECTOR_DVI_I;
 981                         mode_info->bios_connector[0].dac_type = DAC_PRIMARY;
 982                         mode_info->bios_connector[0].tmds_type = TMDS_INT;
 983                         mode_info->bios_connector[0].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
 984                 } else {
 985                         DRM_DEBUG("No connector info found\n");
 986                         return false;
 987                 }
 988         }
 989
 990         if (dev_priv->flags & RADEON_IS_MOBILITY ||
 991             dev_priv->chip_family == CHIP_RS400 ||
 992             dev_priv->chip_family == CHIP_RS480) {
 993                 uint16_t lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
 994                 if (lcd_info) {
 995                         uint16_t lcd_ddc_info = combios_get_table_offset(dev, COMBIOS_LCD_DDC_INFO_TABLE);
 996
 997                         mode_info->bios_connector[4].valid = true;
 998                         mode_info->bios_connector[4].connector_type = CONNECTOR_LVDS;
 999                         mode_info->bios_connector[4].dac_type = DAC_NONE;
1000                         mode_info->bios_connector[4].tmds_type = TMDS_NONE;
1001                         mode_info->bios_connector[4].ddc_i2c.valid = false;
1002
1003                         if (lcd_ddc_info) {
1004                                 ddc_type = radeon_bios8(dev_priv, lcd_ddc_info + 2);
1005                                 switch(ddc_type) {
1006                                 case DDC_MONID:
1007                                         mode_info->bios_connector[4].ddc_i2c =
1008                                                 combios_setup_i2c_bus(RADEON_GPIO_MONID);
1009                                         break;
1010                                 case DDC_DVI:
1011                                         mode_info->bios_connector[4].ddc_i2c =
1012                                                 combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1013                                         break;
1014                                 case DDC_VGA:
1015                                         mode_info->bios_connector[4].ddc_i2c =
1016                                                 combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1017                                         break;
1018                                 case DDC_CRT2:
1019                                         mode_info->bios_connector[4].ddc_i2c =
1020                                                 combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1021                                         break;
1022                                 case DDC_LCD:
1023                                         mode_info->bios_connector[4].ddc_i2c =
1024                                                 combios_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
1025                                         mode_info->bios_connector[4].ddc_i2c.mask_clk_mask =
1026                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
1027                                         mode_info->bios_connector[4].ddc_i2c.mask_data_mask =
1028                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
1029                                         mode_info->bios_connector[4].ddc_i2c.a_clk_mask =
1030                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
1031                                         mode_info->bios_connector[4].ddc_i2c.a_data_mask =
1032                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
1033                                         mode_info->bios_connector[4].ddc_i2c.put_clk_mask =
1034                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
1035                                         mode_info->bios_connector[4].ddc_i2c.put_data_mask =
1036                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
1037                                         mode_info->bios_connector[4].ddc_i2c.get_clk_mask =
1038                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
1039                                         mode_info->bios_connector[4].ddc_i2c.get_data_mask =
1040                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
1041                                         break;
1042                                 case DDC_GPIO:
1043                                         mode_info->bios_connector[4].ddc_i2c =
1044                                                 combios_setup_i2c_bus(RADEON_MDGPIO_EN_REG);
1045                                         mode_info->bios_connector[4].ddc_i2c.mask_clk_mask =
1046                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
1047                                         mode_info->bios_connector[4].ddc_i2c.mask_data_mask =
1048                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
1049                                         mode_info->bios_connector[4].ddc_i2c.a_clk_mask =
1050                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
1051                                         mode_info->bios_connector[4].ddc_i2c.a_data_mask =
1052                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
1053                                         mode_info->bios_connector[4].ddc_i2c.put_clk_mask =
1054                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
1055                                         mode_info->bios_connector[4].ddc_i2c.put_data_mask =
1056                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
1057                                         mode_info->bios_connector[4].ddc_i2c.get_clk_mask =
1058                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
1059                                         mode_info->bios_connector[4].ddc_i2c.get_data_mask =
1060                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
1061                                         break;
1062                                 default:
1063                                         break;
1064                                 }
1065                                 DRM_DEBUG("LCD DDC Info Table found!\n");
1066                         }
1067                 } else
1068                         mode_info->bios_connector[4].ddc_i2c.valid = false;
1069         }
1070
1071         /* check TV table */
1072         if (dev_priv->chip_family != CHIP_R100 &&
1073             dev_priv->chip_family != CHIP_R200) {
1074                 uint32_t tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1075                 if (tv_info) {
1076                         if (radeon_bios8(dev_priv, tv_info + 6) == 'T') {
1077                                 mode_info->bios_connector[5].valid = true;
1078                                 mode_info->bios_connector[5].connector_type = CONNECTOR_DIN;
1079                                 mode_info->bios_connector[5].dac_type = DAC_TVDAC;
1080                                 mode_info->bios_connector[5].tmds_type = TMDS_NONE;
1081                                 mode_info->bios_connector[5].ddc_i2c.valid = false;
1082                         }
1083                 }
1084         }
1085
1086
1087         DRM_DEBUG("BIOS Connector table\n");
1088         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
1089                 if (!mode_info->bios_connector[i].valid)
1090                         continue;
1091
1092                 DRM_DEBUG("Port %d: ddc_type 0x%x, dac_type %d, tmds_type %d, connector type %d, hpd_mask %d\n",
1093                           i, mode_info->bios_connector[i].ddc_i2c.mask_clk_reg,
1094                           mode_info->bios_connector[i].dac_type,
1095                           mode_info->bios_connector[i].tmds_type,
1096                           mode_info->bios_connector[i].connector_type,
1097                           mode_info->bios_connector[i].hpd_mask);
1098         }
1099
1100         return true;
1101 }
1102
1103 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
1104 {
1105         struct drm_radeon_private *dev_priv = dev->dev_private;
1106
1107         if (offset) {
1108                 while (radeon_bios16(dev_priv, offset)) {
1109                         uint16_t cmd  = ((radeon_bios16(dev_priv, offset) & 0xe000) >> 13);
1110                         uint32_t addr = (radeon_bios16(dev_priv, offset) & 0x1fff);
1111                         uint32_t val, and_mask, or_mask;
1112                         uint32_t tmp;
1113
1114                         offset += 2;
1115                         switch (cmd) {
1116                         case 0:
1117                                 val = radeon_bios32(dev_priv, offset);
1118                                 offset += 4;
1119                                 RADEON_WRITE(addr, val);
1120                                 break;
1121                         case 1:
1122                                 val = radeon_bios32(dev_priv, offset);
1123                                 offset += 4;
1124                                 RADEON_WRITE(addr, val);
1125                                 break;
1126                         case 2:
1127                                 and_mask = radeon_bios32(dev_priv, offset);
1128                                 offset += 4;
1129                                 or_mask = radeon_bios32(dev_priv, offset);
1130                                 offset += 4;
1131                                 tmp = RADEON_READ(addr);
1132                                 tmp &= and_mask;
1133                                 tmp |= or_mask;
1134                                 RADEON_WRITE(addr, tmp);
1135                                 break;
1136                         case 3:
1137                                 and_mask = radeon_bios32(dev_priv, offset);
1138                                 offset += 4;
1139                                 or_mask = radeon_bios32(dev_priv, offset);
1140                                 offset += 4;
1141                                 tmp = RADEON_READ(addr);
1142                                 tmp &= and_mask;
1143                                 tmp |= or_mask;
1144                                 RADEON_WRITE(addr, tmp);
1145                                 break;
1146                         case 4:
1147                                 val = radeon_bios16(dev_priv, offset);
1148                                 offset += 2;
1149                                 udelay(val);
1150                                 break;
1151                         case 5:
1152                                 val = radeon_bios16(dev_priv, offset);
1153                                 offset += 2;
1154                                 switch (addr) {
1155                                 case 8:
1156                                         while (val--) {
1157                                                 if (!(RADEON_READ_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL) &
1158                                                       RADEON_MC_BUSY))
1159                                                         break;
1160                                         }
1161                                         break;
1162                                 case 9:
1163                                         while (val--) {
1164                                                 if ((RADEON_READ(RADEON_MC_STATUS) &
1165                                                       RADEON_MC_IDLE))
1166                                                         break;
1167                                         }
1168                                         break;
1169                                 default:
1170                                         break;
1171                                 }
1172                                 break;
1173                         default:
1174                                 break;
1175                         }
1176                 }
1177         }
1178 }
1179
1180 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
1181 {
1182         struct drm_radeon_private *dev_priv = dev->dev_private;
1183
1184         if (offset) {
1185                 while (radeon_bios8(dev_priv, offset)) {
1186                         uint8_t cmd  = ((radeon_bios8(dev_priv, offset) & 0xc0) >> 6);
1187                         uint8_t addr = (radeon_bios8(dev_priv, offset) & 0x3f);
1188                         uint32_t val, shift, tmp;
1189                         uint32_t and_mask, or_mask;
1190
1191                         offset++;
1192                         switch (cmd) {
1193                         case 0:
1194                                 val = radeon_bios32(dev_priv, offset);
1195                                 offset += 4;
1196                                 RADEON_WRITE_PLL(dev_priv, addr, val);
1197                                 break;
1198                         case 1:
1199                                 shift = radeon_bios8(dev_priv, offset) * 8;
1200                                 offset++;
1201                                 and_mask = radeon_bios8(dev_priv, offset) << shift;
1202                                 and_mask |= ~(0xff << shift);
1203                                 offset++;
1204                                 or_mask = radeon_bios8(dev_priv, offset) << shift;
1205                                 offset++;
1206                                 tmp = RADEON_READ_PLL(dev_priv, addr);
1207                                 tmp &= and_mask;
1208                                 tmp |= or_mask;
1209                                 RADEON_WRITE_PLL(dev_priv, addr, tmp);
1210                                 break;
1211                         case 2:
1212                         case 3:
1213                                 tmp = 1000;
1214                                 switch (addr) {
1215                                 case 1:
1216                                         udelay(150);
1217                                         break;
1218                                 case 2:
1219                                         udelay(1000);
1220                                         break;
1221                                 case 3:
1222                                         while (tmp--) {
1223                                                 if (!(RADEON_READ_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL) &
1224                                                       RADEON_MC_BUSY))
1225                                                         break;
1226                                         }
1227                                         break;
1228                                 case 4:
1229                                         while (tmp--) {
1230                                                 if (RADEON_READ_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL) &
1231                                                     RADEON_DLL_READY)
1232                                                         break;
1233                                         }
1234                                         break;
1235                                 case 5:
1236                                         tmp = RADEON_READ_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL);
1237                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
1238 #if 0
1239                                                 uint32_t mclk_cntl = RADEON_READ_PLL(RADEON_MCLK_CNTL);
1240                                                 mclk_cntl &= 0xffff0000;
1241                                                 //mclk_cntl |= 0x00001111; /* ??? */
1242                                                 RADEON_WRITE_PLL(dev_priv, RADEON_MCLK_CNTL, mclk_cntl);
1243                                                 udelay(10000);
1244 #endif
1245                                                 RADEON_WRITE_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL,
1246                                                                  tmp & ~RADEON_CG_NO1_DEBUG_0);
1247                                                 udelay(10000);
1248                                         }
1249                                         break;
1250                                 default:
1251                                         break;
1252                                 }
1253                                 break;
1254                         default:
1255                                 break;
1256                         }
1257                 }
1258         }
1259 }
1260
1261 static void combios_parse_ram_reset_table(struct drm_device *dev, uint16_t offset)
1262 {
1263         struct drm_radeon_private *dev_priv = dev->dev_private;
1264         uint32_t tmp;
1265
1266         if (offset) {
1267                 uint8_t val = radeon_bios8(dev_priv, offset);
1268                 while (val != 0xff) {
1269                         offset++;
1270
1271                         if (val == 0x0f) {
1272                                 uint32_t channel_complete_mask;
1273
1274                                 if (radeon_is_r300(dev_priv))
1275                                         channel_complete_mask = R300_MEM_PWRUP_COMPLETE;
1276                                 else
1277                                         channel_complete_mask = RADEON_MEM_PWRUP_COMPLETE;
1278                                 tmp = 20000;
1279                                 while (tmp--) {
1280                                         if ((RADEON_READ(RADEON_MEM_STR_CNTL) &
1281                                              channel_complete_mask) ==
1282                                             channel_complete_mask)
1283                                                 break;
1284                                 }
1285                         } else {
1286                                 uint32_t or_mask = radeon_bios16(dev_priv, offset);
1287                                 offset += 2;
1288
1289                                 tmp = RADEON_READ(RADEON_MEM_SDRAM_MODE_REG);
1290                                 tmp &= RADEON_SDRAM_MODE_MASK;
1291                                 tmp |= or_mask;
1292                                 RADEON_WRITE(RADEON_MEM_SDRAM_MODE_REG, tmp);
1293
1294                                 or_mask = val << 24;
1295                                 tmp = RADEON_READ(RADEON_MEM_SDRAM_MODE_REG);
1296                                 tmp &= RADEON_B3MEM_RESET_MASK;
1297                                 tmp |= or_mask;
1298                                 RADEON_WRITE(RADEON_MEM_SDRAM_MODE_REG, tmp);
1299                         }
1300                         val = radeon_bios8(dev_priv, offset);
1301                 }
1302         }
1303 }
1304
1305 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
1306 {
1307         uint16_t dyn_clk_info = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
1308
1309         if (dyn_clk_info)
1310                 combios_parse_pll_table(dev, dyn_clk_info);
1311 }
1312
1313 void radeon_combios_asic_init(struct drm_device *dev)
1314 {
1315         uint16_t table;
1316
1317         /* ASIC INIT 1 */
1318         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
1319         if (table)
1320                 combios_parse_mmio_table(dev, table);
1321
1322         /* PLL INIT */
1323         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
1324         if (table)
1325                 combios_parse_pll_table(dev, table);
1326
1327         /* ASIC INIT 2 */
1328         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
1329         if (table)
1330                 combios_parse_mmio_table(dev, table);
1331
1332         /* ASIC INIT 4 */
1333         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
1334         if (table)
1335                 combios_parse_mmio_table(dev, table);
1336
1337         /* RAM RESET */
1338         table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
1339         if (table)
1340                 combios_parse_ram_reset_table(dev, table);
1341
1342         /* ASIC INIT 3 */
1343         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
1344         if (table)
1345                 combios_parse_mmio_table(dev, table);
1346
1347         /* DYN CLK 1 */
1348         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
1349         if (table)
1350                 combios_parse_pll_table(dev, table);
1351
1352         /* ASIC INIT 5 */
1353         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_5_TABLE);
1354         if (table)
1355                 combios_parse_mmio_table(dev, table);
1356
1357 }
1358
1359 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
1360 {
1361         struct drm_radeon_private *dev_priv = dev->dev_private;
1362         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
1363
1364         bios_0_scratch = RADEON_READ(RADEON_BIOS_0_SCRATCH);
1365         bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
1366         //bios_7_scratch = RADEON_READ(RADEON_BIOS_7_SCRATCH);
1367
1368         /* let the bios control the backlight */
1369         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
1370
1371         /* tell the bios not to handle mode switching */
1372         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
1373                                  RADEON_ACC_MODE_CHANGE);
1374
1375         /* tell the bios a driver is loaded */
1376         //bios_7_scratch |= RADEON_DRV_LOADED;
1377
1378         RADEON_WRITE(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1379         RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1380         //RADEON_WRITE(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
1381 }
1382
1383 void
1384 radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
1385 {
1386         struct drm_device *dev = encoder->dev;
1387         struct drm_radeon_private *dev_priv = dev->dev_private;
1388         uint32_t bios_6_scratch;
1389
1390         bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
1391
1392         if (lock)
1393                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
1394         else
1395                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
1396
1397         RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1398 }