linux-core/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon_drv.h"
  30
  31 /* old legacy ATI BIOS routines */
  32
  33 /* COMBIOS table offsets */
  34 enum radeon_combios_table_offset
  35 {
  36         /* absolute offset tables */
  37         COMBIOS_ASIC_INIT_1_TABLE,
  38         COMBIOS_BIOS_SUPPORT_TABLE,
  39         COMBIOS_DAC_PROGRAMMING_TABLE,
  40         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  41         COMBIOS_CRTC_INFO_TABLE,
  42         COMBIOS_PLL_INFO_TABLE,
  43         COMBIOS_TV_INFO_TABLE,
  44         COMBIOS_DFP_INFO_TABLE,
  45         COMBIOS_HW_CONFIG_INFO_TABLE,
  46         COMBIOS_MULTIMEDIA_INFO_TABLE,
  47         COMBIOS_TV_STD_PATCH_TABLE,
  48         COMBIOS_LCD_INFO_TABLE,
  49         COMBIOS_MOBILE_INFO_TABLE,
  50         COMBIOS_PLL_INIT_TABLE,
  51         COMBIOS_MEM_CONFIG_TABLE,
  52         COMBIOS_SAVE_MASK_TABLE,
  53         COMBIOS_HARDCODED_EDID_TABLE,
  54         COMBIOS_ASIC_INIT_2_TABLE,
  55         COMBIOS_CONNECTOR_INFO_TABLE,
  56         COMBIOS_DYN_CLK_1_TABLE,
  57         COMBIOS_RESERVED_MEM_TABLE,
  58         COMBIOS_EXT_TDMS_INFO_TABLE,
  59         COMBIOS_MEM_CLK_INFO_TABLE,
  60         COMBIOS_EXT_DAC_INFO_TABLE,
  61         COMBIOS_MISC_INFO_TABLE,
  62         COMBIOS_CRT_INFO_TABLE,
  63         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  64         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  65         COMBIOS_FAN_SPEED_INFO_TABLE,
  66         COMBIOS_OVERDRIVE_INFO_TABLE,
  67         COMBIOS_OEM_INFO_TABLE,
  68         COMBIOS_DYN_CLK_2_TABLE,
  69         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  70         COMBIOS_I2C_INFO_TABLE,
  71         /* relative offset tables */
  72         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
  73         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
  74         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
  75         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
  76         COMBIOS_POWERPLAY_TABLE,        /* offset from mobile info */
  77         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
  78         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
  79         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
  80         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
  81         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
  82 };
  83
  84 enum radeon_combios_ddc
  85 {
  86     DDC_NONE_DETECTED,
  87     DDC_MONID,
  88     DDC_DVI,
  89     DDC_VGA,
  90     DDC_CRT2,
  91     DDC_LCD,
  92     DDC_GPIO,
  93 };
  94
  95 enum radeon_combios_connector
  96 {
  97     CONNECTOR_NONE_LEGACY,
  98     CONNECTOR_PROPRIETARY_LEGACY,
  99     CONNECTOR_CRT_LEGACY,
 100     CONNECTOR_DVI_I_LEGACY,
 101     CONNECTOR_DVI_D_LEGACY,
 102     CONNECTOR_CTV_LEGACY,
 103     CONNECTOR_STV_LEGACY,
 104     CONNECTOR_UNSUPPORTED_LEGACY
 105 };
 106
 107 static uint16_t combios_get_table_offset(struct drm_device *dev, enum radeon_combios_table_offset table)
 108 {
 109         struct drm_radeon_private *dev_priv = dev->dev_private;
 110         int rev;
 111         uint16_t offset = 0, check_offset;
 112
 113         switch (table) {
 114         /* absolute offset tables */
 115         case COMBIOS_ASIC_INIT_1_TABLE:
 116                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0xc);
 117                 if (check_offset)
 118                         offset = check_offset;
 119                 break;
 120         case COMBIOS_BIOS_SUPPORT_TABLE:
 121                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x14);
 122                 if (check_offset)
 123                         offset = check_offset;
 124                 break;
 125         case COMBIOS_DAC_PROGRAMMING_TABLE:
 126                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x2a);
 127                 if (check_offset)
 128                         offset = check_offset;
 129                 break;
 130         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 131                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x2c);
 132                 if (check_offset)
 133                         offset = check_offset;
 134                 break;
 135         case COMBIOS_CRTC_INFO_TABLE:
 136                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x2e);
 137                 if (check_offset)
 138                         offset = check_offset;
 139                 break;
 140         case COMBIOS_PLL_INFO_TABLE:
 141                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x30);
 142                 if (check_offset)
 143                         offset = check_offset;
 144                 break;
 145         case COMBIOS_TV_INFO_TABLE:
 146                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x32);
 147                 if (check_offset)
 148                         offset = check_offset;
 149                 break;
 150         case COMBIOS_DFP_INFO_TABLE:
 151                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x34);
 152                 if (check_offset)
 153                         offset = check_offset;
 154                 break;
 155         case COMBIOS_HW_CONFIG_INFO_TABLE:
 156                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x36);
 157                 if (check_offset)
 158                         offset = check_offset;
 159                 break;
 160         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 161                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x38);
 162                 if (check_offset)
 163                         offset = check_offset;
 164                 break;
 165         case COMBIOS_TV_STD_PATCH_TABLE:
 166                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x3e);
 167                 if (check_offset)
 168                         offset = check_offset;
 169                 break;
 170         case COMBIOS_LCD_INFO_TABLE:
 171                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x40);
 172                 if (check_offset)
 173                         offset = check_offset;
 174                 break;
 175         case COMBIOS_MOBILE_INFO_TABLE:
 176                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x42);
 177                 if (check_offset)
 178                         offset = check_offset;
 179                 break;
 180         case COMBIOS_PLL_INIT_TABLE:
 181                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x46);
 182                 if (check_offset)
 183                         offset = check_offset;
 184                 break;
 185         case COMBIOS_MEM_CONFIG_TABLE:
 186                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x48);
 187                 if (check_offset)
 188                         offset = check_offset;
 189                 break;
 190         case COMBIOS_SAVE_MASK_TABLE:
 191                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x4a);
 192                 if (check_offset)
 193                         offset = check_offset;
 194                 break;
 195         case COMBIOS_HARDCODED_EDID_TABLE:
 196                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x4c);
 197                 if (check_offset)
 198                         offset = check_offset;
 199                 break;
 200         case COMBIOS_ASIC_INIT_2_TABLE:
 201                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x4e);
 202                 if (check_offset)
 203                         offset = check_offset;
 204                 break;
 205         case COMBIOS_CONNECTOR_INFO_TABLE:
 206                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x50);
 207                 if (check_offset)
 208                         offset = check_offset;
 209                 break;
 210         case COMBIOS_DYN_CLK_1_TABLE:
 211                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x52);
 212                 if (check_offset)
 213                         offset = check_offset;
 214                 break;
 215         case COMBIOS_RESERVED_MEM_TABLE:
 216                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x54);
 217                 if (check_offset)
 218                         offset = check_offset;
 219                 break;
 220         case COMBIOS_EXT_TDMS_INFO_TABLE:
 221                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x58);
 222                 if (check_offset)
 223                         offset = check_offset;
 224                 break;
 225         case COMBIOS_MEM_CLK_INFO_TABLE:
 226                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x5a);
 227                 if (check_offset)
 228                         offset = check_offset;
 229                 break;
 230         case COMBIOS_EXT_DAC_INFO_TABLE:
 231                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x5c);
 232                 if (check_offset)
 233                         offset = check_offset;
 234                 break;
 235         case COMBIOS_MISC_INFO_TABLE:
 236                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x5e);
 237                 if (check_offset)
 238                         offset = check_offset;
 239                 break;
 240         case COMBIOS_CRT_INFO_TABLE:
 241                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x60);
 242                 if (check_offset)
 243                         offset = check_offset;
 244                 break;
 245         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 246                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x62);
 247                 if (check_offset)
 248                         offset = check_offset;
 249                 break;
 250         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 251                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x64);
 252                 if (check_offset)
 253                         offset = check_offset;
 254                 break;
 255         case COMBIOS_FAN_SPEED_INFO_TABLE:
 256                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x66);
 257                 if (check_offset)
 258                         offset = check_offset;
 259                 break;
 260         case COMBIOS_OVERDRIVE_INFO_TABLE:
 261                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x68);
 262                 if (check_offset)
 263                         offset = check_offset;
 264                 break;
 265         case COMBIOS_OEM_INFO_TABLE:
 266                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x6a);
 267                 if (check_offset)
 268                         offset = check_offset;
 269                 break;
 270         case COMBIOS_DYN_CLK_2_TABLE:
 271                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x6c);
 272                 if (check_offset)
 273                         offset = check_offset;
 274                 break;
 275         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 276                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x6e);
 277                 if (check_offset)
 278                         offset = check_offset;
 279                 break;
 280         case COMBIOS_I2C_INFO_TABLE:
 281                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x70);
 282                 if (check_offset)
 283                         offset = check_offset;
 284                 break;
 285         /* relative offset tables */
 286         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 287                 check_offset = combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 288                 if (check_offset) {
 289                         rev = radeon_bios8(dev_priv, check_offset);
 290                         if (rev > 0) {
 291                                 check_offset = radeon_bios16(dev_priv, check_offset + 0x3);
 292                                 if (check_offset)
 293                                         offset = check_offset;
 294                         }
 295                 }
 296                 break;
 297         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 298                 check_offset = combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 299                 if (check_offset) {
 300                         rev = radeon_bios8(dev_priv, check_offset);
 301                         if (rev > 0) {
 302                                 check_offset = radeon_bios16(dev_priv, check_offset + 0x5);
 303                                 if (check_offset)
 304                                         offset = check_offset;
 305                         }
 306                 }
 307                 break;
 308         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 309                 check_offset = combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 310                 if (check_offset) {
 311                         rev = radeon_bios8(dev_priv, check_offset);
 312                         if (rev == 2) {
 313                                 check_offset = radeon_bios16(dev_priv, check_offset + 0x9);
 314                                 if (check_offset)
 315                                         offset = check_offset;
 316                         }
 317                 }
 318                 break;
 319         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 320                 check_offset = combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 321                 if (check_offset) {
 322                         while (radeon_bios8(dev_priv, check_offset++));
 323                         check_offset += 2;
 324                         if (check_offset)
 325                                 offset = check_offset;
 326                 }
 327                 break;
 328         case COMBIOS_POWERPLAY_TABLE:   /* offset from mobile info */
 329                 check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 330                 if (check_offset) {
 331                         check_offset = radeon_bios16(dev_priv, check_offset + 0x11);
 332                         if (check_offset)
 333                                 offset = check_offset;
 334                 }
 335                 break;
 336         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 337                 check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 338                 if (check_offset) {
 339                         check_offset = radeon_bios16(dev_priv, check_offset + 0x13);
 340                         if (check_offset)
 341                                 offset = check_offset;
 342                 }
 343                 break;
 344         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 345                 check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 346                 if (check_offset) {
 347                         check_offset = radeon_bios16(dev_priv, check_offset + 0x15);
 348                         if (check_offset)
 349                                 offset = check_offset;
 350                 }
 351                 break;
 352         case COMBIOS_TMDS_POWER_TABLE:          /* offset from mobile info */
 353                 check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 354                 if (check_offset) {
 355                         check_offset = radeon_bios16(dev_priv, check_offset + 0x17);
 356                         if (check_offset)
 357                                 offset = check_offset;
 358                 }
 359                 break;
 360         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 361                 check_offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 362                 if (check_offset) {
 363                         check_offset = radeon_bios16(dev_priv, check_offset + 0x2);
 364                         if (check_offset)
 365                                 offset = check_offset;
 366                 }
 367                 break;
 368         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 369                 check_offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 370                 if (check_offset) {
 371                         check_offset = radeon_bios16(dev_priv, check_offset + 0x4);
 372                         if (check_offset)
 373                                 offset = check_offset;
 374                 }
 375                 break;
 376         default:
 377                 break;
 378         }
 379
 380         return offset;
 381
 382 }
 383
 384 struct radeon_i2c_bus_rec combios_setup_i2c_bus(int ddc_line)
 385 {
 386         struct radeon_i2c_bus_rec i2c;
 387
 388         i2c.mask_clk_mask = RADEON_GPIO_EN_1;
 389         i2c.mask_data_mask = RADEON_GPIO_EN_0;
 390         i2c.a_clk_mask = RADEON_GPIO_A_1;
 391         i2c.a_data_mask = RADEON_GPIO_A_0;
 392         i2c.put_clk_mask = RADEON_GPIO_EN_1;
 393         i2c.put_data_mask = RADEON_GPIO_EN_0;
 394         i2c.get_clk_mask = RADEON_GPIO_Y_1;
 395         i2c.get_data_mask = RADEON_GPIO_Y_0;
 396         if ((ddc_line == RADEON_LCD_GPIO_MASK) ||
 397             (ddc_line == RADEON_MDGPIO_EN_REG)) {
 398                 i2c.mask_clk_reg = ddc_line;
 399                 i2c.mask_data_reg = ddc_line;
 400                 i2c.a_clk_reg = ddc_line;
 401                 i2c.a_data_reg = ddc_line;
 402                 i2c.put_clk_reg = ddc_line;
 403                 i2c.put_data_reg = ddc_line;
 404                 i2c.get_clk_reg = ddc_line + 4;
 405                 i2c.get_data_reg = ddc_line + 4;
 406         } else {
 407                 i2c.mask_clk_reg = ddc_line;
 408                 i2c.mask_data_reg = ddc_line;
 409                 i2c.a_clk_reg = ddc_line;
 410                 i2c.a_data_reg = ddc_line;
 411                 i2c.put_clk_reg = ddc_line;
 412                 i2c.put_data_reg = ddc_line;
 413                 i2c.get_clk_reg = ddc_line;
 414                 i2c.get_data_reg = ddc_line;
 415         }
 416
 417         if (ddc_line)
 418                 i2c.valid = true;
 419         else
 420                 i2c.valid = false;
 421
 422         return i2c;
 423 }
 424
 425 bool radeon_combios_get_clock_info(struct drm_device *dev)
 426 {
 427         struct drm_radeon_private *dev_priv = dev->dev_private;
 428         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 429         uint16_t pll_info;
 430         struct radeon_pll *pll = &mode_info->pll;
 431         int8_t rev;
 432
 433         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 434         if (pll_info) {
 435                 rev = radeon_bios8(dev_priv, pll_info);
 436
 437                 pll->reference_freq = radeon_bios16(dev_priv, pll_info + 0xe);
 438                 pll->reference_div = radeon_bios16(dev_priv, pll_info + 0x10);
 439                 pll->pll_out_min = radeon_bios32(dev_priv, pll_info + 0x12);
 440                 pll->pll_out_max = radeon_bios32(dev_priv, pll_info + 0x16);
 441
 442                 if (rev > 9) {
 443                         pll->pll_in_min = radeon_bios32(dev_priv, pll_info + 0x36);
 444                         pll->pll_in_max = radeon_bios32(dev_priv, pll_info + 0x3a);
 445                 } else {
 446                         pll->pll_in_min = 40;
 447                         pll->pll_in_max = 500;
 448                 }
 449
 450                 pll->xclk = radeon_bios16(dev_priv, pll_info + 0x08);
 451
 452                 // sclk/mclk use fixed point
 453                 //sclk = radeon_bios16(pll_info + 8) / 100.0;
 454                 //mclk = radeon_bios16(pll_info + 10) / 100.0;
 455                 //if (sclk == 0) sclk = 200;
 456                 //if (mclk == 0) mclk = 200;
 457
 458                 return true;
 459         }
 460         return false;
 461 }
 462
 463 bool radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder)
 464 {
 465         struct drm_device *dev = encoder->base.dev;
 466         struct drm_radeon_private *dev_priv = dev->dev_private;
 467         uint16_t dac_info;
 468         uint8_t rev, bg, dac;
 469
 470         /* first check TV table */
 471         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 472         if (dac_info) {
 473                 rev = radeon_bios8(dev_priv, dac_info + 0x3);
 474                 if (rev > 4) {
 475                         bg = radeon_bios8(dev_priv, dac_info + 0xc) & 0xf;
 476                         dac = radeon_bios8(dev_priv, dac_info + 0xd) & 0xf;
 477                         encoder->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 478
 479                         bg = radeon_bios8(dev_priv, dac_info + 0xe) & 0xf;
 480                         dac = radeon_bios8(dev_priv, dac_info + 0xf) & 0xf;
 481                         encoder->pal_tvdac_adj = (bg << 16) | (dac << 20);
 482
 483                         bg = radeon_bios8(dev_priv, dac_info + 0x10) & 0xf;
 484                         dac = radeon_bios8(dev_priv, dac_info + 0x11) & 0xf;
 485                         encoder->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 486
 487                         return true;
 488                 } else if (rev > 1) {
 489                         bg = radeon_bios8(dev_priv, dac_info + 0xc) & 0xf;
 490                         dac = (radeon_bios8(dev_priv, dac_info + 0xc) >> 4) & 0xf;
 491                         encoder->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 492
 493                         bg = radeon_bios8(dev_priv, dac_info + 0xd) & 0xf;
 494                         dac = (radeon_bios8(dev_priv, dac_info + 0xd) >> 4) & 0xf;
 495                         encoder->pal_tvdac_adj = (bg << 16) | (dac << 20);
 496
 497                         bg = radeon_bios8(dev_priv, dac_info + 0xe) & 0xf;
 498                         dac = (radeon_bios8(dev_priv, dac_info + 0xe) >> 4) & 0xf;
 499                         encoder->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 500
 501                         return true;
 502                 }
 503         }
 504
 505         /* then check CRT table */
 506         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 507         if (dac_info) {
 508                 rev = radeon_bios8(dev_priv, dac_info) & 0x3;
 509                 if (rev < 2) {
 510                         bg = radeon_bios8(dev_priv, dac_info + 0x3) & 0xf;
 511                         dac = (radeon_bios8(dev_priv, dac_info + 0x3) >> 4) & 0xf;
 512                         encoder->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 513                         encoder->pal_tvdac_adj = encoder->ps2_tvdac_adj;
 514                         encoder->ntsc_tvdac_adj = encoder->ps2_tvdac_adj;
 515
 516                         return true;
 517                 } else {
 518                         bg = radeon_bios8(dev_priv, dac_info + 0x4) & 0xf;
 519                         dac = radeon_bios8(dev_priv, dac_info + 0x5) & 0xf;
 520                         encoder->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 521                         encoder->pal_tvdac_adj = encoder->ps2_tvdac_adj;
 522                         encoder->ntsc_tvdac_adj = encoder->ps2_tvdac_adj;
 523
 524                         return true;
 525                 }
 526
 527         }
 528
 529         return false;
 530 }
 531
 532 bool radeon_combios_get_tv_info(struct radeon_encoder *encoder)
 533 {
 534         struct drm_device *dev = encoder->base.dev;
 535         struct drm_radeon_private *dev_priv = dev->dev_private;
 536         uint16_t tv_info;
 537
 538         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 539         if (tv_info) {
 540                 if (radeon_bios8(dev_priv, tv_info + 6) == 'T') {
 541                         switch (radeon_bios8(dev_priv, tv_info + 7) & 0xf) {
 542                         case 1:
 543                                 encoder->tv_std = TV_STD_NTSC;
 544                                 DRM_INFO("Default TV standard: NTSC\n");
 545                                 break;
 546                         case 2:
 547                                 encoder->tv_std = TV_STD_PAL;
 548                                 DRM_INFO("Default TV standard: PAL\n");
 549                                 break;
 550                         case 3:
 551                                 encoder->tv_std = TV_STD_PAL_M;
 552                                 DRM_INFO("Default TV standard: PAL-M\n");
 553                                 break;
 554                         case 4:
 555                                 encoder->tv_std = TV_STD_PAL_60;
 556                                 DRM_INFO("Default TV standard: PAL-60\n");
 557                                 break;
 558                         case 5:
 559                                 encoder->tv_std = TV_STD_NTSC_J;
 560                                 DRM_INFO("Default TV standard: NTSC-J\n");
 561                                 break;
 562                         case 6:
 563                                 encoder->tv_std = TV_STD_SCART_PAL;
 564                                 DRM_INFO("Default TV standard: SCART-PAL\n");
 565                                 break;
 566                         default:
 567                                 encoder->tv_std = TV_STD_NTSC;
 568                                 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
 569                                 break;
 570                         }
 571
 572                         switch ((radeon_bios8(dev_priv, tv_info + 9) >> 2) & 0x3) {
 573                         case 0:
 574                                 DRM_INFO("29.498928713 MHz TV ref clk\n");
 575                                 break;
 576                         case 1:
 577                                 DRM_INFO("28.636360000 MHz TV ref clk\n");
 578                                 break;
 579                         case 2:
 580                                 DRM_INFO("14.318180000 MHz TV ref clk\n");
 581                                 break;
 582                         case 3:
 583                                 DRM_INFO("27.000000000 MHz TV ref clk\n");
 584                                 break;
 585                         default:
 586                                 break;
 587                         }
 588                         return true;
 589                 }
 590         }
 591         return false;
 592 }
 593
 594 bool radeon_combios_get_lvds_info(struct radeon_encoder *encoder)
 595 {
 596         struct drm_device *dev = encoder->base.dev;
 597         struct drm_radeon_private *dev_priv = dev->dev_private;
 598         uint16_t lcd_info;
 599         uint32_t panel_setup;
 600         char stmp[30];
 601         int tmp, i;
 602
 603         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
 604
 605         if (lcd_info) {
 606                 for (i = 0; i < 24; i++)
 607                         stmp[i] = radeon_bios8(dev_priv, lcd_info + i + 1);
 608                 stmp[24] = 0;
 609
 610                 DRM_INFO("Panel ID String: %s\n", stmp);
 611
 612                 encoder->panel_xres = radeon_bios16(dev_priv, lcd_info + 25);
 613                 encoder->panel_yres = radeon_bios16(dev_priv, lcd_info + 27);
 614
 615                 DRM_INFO("Panel Size %dx%d\n", encoder->panel_xres, encoder->panel_yres);
 616
 617                 encoder->panel_vcc_delay = radeon_bios16(dev_priv, lcd_info + 44);
 618                 if (encoder->panel_vcc_delay > 2000 || encoder->panel_vcc_delay < 0)
 619                         encoder->panel_vcc_delay = 2000;
 620
 621                 encoder->panel_pwr_delay = radeon_bios16(dev_priv, lcd_info + 0x24);
 622                 encoder->panel_digon_delay = radeon_bios16(dev_priv, lcd_info + 0x38) & 0xf;
 623                 encoder->panel_blon_delay = (radeon_bios16(dev_priv, lcd_info + 0x38) >> 4) & 0xf;
 624
 625                 encoder->panel_ref_divider = radeon_bios16(dev_priv, lcd_info + 46);
 626                 encoder->panel_post_divider = radeon_bios8(dev_priv, lcd_info + 48);
 627                 encoder->panel_fb_divider = radeon_bios16(dev_priv, lcd_info + 49);
 628                 if ((encoder->panel_ref_divider != 0) &&
 629                     (encoder->panel_fb_divider > 3))
 630                         encoder->use_bios_dividers = true;
 631
 632                 panel_setup = radeon_bios32(dev_priv, lcd_info + 0x39);
 633                 encoder->lvds_gen_cntl = 0;
 634                 if (panel_setup & 0x1)
 635                         encoder->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
 636
 637                 if ((panel_setup >> 4) & 0x1)
 638                         encoder->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
 639
 640                 switch ((panel_setup >> 8) & 0x8) {
 641                 case 0:
 642                         encoder->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
 643                         break;
 644                 case 1:
 645                         encoder->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
 646                         break;
 647                 case 2:
 648                         encoder->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
 649                         break;
 650                 default:
 651                         break;
 652                 }
 653
 654                 if ((panel_setup >> 16) & 0x1)
 655                         encoder->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
 656
 657                 if ((panel_setup >> 17) & 0x1)
 658                         encoder->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
 659
 660                 if ((panel_setup >> 18) & 0x1)
 661                         encoder->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
 662
 663                 if ((panel_setup >> 23) & 0x1)
 664                         encoder->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
 665
 666                 encoder->lvds_gen_cntl |= (panel_setup & 0xf0000000);
 667
 668
 669                 for (i = 0; i < 32; i++) {
 670                         tmp = radeon_bios16(dev_priv, lcd_info + 64 + i * 2);
 671                         if (tmp == 0) break;
 672
 673                         if ((radeon_bios16(dev_priv, tmp) == encoder->panel_xres) &&
 674                             (radeon_bios16(dev_priv, tmp + 2) == encoder->panel_yres)) {
 675                                 encoder->hblank = (radeon_bios16(dev_priv, tmp + 17) -
 676                                                    radeon_bios16(dev_priv, tmp + 19)) * 8;
 677                                 encoder->hoverplus = (radeon_bios16(dev_priv, tmp + 21) -
 678                                                       radeon_bios16(dev_priv, tmp + 19) - 1) * 8;
 679                                 encoder->hsync_width = radeon_bios8(dev_priv, tmp + 23) * 8;
 680
 681                                 encoder->vblank = (radeon_bios16(dev_priv, tmp + 24) -
 682                                                    radeon_bios16(dev_priv, tmp + 26));
 683                                 encoder->voverplus = ((radeon_bios16(dev_priv, tmp + 28) & 0x7fff) -
 684                                                       radeon_bios16(dev_priv, tmp + 26));
 685                                 encoder->vsync_width = ((radeon_bios16(dev_priv, tmp + 28) & 0xf800) >> 11);
 686                                 encoder->dotclock = radeon_bios16(dev_priv, tmp + 9) * 10;
 687                                 encoder->flags = 0;
 688                         }
 689                 }
 690                 return true;
 691         }
 692         DRM_INFO("No panel info found in BIOS\n");
 693         return false;
 694
 695 }
 696
 697 bool radeon_combios_get_tmds_info(struct radeon_encoder *encoder)
 698 {
 699         struct drm_device *dev = encoder->base.dev;
 700         struct drm_radeon_private *dev_priv = dev->dev_private;
 701         uint16_t tmds_info;
 702         int i, n;
 703         uint8_t ver;
 704
 705         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
 706
 707         if (tmds_info) {
 708                 ver = radeon_bios8(dev_priv, tmds_info);
 709                 DRM_INFO("DFP table revision: %d\n", ver);
 710                 if (ver == 3) {
 711                         n = radeon_bios8(dev_priv, tmds_info + 5) + 1;
 712                         if (n > 4)
 713                                 n = 4;
 714                         for (i = 0; i < n; i++) {
 715                                 encoder->tmds_pll[i].value = radeon_bios32(dev_priv, tmds_info + i * 10 + 0x08);
 716                                 encoder->tmds_pll[i].freq = radeon_bios16(dev_priv, tmds_info + i * 10 + 0x10);
 717                         }
 718                         return true;
 719                 } else if (ver == 4) {
 720                         int stride = 0;
 721                         n = radeon_bios8(dev_priv, tmds_info + 5) + 1;
 722                         if (n > 4)
 723                                 n = 4;
 724                         for (i = 0; i < n; i++) {
 725                                 encoder->tmds_pll[i].value = radeon_bios32(dev_priv, tmds_info + stride + 0x08);
 726                                 encoder->tmds_pll[i].freq = radeon_bios16(dev_priv, tmds_info + stride + 0x10);
 727                                 if (i == 0)
 728                                         stride += 10;
 729                                 else
 730                                         stride += 6;
 731                         }
 732                         return true;
 733                 }
 734         }
 735
 736         DRM_INFO("No TMDS info found in BIOS\n");
 737         return false;
 738 }
 739
 740 static void radeon_apply_legacy_quirks(struct drm_device *dev, int bios_index)
 741 {
 742         struct drm_radeon_private *dev_priv = dev->dev_private;
 743         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 744
 745         /* XPRESS DDC quirks */
 746         if ((dev_priv->chip_family == CHIP_RS400 ||
 747              dev_priv->chip_family == CHIP_RS480) &&
 748             mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) {
 749                 mode_info->bios_connector[bios_index].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
 750         } else if ((dev_priv->chip_family == CHIP_RS400 ||
 751                     dev_priv->chip_family == CHIP_RS480) &&
 752                    mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_reg == RADEON_GPIO_MONID) {
 753                 mode_info->bios_connector[bios_index].ddc_i2c.valid = true;
 754                 mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_mask = (0x20 << 8);
 755                 mode_info->bios_connector[bios_index].ddc_i2c.mask_data_mask = 0x80;
 756                 mode_info->bios_connector[bios_index].ddc_i2c.a_clk_mask = (0x20 << 8);
 757                 mode_info->bios_connector[bios_index].ddc_i2c.a_data_mask = 0x80;
 758                 mode_info->bios_connector[bios_index].ddc_i2c.put_clk_mask = (0x20 << 8);
 759                 mode_info->bios_connector[bios_index].ddc_i2c.put_data_mask = 0x80;
 760                 mode_info->bios_connector[bios_index].ddc_i2c.get_clk_mask = (0x20 << 8);
 761                 mode_info->bios_connector[bios_index].ddc_i2c.get_data_mask = 0x80;
 762                 mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 763                 mode_info->bios_connector[bios_index].ddc_i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 764                 mode_info->bios_connector[bios_index].ddc_i2c.a_clk_reg = RADEON_GPIOPAD_A;
 765                 mode_info->bios_connector[bios_index].ddc_i2c.a_data_reg = RADEON_GPIOPAD_A;
 766                 mode_info->bios_connector[bios_index].ddc_i2c.put_clk_reg = RADEON_GPIOPAD_EN;
 767                 mode_info->bios_connector[bios_index].ddc_i2c.put_data_reg = RADEON_GPIOPAD_EN;
 768                 mode_info->bios_connector[bios_index].ddc_i2c.get_clk_reg = RADEON_LCD_GPIO_Y_REG;
 769                 mode_info->bios_connector[bios_index].ddc_i2c.get_data_reg = RADEON_LCD_GPIO_Y_REG;
 770         }
 771
 772         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
 773            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
 774         if (dev->pdev->device == 0x515e &&
 775             dev->pdev->subsystem_vendor == 0x1014) {
 776                 if (mode_info->bios_connector[bios_index].connector_type == CONNECTOR_VGA &&
 777                     mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) {
 778                         mode_info->bios_connector[bios_index].valid = false;
 779                 }
 780         }
 781
 782         /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
 783         if (dev->pdev->device == 0x5159 &&
 784             dev->pdev->subsystem_vendor == 0x1002 &&
 785             dev->pdev->subsystem_device == 0x013a) {
 786                 if (mode_info->bios_connector[bios_index].connector_type == CONNECTOR_DVI_I)
 787                         mode_info->bios_connector[bios_index].connector_type = CONNECTOR_VGA;
 788
 789         }
 790
 791         /* X300 card with extra non-existent DVI port */
 792         if (dev->pdev->device == 0x5B60 &&
 793             dev->pdev->subsystem_vendor == 0x17af &&
 794             dev->pdev->subsystem_device == 0x201e &&
 795             bios_index == 2) {
 796                 if (mode_info->bios_connector[bios_index].connector_type == CONNECTOR_DVI_I)
 797                         mode_info->bios_connector[bios_index].valid = false;
 798         }
 799
 800 }
 801
 802 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
 803 {
 804         struct drm_radeon_private *dev_priv = dev->dev_private;
 805         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 806         uint32_t conn_info, entry;
 807         uint16_t tmp;
 808         enum radeon_combios_ddc ddc_type;
 809         enum radeon_combios_connector connector_type;
 810         int i;
 811
 812         DRM_DEBUG("\n");
 813         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
 814         if (conn_info) {
 815                 for (i = 0; i < 4; i++) {
 816                         entry = conn_info + 2 + i * 2;
 817
 818                         if (!radeon_bios16(dev_priv, entry))
 819                                     break;
 820
 821                         mode_info->bios_connector[i].valid = true;
 822
 823                         tmp = radeon_bios16(dev_priv, entry);
 824
 825                         connector_type = (tmp >> 12) & 0xf;
 826                         mode_info->bios_connector[i].connector_type = connector_type;
 827
 828                         switch(connector_type) {
 829                         case CONNECTOR_PROPRIETARY_LEGACY:
 830                                 mode_info->bios_connector[i].connector_type = CONNECTOR_DVI_D;
 831                                 break;
 832                         case CONNECTOR_CRT_LEGACY:
 833                                 mode_info->bios_connector[i].connector_type = CONNECTOR_VGA;
 834                                 break;
 835                         case CONNECTOR_DVI_I_LEGACY:
 836                                 mode_info->bios_connector[i].connector_type = CONNECTOR_DVI_I;
 837                                 break;
 838                         case CONNECTOR_DVI_D_LEGACY:
 839                                 mode_info->bios_connector[i].connector_type = CONNECTOR_DVI_D;
 840                                 break;
 841                         case CONNECTOR_CTV_LEGACY:
 842                                 mode_info->bios_connector[i].connector_type = CONNECTOR_CTV;
 843                                 break;
 844                         case CONNECTOR_STV_LEGACY:
 845                                 mode_info->bios_connector[i].connector_type = CONNECTOR_STV;
 846                                 break;
 847                         default:
 848                                 DRM_ERROR("Unknown connector type: %d\n", connector_type);
 849                                 mode_info->bios_connector[i].valid = false;
 850                                 break;
 851                         }
 852
 853                         mode_info->bios_connector[i].ddc_i2c.valid = false;
 854
 855                         ddc_type = (tmp >> 8) & 0xf;
 856                         switch (ddc_type) {
 857                         case DDC_MONID:
 858                                 mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
 859                                 break;
 860                         case DDC_DVI:
 861                                 mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
 862                                 break;
 863                         case DDC_VGA:
 864                                 mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
 865                                 break;
 866                         case DDC_CRT2:
 867                                 mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
 868                                 break;
 869                         default:
 870                                 break;
 871                         }
 872
 873                         if (tmp & 0x1)
 874                                 mode_info->bios_connector[i].dac_type = DAC_TVDAC;
 875                         else
 876                                 mode_info->bios_connector[i].dac_type = DAC_PRIMARY;
 877
 878                         if ((dev_priv->chip_family == CHIP_RS300) ||
 879                             (dev_priv->chip_family == CHIP_RS400) ||
 880                             (dev_priv->chip_family == CHIP_RS480))
 881                                 mode_info->bios_connector[i].dac_type = DAC_TVDAC;
 882
 883                         if ((tmp >> 4) & 0x1)
 884                                 mode_info->bios_connector[i].tmds_type = TMDS_EXT;
 885                         else
 886                                 mode_info->bios_connector[i].tmds_type = TMDS_INT;
 887
 888                         radeon_apply_legacy_quirks(dev, i);
 889                 }
 890         } else {
 891                 uint16_t tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
 892                 if (tmds_info) {
 893                         DRM_DEBUG("Found DFP table, assuming DVI connector\n");
 894
 895                         mode_info->bios_connector[0].valid = true;
 896                         mode_info->bios_connector[0].connector_type = CONNECTOR_DVI_I;
 897                         mode_info->bios_connector[0].dac_type = DAC_PRIMARY;
 898                         mode_info->bios_connector[0].tmds_type = TMDS_INT;
 899                         mode_info->bios_connector[0].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
 900                 } else {
 901                         DRM_DEBUG("No connector info found\n");
 902                         return false;
 903                 }
 904         }
 905
 906         if (dev_priv->flags & RADEON_IS_MOBILITY ||
 907             dev_priv->chip_family == CHIP_RS400 ||
 908             dev_priv->chip_family == CHIP_RS480) {
 909                 uint16_t lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
 910                 if (lcd_info) {
 911                         uint16_t lcd_ddc_info = lcd_ddc_info = combios_get_table_offset(dev, COMBIOS_LCD_DDC_INFO_TABLE);
 912
 913                         mode_info->bios_connector[4].valid = true;
 914                         mode_info->bios_connector[4].connector_type = CONNECTOR_LVDS;
 915                         mode_info->bios_connector[4].dac_type = DAC_NONE;
 916                         mode_info->bios_connector[4].tmds_type = TMDS_NONE;
 917                         mode_info->bios_connector[4].ddc_i2c.valid = false;
 918
 919                         if (lcd_ddc_info) {
 920                                 ddc_type = radeon_bios8(dev_priv, lcd_ddc_info + 2);
 921                                 switch(ddc_type) {
 922                                 case DDC_MONID:
 923                                         mode_info->bios_connector[4].ddc_i2c =
 924                                                 combios_setup_i2c_bus(RADEON_GPIO_MONID);
 925                                         break;
 926                                 case DDC_DVI:
 927                                         mode_info->bios_connector[4].ddc_i2c =
 928                                                 combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
 929                                         break;
 930                                 case DDC_VGA:
 931                                         mode_info->bios_connector[4].ddc_i2c =
 932                                                 combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
 933                                         break;
 934                                 case DDC_CRT2:
 935                                         mode_info->bios_connector[4].ddc_i2c =
 936                                                 combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
 937                                         break;
 938                                 case DDC_LCD:
 939                                         mode_info->bios_connector[4].ddc_i2c =
 940                                                 combios_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
 941                                         mode_info->bios_connector[4].ddc_i2c.mask_clk_mask =
 942                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
 943                                         mode_info->bios_connector[4].ddc_i2c.mask_data_mask =
 944                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
 945                                         mode_info->bios_connector[4].ddc_i2c.a_clk_mask =
 946                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
 947                                         mode_info->bios_connector[4].ddc_i2c.a_data_mask =
 948                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
 949                                         mode_info->bios_connector[4].ddc_i2c.put_clk_mask =
 950                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
 951                                         mode_info->bios_connector[4].ddc_i2c.put_data_mask =
 952                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
 953                                         mode_info->bios_connector[4].ddc_i2c.get_clk_mask =
 954                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
 955                                         mode_info->bios_connector[4].ddc_i2c.get_data_mask =
 956                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
 957                                         break;
 958                                 case DDC_GPIO:
 959                                         mode_info->bios_connector[4].ddc_i2c =
 960                                                 combios_setup_i2c_bus(RADEON_MDGPIO_EN_REG);
 961                                         mode_info->bios_connector[4].ddc_i2c.mask_clk_mask =
 962                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
 963                                         mode_info->bios_connector[4].ddc_i2c.mask_data_mask =
 964                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
 965                                         mode_info->bios_connector[4].ddc_i2c.a_clk_mask =
 966                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
 967                                         mode_info->bios_connector[4].ddc_i2c.a_data_mask =
 968                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
 969                                         mode_info->bios_connector[4].ddc_i2c.put_clk_mask =
 970                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
 971                                         mode_info->bios_connector[4].ddc_i2c.put_data_mask =
 972                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
 973                                         mode_info->bios_connector[4].ddc_i2c.get_clk_mask =
 974                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
 975                                         mode_info->bios_connector[4].ddc_i2c.get_data_mask =
 976                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
 977                                         break;
 978                                 default:
 979                                         break;
 980                                 }
 981                                 DRM_DEBUG("LCD DDC Info Table found!\n");
 982                         }
 983                 } else
 984                         mode_info->bios_connector[4].ddc_i2c.valid = false;
 985         }
 986
 987         /* check TV table */
 988         if (dev_priv->chip_family != CHIP_R100 &&
 989             dev_priv->chip_family != CHIP_R200) {
 990                 uint32_t tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 991                 if (tv_info) {
 992                         if (radeon_bios8(dev_priv, tv_info + 6) == 'T') {
 993                                 mode_info->bios_connector[5].valid = true;
 994                                 mode_info->bios_connector[5].connector_type = CONNECTOR_DIN;
 995                                 mode_info->bios_connector[5].dac_type = DAC_TVDAC;
 996                                 mode_info->bios_connector[5].tmds_type = TMDS_NONE;
 997                                 mode_info->bios_connector[5].ddc_i2c.valid = false;
 998                         }
 999                 }
1000         }
1001
1002
1003         DRM_DEBUG("BIOS Connector table\n");
1004         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
1005                 if (!mode_info->bios_connector[i].valid)
1006                         continue;
1007
1008                 DRM_DEBUG("Port %d: ddc_type 0x%x, dac_type %d, tmds_type %d, connector type %d, hpd_mask %d\n",
1009                           i, mode_info->bios_connector[i].ddc_i2c.mask_clk_reg,
1010                           mode_info->bios_connector[i].dac_type,
1011                           mode_info->bios_connector[i].tmds_type,
1012                           mode_info->bios_connector[i].connector_type,
1013                           mode_info->bios_connector[i].hpd_mask);
1014         }
1015
1016         return true;
1017 }
1018
1019 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
1020 {
1021         struct drm_radeon_private *dev_priv = dev->dev_private;
1022
1023         if (offset) {
1024                 while (radeon_bios16(dev_priv, offset)) {
1025                         uint16_t cmd  = ((radeon_bios16(dev_priv, offset) & 0xe000) >> 13);
1026                         uint32_t addr = (radeon_bios16(dev_priv, offset) & 0x1fff);
1027                         uint32_t val, and_mask, or_mask;
1028                         uint32_t tmp;
1029
1030                         offset += 2;
1031                         switch (cmd) {
1032                         case 0:
1033                                 val = radeon_bios32(dev_priv, offset);
1034                                 offset += 4;
1035                                 RADEON_WRITE(addr, val);
1036                                 break;
1037                         case 1:
1038                                 val = radeon_bios32(dev_priv, offset);
1039                                 offset += 4;
1040                                 RADEON_WRITE(addr, val);
1041                                 break;
1042                         case 2:
1043                                 and_mask = radeon_bios32(dev_priv, offset);
1044                                 offset += 4;
1045                                 or_mask = radeon_bios32(dev_priv, offset);
1046                                 offset += 4;
1047                                 tmp = RADEON_READ(addr);
1048                                 tmp &= and_mask;
1049                                 tmp |= or_mask;
1050                                 RADEON_WRITE(addr, tmp);
1051                                 break;
1052                         case 3:
1053                                 and_mask = radeon_bios32(dev_priv, offset);
1054                                 offset += 4;
1055                                 or_mask = radeon_bios32(dev_priv, offset);
1056                                 offset += 4;
1057                                 tmp = RADEON_READ(addr);
1058                                 tmp &= and_mask;
1059                                 tmp |= or_mask;
1060                                 RADEON_WRITE(addr, tmp);
1061                                 break;
1062                         case 4:
1063                                 val = radeon_bios16(dev_priv, offset);
1064                                 offset += 2;
1065                                 udelay(val);
1066                                 break;
1067                         case 5:
1068                                 val = radeon_bios16(dev_priv, offset);
1069                                 offset += 2;
1070                                 switch (addr) {
1071                                 case 8:
1072                                         while (val--) {
1073                                                 if (!(RADEON_READ_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL) &
1074                                                       RADEON_MC_BUSY))
1075                                                         break;
1076                                         }
1077                                         break;
1078                                 case 9:
1079                                         while (val--) {
1080                                                 if ((RADEON_READ(RADEON_MC_STATUS) &
1081                                                       RADEON_MC_IDLE))
1082                                                         break;
1083                                         }
1084                                         break;
1085                                 default:
1086                                         break;
1087                                 }
1088                                 break;
1089                         default:
1090                                 break;
1091                         }
1092                 }
1093         }
1094 }
1095
1096 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
1097 {
1098         struct drm_radeon_private *dev_priv = dev->dev_private;
1099
1100         if (offset) {
1101                 while (radeon_bios8(dev_priv, offset)) {
1102                         uint8_t cmd  = ((radeon_bios8(dev_priv, offset) & 0xc0) >> 6);
1103                         uint8_t addr = (radeon_bios8(dev_priv, offset) & 0x3f);
1104                         uint32_t val, shift, tmp;
1105                         uint32_t and_mask, or_mask;
1106
1107                         offset++;
1108                         switch (cmd) {
1109                         case 0:
1110                                 val = radeon_bios32(dev_priv, offset);
1111                                 offset += 4;
1112                                 RADEON_WRITE_PLL(dev_priv, addr, val);
1113                                 break;
1114                         case 1:
1115                                 shift = radeon_bios8(dev_priv, offset) * 8;
1116                                 offset++;
1117                                 and_mask = radeon_bios8(dev_priv, offset) << shift;
1118                                 and_mask |= ~(0xff << shift);
1119                                 offset++;
1120                                 or_mask = radeon_bios8(dev_priv, offset) << shift;
1121                                 offset++;
1122                                 tmp = RADEON_READ_PLL(dev_priv, addr);
1123                                 tmp &= and_mask;
1124                                 tmp |= or_mask;
1125                                 RADEON_WRITE_PLL(dev_priv, addr, tmp);
1126                                 break;
1127                         case 2:
1128                         case 3:
1129                                 tmp = 1000;
1130                                 switch (addr) {
1131                                 case 1:
1132                                         udelay(150);
1133                                         break;
1134                                 case 2:
1135                                         udelay(1000);
1136                                         break;
1137                                 case 3:
1138                                         while (tmp--) {
1139                                                 if (!(RADEON_READ_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL) &
1140                                                       RADEON_MC_BUSY))
1141                                                         break;
1142                                         }
1143                                         break;
1144                                 case 4:
1145                                         while (tmp--) {
1146                                                 if (RADEON_READ_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL) &
1147                                                     RADEON_DLL_READY)
1148                                                         break;
1149                                         }
1150                                         break;
1151                                 case 5:
1152                                         tmp = RADEON_READ_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL);
1153                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
1154 #if 0
1155                                                 uint32_t mclk_cntl = RADEON_READ_PLL(RADEON_MCLK_CNTL);
1156                                                 mclk_cntl &= 0xffff0000;
1157                                                 //mclk_cntl |= 0x00001111; /* ??? */
1158                                                 RADEON_WRITE_PLL(dev_priv, RADEON_MCLK_CNTL, mclk_cntl);
1159                                                 udelay(10000);
1160 #endif
1161                                                 RADEON_WRITE_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL,
1162                                                                  tmp & ~RADEON_CG_NO1_DEBUG_0);
1163                                                 udelay(10000);
1164                                         }
1165                                         break;
1166                                 default:
1167                                         break;
1168                                 }
1169                                 break;
1170                         default:
1171                                 break;
1172                         }
1173                 }
1174         }
1175 }
1176
1177 static void combios_parse_ram_reset_table(struct drm_device *dev, uint16_t offset)
1178 {
1179         struct drm_radeon_private *dev_priv = dev->dev_private;
1180         uint32_t tmp;
1181
1182         if (offset) {
1183                 uint8_t val = radeon_bios8(dev_priv, offset);
1184                 while (val != 0xff) {
1185                         offset++;
1186
1187                         if (val == 0x0f) {
1188                                 uint32_t channel_complete_mask;
1189
1190                                 if (radeon_is_r300(dev_priv))
1191                                         channel_complete_mask = R300_MEM_PWRUP_COMPLETE;
1192                                 else
1193                                         channel_complete_mask = RADEON_MEM_PWRUP_COMPLETE;
1194                                 tmp = 20000;
1195                                 while (tmp--) {
1196                                         if ((RADEON_READ(RADEON_MEM_STR_CNTL) &
1197                                              channel_complete_mask) ==
1198                                             channel_complete_mask)
1199                                                 break;
1200                                 }
1201                         } else {
1202                                 uint32_t or_mask = radeon_bios16(dev_priv, offset);
1203                                 offset += 2;
1204
1205                                 tmp = RADEON_READ(RADEON_MEM_SDRAM_MODE_REG);
1206                                 tmp &= RADEON_SDRAM_MODE_MASK;
1207                                 tmp |= or_mask;
1208                                 RADEON_WRITE(RADEON_MEM_SDRAM_MODE_REG, tmp);
1209
1210                                 or_mask = val << 24;
1211                                 tmp = RADEON_READ(RADEON_MEM_SDRAM_MODE_REG);
1212                                 tmp &= RADEON_B3MEM_RESET_MASK;
1213                                 tmp |= or_mask;
1214                                 RADEON_WRITE(RADEON_MEM_SDRAM_MODE_REG, tmp);
1215                         }
1216                         val = radeon_bios8(dev_priv, offset);
1217                 }
1218         }
1219 }
1220
1221 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
1222 {
1223         uint16_t dyn_clk_info = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
1224
1225         if (dyn_clk_info)
1226                 combios_parse_pll_table(dev, dyn_clk_info);
1227 }
1228
1229 void radeon_combios_asic_init(struct drm_device *dev)
1230 {
1231         uint16_t table;
1232
1233         /* ASIC INIT 1 */
1234         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
1235         if (table)
1236                 combios_parse_mmio_table(dev, table);
1237
1238         /* PLL INIT */
1239         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
1240         if (table)
1241                 combios_parse_pll_table(dev, table);
1242
1243         /* ASIC INIT 2 */
1244         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
1245         if (table)
1246                 combios_parse_mmio_table(dev, table);
1247
1248         /* ASIC INIT 4 */
1249         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
1250         if (table)
1251                 combios_parse_mmio_table(dev, table);
1252
1253         /* RAM RESET */
1254         table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
1255         if (table)
1256                 combios_parse_ram_reset_table(dev, table);
1257
1258         /* ASIC INIT 3 */
1259         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
1260         if (table)
1261                 combios_parse_mmio_table(dev, table);
1262
1263         /* DYN CLK 1 */
1264         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
1265         if (table)
1266                 combios_parse_pll_table(dev, table);
1267
1268         /* ASIC INIT 5 */
1269         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_5_TABLE);
1270         if (table)
1271                 combios_parse_mmio_table(dev, table);
1272
1273 }