linux-core/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon_drv.h"
  30
  31 /* old legacy ATI BIOS routines */
  32
  33 enum radeon_combios_ddc
  34 {
  35     DDC_NONE_DETECTED,
  36     DDC_MONID,
  37     DDC_DVI,
  38     DDC_VGA,
  39     DDC_CRT2,
  40     DDC_LCD,
  41     DDC_GPIO,
  42 };
  43
  44 enum radeon_combios_connector
  45 {
  46     CONNECTOR_NONE_LEGACY,
  47     CONNECTOR_PROPRIETARY_LEGACY,
  48     CONNECTOR_CRT_LEGACY,
  49     CONNECTOR_DVI_I_LEGACY,
  50     CONNECTOR_DVI_D_LEGACY,
  51     CONNECTOR_CTV_LEGACY,
  52     CONNECTOR_STV_LEGACY,
  53     CONNECTOR_UNSUPPORTED_LEGACY
  54 };
  55
  56 struct radeon_i2c_bus_rec combios_setup_i2c_bus(int ddc_line)
  57 {
  58         struct radeon_i2c_bus_rec i2c;
  59
  60         i2c.mask_clk_mask = RADEON_GPIO_EN_1;
  61         i2c.mask_data_mask = RADEON_GPIO_EN_0;
  62         i2c.a_clk_mask = RADEON_GPIO_A_1;
  63         i2c.a_data_mask = RADEON_GPIO_A_0;
  64         i2c.put_clk_mask = RADEON_GPIO_EN_1;
  65         i2c.put_data_mask = RADEON_GPIO_EN_0;
  66         i2c.get_clk_mask = RADEON_GPIO_Y_1;
  67         i2c.get_data_mask = RADEON_GPIO_Y_0;
  68         if ((ddc_line == RADEON_LCD_GPIO_MASK) ||
  69             (ddc_line == RADEON_MDGPIO_EN_REG)) {
  70                 i2c.mask_clk_reg = ddc_line;
  71                 i2c.mask_data_reg = ddc_line;
  72                 i2c.a_clk_reg = ddc_line;
  73                 i2c.a_data_reg = ddc_line;
  74                 i2c.put_clk_reg = ddc_line;
  75                 i2c.put_data_reg = ddc_line;
  76                 i2c.get_clk_reg = ddc_line + 4;
  77                 i2c.get_data_reg = ddc_line + 4;
  78         } else {
  79                 i2c.mask_clk_reg = ddc_line;
  80                 i2c.mask_data_reg = ddc_line;
  81                 i2c.a_clk_reg = ddc_line;
  82                 i2c.a_data_reg = ddc_line;
  83                 i2c.put_clk_reg = ddc_line;
  84                 i2c.put_data_reg = ddc_line;
  85                 i2c.get_clk_reg = ddc_line;
  86                 i2c.get_data_reg = ddc_line;
  87         }
  88
  89         if (ddc_line)
  90                 i2c.valid = true;
  91         else
  92                 i2c.valid = false;
  93
  94         return i2c;
  95 }
  96
  97 bool radeon_combios_get_clock_info(struct drm_device *dev)
  98 {
  99         struct drm_radeon_private *dev_priv = dev->dev_private;
 100         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 101         uint16_t pll_info_block;
 102         struct radeon_pll *pll = &mode_info->pll;
 103         int rev;
 104
 105         pll_info_block = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x30);
 106         rev = radeon_bios8(dev_priv, pll_info_block);
 107
 108         pll->reference_freq = radeon_bios16(dev_priv, pll_info_block + 0xe);
 109         pll->reference_div = radeon_bios16(dev_priv, pll_info_block + 0x10);
 110         pll->pll_out_min = radeon_bios32(dev_priv, pll_info_block + 0x12);
 111         pll->pll_out_max = radeon_bios32(dev_priv, pll_info_block + 0x16);
 112
 113         if (rev > 9) {
 114                 pll->pll_in_min = radeon_bios32(dev_priv, pll_info_block + 0x36);
 115                 pll->pll_in_max = radeon_bios32(dev_priv, pll_info_block + 0x3a);
 116         } else {
 117                 pll->pll_in_min = 40;
 118                 pll->pll_in_max = 500;
 119         }
 120
 121         pll->xclk = radeon_bios16(dev_priv, pll_info_block + 0x08);
 122
 123         // sclk/mclk use fixed point
 124
 125         return true;
 126
 127 }
 128
 129 bool radeon_combios_get_lvds_info(struct radeon_encoder *encoder)
 130 {
 131         struct drm_device *dev = encoder->base.dev;
 132         struct drm_radeon_private *dev_priv = dev->dev_private;
 133         uint16_t tmp;
 134         char stmp[30];
 135         int tmp0;
 136         int i;
 137
 138         tmp = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x40);
 139         if (!tmp) {
 140                 DRM_INFO("No panel info found in BIOS\n");
 141                 return false;
 142
 143         }
 144
 145         for (i = 0; i < 24; i++)
 146                 stmp[i] = radeon_bios8(dev_priv, tmp + i + 1);
 147         stmp[24] = 0;
 148
 149         DRM_INFO("Panel ID String: %s\n", stmp);
 150
 151         encoder->panel_xres = radeon_bios16(dev_priv, tmp + 25);
 152         encoder->panel_yres = radeon_bios16(dev_priv, tmp + 27);
 153
 154         DRM_INFO("Panel Size %dx%d\n", encoder->panel_xres, encoder->panel_yres);
 155
 156         encoder->panel_pwr_delay = radeon_bios16(dev_priv, tmp + 44);
 157         if (encoder->panel_pwr_delay > 2000 || encoder->panel_pwr_delay < 0)
 158                 encoder->panel_pwr_delay = 2000;
 159
 160         for (i = 0; i < 32; i++) {
 161                 tmp0 = radeon_bios16(dev_priv, tmp + 64 + i * 2);
 162                 if (tmp0 == 0) break;
 163
 164                 if ((radeon_bios16(dev_priv, tmp0) == encoder->panel_xres) &&
 165                     (radeon_bios16(dev_priv, tmp0 + 2) == encoder->panel_yres)) {
 166                         encoder->hblank = (radeon_bios16(dev_priv, tmp0 + 17) -
 167                                            radeon_bios16(dev_priv, tmp0 + 19)) * 8;
 168                         encoder->hoverplus = (radeon_bios16(dev_priv, tmp0 + 21) -
 169                                               radeon_bios16(dev_priv, tmp0 + 19) - 1) * 8;
 170                         encoder->hsync_width = radeon_bios8(dev_priv, tmp0 + 23) * 8;
 171
 172                         encoder->vblank = (radeon_bios16(dev_priv, tmp0 + 24) -
 173                                            radeon_bios16(dev_priv, tmp0 + 26));
 174                         encoder->voverplus = ((radeon_bios16(dev_priv, tmp0 + 28) & 0x7fff) -
 175                                               radeon_bios16(dev_priv, tmp0 + 26));
 176                         encoder->vsync_width = ((radeon_bios16(dev_priv, tmp0 + 28) & 0xf800) >> 11);
 177                         encoder->dotclock = radeon_bios16(dev_priv, tmp0 + 9) * 10;
 178                         encoder->flags = 0;
 179                 }
 180         }
 181         return true;
 182 }
 183
 184 bool radeon_combios_get_tmds_info(struct radeon_encoder *encoder)
 185 {
 186         struct drm_device *dev = encoder->base.dev;
 187         struct drm_radeon_private *dev_priv = dev->dev_private;
 188         uint16_t tmp;
 189         int i, n;
 190         uint8_t ver;
 191
 192         tmp = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x34);
 193         if (!tmp) {
 194                 DRM_INFO("No TMDS info found in BIOS\n");
 195                 return false;
 196         }
 197
 198         ver = radeon_bios8(dev_priv, tmp);
 199         DRM_INFO("DFP table revision: %d\n", ver);
 200         if (ver == 3) {
 201                 n = radeon_bios8(dev_priv, tmp + 5) + 1;
 202                 if (n > 4) n = 4;
 203                 for (i = 0; i < n; i++) {
 204                         encoder->tmds_pll[i].value = radeon_bios32(dev_priv, tmp+i*10+0x08);
 205                         encoder->tmds_pll[i].freq = radeon_bios16(dev_priv, tmp+i*10+0x10);
 206                 }
 207                 return true;
 208         } else if (ver == 4) {
 209                 int stride = 0;
 210                 n = radeon_bios8(dev_priv, tmp + 5) + 1;
 211                 if (n > 4) n = 4;
 212                 for (i = 0; i < n; i++) {
 213                         encoder->tmds_pll[i].value = radeon_bios32(dev_priv, tmp+stride+0x08);
 214                         encoder->tmds_pll[i].freq = radeon_bios16(dev_priv, tmp+stride+0x10);
 215                         if (i == 0) stride += 10;
 216                         else stride += 6;
 217                 }
 218                 return true;
 219         }
 220         return false;
 221 }
 222
 223 static void radeon_apply_legacy_quirks(struct drm_device *dev, int bios_index)
 224 {
 225         struct drm_radeon_private *dev_priv = dev->dev_private;
 226         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 227
 228         /* on XPRESS chips, CRT2_DDC and MONID_DCC both use the
 229          * MONID gpio, but use different pins.
 230          * CRT2_DDC uses the standard pinout, MONID_DDC uses
 231          * something else.
 232          */
 233         if ((dev_priv->chip_family == CHIP_RS400 ||
 234              dev_priv->chip_family == CHIP_RS480) &&
 235             mode_info->bios_connector[bios_index].connector_type == CONNECTOR_VGA &&
 236             mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) {
 237                 mode_info->bios_connector[bios_index].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
 238         }
 239
 240         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
 241            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
 242         if (dev->pdev->device == 0x515e &&
 243             dev->pdev->subsystem_vendor == 0x1014) {
 244                 if (mode_info->bios_connector[bios_index].connector_type == CONNECTOR_VGA &&
 245                     mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) {
 246                         mode_info->bios_connector[bios_index].valid = false;
 247                 }
 248         }
 249
 250         /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
 251         if (dev->pdev->device == 0x5159 &&
 252             dev->pdev->subsystem_vendor == 0x1002 &&
 253             dev->pdev->subsystem_device == 0x013a) {
 254                 if (mode_info->bios_connector[bios_index].connector_type == CONNECTOR_DVI_I)
 255                         mode_info->bios_connector[bios_index].connector_type = CONNECTOR_VGA;
 256
 257         }
 258
 259 }
 260
 261 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
 262 {
 263         struct drm_radeon_private *dev_priv = dev->dev_private;
 264         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 265         uint32_t offset, entry;
 266         uint16_t tmp0, tmp1, tmp;
 267         enum radeon_combios_ddc ddctype;
 268         enum radeon_combios_connector connector_type;
 269         int i;
 270
 271         DRM_DEBUG("\n");
 272         offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x50);
 273         if (offset) {
 274                 for (i = 0; i < 4; i++) {
 275                         entry = offset + 2 + i * 2;
 276
 277                         if (!radeon_bios16(dev_priv, entry))
 278                                     break;
 279
 280                         mode_info->bios_connector[i].valid = true;
 281
 282                         tmp = radeon_bios16(dev_priv, entry);
 283
 284                         connector_type = (tmp >> 12) & 0xf;
 285                         mode_info->bios_connector[i].connector_type = connector_type;
 286
 287                         switch(connector_type) {
 288                         case CONNECTOR_PROPRIETARY_LEGACY:
 289                                 mode_info->bios_connector[i].connector_type = CONNECTOR_DVI_D;
 290                                 break;
 291                         case CONNECTOR_CRT_LEGACY:
 292                                 mode_info->bios_connector[i].connector_type = CONNECTOR_VGA;
 293                                 break;
 294                         case CONNECTOR_DVI_I_LEGACY:
 295                                 mode_info->bios_connector[i].connector_type = CONNECTOR_DVI_I;
 296                                 break;
 297                         case CONNECTOR_DVI_D_LEGACY:
 298                                 mode_info->bios_connector[i].connector_type = CONNECTOR_DVI_D;
 299                                 break;
 300                         case CONNECTOR_CTV_LEGACY:
 301                                 mode_info->bios_connector[i].connector_type = CONNECTOR_CTV;
 302                                 break;
 303                         case CONNECTOR_STV_LEGACY:
 304                                 mode_info->bios_connector[i].connector_type = CONNECTOR_STV;
 305                                 break;
 306                         default:
 307                                 DRM_ERROR("Unknown connector type: %d\n", connector_type);
 308                                 mode_info->bios_connector[i].valid = false;
 309                                 break;
 310                         }
 311
 312                         mode_info->bios_connector[i].ddc_i2c.valid = false;
 313
 314                         ddctype = (tmp >> 8) & 0xf;
 315                         switch (ddctype) {
 316                         case DDC_MONID:
 317                                 mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
 318                                 break;
 319                         case DDC_DVI:
 320                                 mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
 321                                 break;
 322                         case DDC_VGA:
 323                                 mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
 324                                 break;
 325                         case DDC_CRT2:
 326                                 mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
 327                                 break;
 328                         default:
 329                                 break;
 330                         }
 331
 332                         if (tmp & 0x1)
 333                                 mode_info->bios_connector[i].dac_type = DAC_TVDAC;
 334                         else
 335                                 mode_info->bios_connector[i].dac_type = DAC_PRIMARY;
 336
 337                         if ((dev_priv->chip_family == CHIP_RS300) ||
 338                             (dev_priv->chip_family == CHIP_RS400) ||
 339                             (dev_priv->chip_family == CHIP_RS480))
 340                                 mode_info->bios_connector[i].dac_type = DAC_TVDAC;
 341
 342                         if ((tmp >> 4) & 0x1)
 343                                 mode_info->bios_connector[i].tmds_type = TMDS_EXT;
 344                         else
 345                                 mode_info->bios_connector[i].tmds_type = TMDS_INT;
 346
 347                         radeon_apply_legacy_quirks(dev, i);
 348                 }
 349         } else {
 350                 DRM_INFO("no connector table found in BIOS\n");
 351                 offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x34);
 352                 if (offset) {
 353                         DRM_DEBUG("Found DFP table, assuming DVI connector\n");
 354
 355                         mode_info->bios_connector[0].valid = true;
 356                         mode_info->bios_connector[0].connector_type = CONNECTOR_DVI_I;
 357                         mode_info->bios_connector[0].dac_type = DAC_PRIMARY;
 358                         mode_info->bios_connector[0].tmds_type = TMDS_INT;
 359                         mode_info->bios_connector[0].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
 360                 } else {
 361                         DRM_DEBUG("No table found\n");
 362                         return false;
 363                 }
 364         }
 365
 366         if (dev_priv->flags & RADEON_IS_MOBILITY) {
 367                 offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x40);
 368                 if (offset) {
 369                         mode_info->bios_connector[4].valid = true;
 370                         mode_info->bios_connector[4].connector_type = CONNECTOR_LVDS;
 371                         mode_info->bios_connector[4].dac_type = DAC_NONE;
 372                         mode_info->bios_connector[4].tmds_type = TMDS_NONE;
 373                         mode_info->bios_connector[4].ddc_i2c.valid = false;
 374
 375                         tmp = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x42);
 376                         if (tmp) {
 377                                 tmp0 = radeon_bios16(dev_priv, tmp + 0x15);
 378                                 if (tmp0) {
 379                                         tmp1 = radeon_bios8(dev_priv, tmp0 + 2) & 0x07;
 380                                         if (tmp1) {
 381                                                 ddctype = tmp1;
 382
 383                                                 switch(ddctype) {
 384                                                 case DDC_MONID:
 385                                                 case DDC_DVI:
 386                                                 case DDC_CRT2:
 387                                                 case DDC_LCD:
 388                                                 case DDC_GPIO:
 389                                                 default:
 390                                                         break;
 391                                                 }
 392                                                 DRM_DEBUG("LCD DDC Info Table found!\n");
 393                                         }
 394                                 }
 395                         } else
 396                                 mode_info->bios_connector[4].ddc_i2c.valid = false;
 397                 }
 398         }
 399
 400         DRM_DEBUG("BIOS Connector table\n");
 401         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
 402                 if (!mode_info->bios_connector[i].valid)
 403                         continue;
 404
 405                 DRM_DEBUG("Port %d: ddc_type 0x%x, dac_type %d, tmds_type %d, connector type %d, hpd_mask %d\n",
 406                           i, mode_info->bios_connector[i].ddc_i2c.mask_clk_reg,
 407                           mode_info->bios_connector[i].dac_type,
 408                           mode_info->bios_connector[i].tmds_type,
 409                           mode_info->bios_connector[i].connector_type,
 410                           mode_info->bios_connector[i].hpd_mask);
 411         }
 412
 413         return true;
 414 }
 415