linux-core/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon_drv.h"
  30
  31 /* old legacy ATI BIOS routines */
  32
  33 /* COMBIOS table offsets */
  34 enum radeon_combios_table_offset
  35 {
  36         /* absolute offset tables */
  37         COMBIOS_ASIC_INIT_1_TABLE,
  38         COMBIOS_BIOS_SUPPORT_TABLE,
  39         COMBIOS_DAC_PROGRAMMING_TABLE,
  40         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  41         COMBIOS_CRTC_INFO_TABLE,
  42         COMBIOS_PLL_INFO_TABLE,
  43         COMBIOS_TV_INFO_TABLE,
  44         COMBIOS_DFP_INFO_TABLE,
  45         COMBIOS_HW_CONFIG_INFO_TABLE,
  46         COMBIOS_MULTIMEDIA_INFO_TABLE,
  47         COMBIOS_TV_STD_PATCH_TABLE,
  48         COMBIOS_LCD_INFO_TABLE,
  49         COMBIOS_MOBILE_INFO_TABLE,
  50         COMBIOS_PLL_INIT_TABLE,
  51         COMBIOS_MEM_CONFIG_TABLE,
  52         COMBIOS_SAVE_MASK_TABLE,
  53         COMBIOS_HARDCODED_EDID_TABLE,
  54         COMBIOS_ASIC_INIT_2_TABLE,
  55         COMBIOS_CONNECTOR_INFO_TABLE,
  56         COMBIOS_DYN_CLK_1_TABLE,
  57         COMBIOS_RESERVED_MEM_TABLE,
  58         COMBIOS_EXT_TDMS_INFO_TABLE,
  59         COMBIOS_MEM_CLK_INFO_TABLE,
  60         COMBIOS_EXT_DAC_INFO_TABLE,
  61         COMBIOS_MISC_INFO_TABLE,
  62         COMBIOS_CRT_INFO_TABLE,
  63         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  64         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  65         COMBIOS_FAN_SPEED_INFO_TABLE,
  66         COMBIOS_OVERDRIVE_INFO_TABLE,
  67         COMBIOS_OEM_INFO_TABLE,
  68         COMBIOS_DYN_CLK_2_TABLE,
  69         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  70         COMBIOS_I2C_INFO_TABLE,
  71         /* relative offset tables */
  72         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
  73         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
  74         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
  75         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
  76         COMBIOS_POWERPLAY_TABLE,        /* offset from mobile info */
  77         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
  78         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
  79         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
  80         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
  81         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
  82 };
  83
  84 enum radeon_combios_ddc
  85 {
  86     DDC_NONE_DETECTED,
  87     DDC_MONID,
  88     DDC_DVI,
  89     DDC_VGA,
  90     DDC_CRT2,
  91     DDC_LCD,
  92     DDC_GPIO,
  93 };
  94
  95 enum radeon_combios_connector
  96 {
  97     CONNECTOR_NONE_LEGACY,
  98     CONNECTOR_PROPRIETARY_LEGACY,
  99     CONNECTOR_CRT_LEGACY,
 100     CONNECTOR_DVI_I_LEGACY,
 101     CONNECTOR_DVI_D_LEGACY,
 102     CONNECTOR_CTV_LEGACY,
 103     CONNECTOR_STV_LEGACY,
 104     CONNECTOR_UNSUPPORTED_LEGACY
 105 };
 106
 107 static uint16_t combios_get_table_offset(struct drm_device *dev, enum radeon_combios_table_offset table)
 108 {
 109         struct drm_radeon_private *dev_priv = dev->dev_private;
 110         int rev;
 111         uint16_t offset = 0, check_offset;
 112
 113         switch (table) {
 114         /* absolute offset tables */
 115         case COMBIOS_ASIC_INIT_1_TABLE:
 116                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0xc);
 117                 if (check_offset)
 118                         offset = check_offset;
 119                 break;
 120         case COMBIOS_BIOS_SUPPORT_TABLE:
 121                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x14);
 122                 if (check_offset)
 123                         offset = check_offset;
 124                 break;
 125         case COMBIOS_DAC_PROGRAMMING_TABLE:
 126                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x2a);
 127                 if (check_offset)
 128                         offset = check_offset;
 129                 break;
 130         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 131                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x2c);
 132                 if (check_offset)
 133                         offset = check_offset;
 134                 break;
 135         case COMBIOS_CRTC_INFO_TABLE:
 136                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x2e);
 137                 if (check_offset)
 138                         offset = check_offset;
 139                 break;
 140         case COMBIOS_PLL_INFO_TABLE:
 141                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x30);
 142                 if (check_offset)
 143                         offset = check_offset;
 144                 break;
 145         case COMBIOS_TV_INFO_TABLE:
 146                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x32);
 147                 if (check_offset)
 148                         offset = check_offset;
 149                 break;
 150         case COMBIOS_DFP_INFO_TABLE:
 151                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x34);
 152                 if (check_offset)
 153                         offset = check_offset;
 154                 break;
 155         case COMBIOS_HW_CONFIG_INFO_TABLE:
 156                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x36);
 157                 if (check_offset)
 158                         offset = check_offset;
 159                 break;
 160         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 161                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x38);
 162                 if (check_offset)
 163                         offset = check_offset;
 164                 break;
 165         case COMBIOS_TV_STD_PATCH_TABLE:
 166                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x3e);
 167                 if (check_offset)
 168                         offset = check_offset;
 169                 break;
 170         case COMBIOS_LCD_INFO_TABLE:
 171                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x40);
 172                 if (check_offset)
 173                         offset = check_offset;
 174                 break;
 175         case COMBIOS_MOBILE_INFO_TABLE:
 176                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x42);
 177                 if (check_offset)
 178                         offset = check_offset;
 179                 break;
 180         case COMBIOS_PLL_INIT_TABLE:
 181                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x46);
 182                 if (check_offset)
 183                         offset = check_offset;
 184                 break;
 185         case COMBIOS_MEM_CONFIG_TABLE:
 186                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x48);
 187                 if (check_offset)
 188                         offset = check_offset;
 189                 break;
 190         case COMBIOS_SAVE_MASK_TABLE:
 191                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x4a);
 192                 if (check_offset)
 193                         offset = check_offset;
 194                 break;
 195         case COMBIOS_HARDCODED_EDID_TABLE:
 196                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x4c);
 197                 if (check_offset)
 198                         offset = check_offset;
 199                 break;
 200         case COMBIOS_ASIC_INIT_2_TABLE:
 201                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x4e);
 202                 if (check_offset)
 203                         offset = check_offset;
 204                 break;
 205         case COMBIOS_CONNECTOR_INFO_TABLE:
 206                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x50);
 207                 if (check_offset)
 208                         offset = check_offset;
 209                 break;
 210         case COMBIOS_DYN_CLK_1_TABLE:
 211                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x52);
 212                 if (check_offset)
 213                         offset = check_offset;
 214                 break;
 215         case COMBIOS_RESERVED_MEM_TABLE:
 216                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x54);
 217                 if (check_offset)
 218                         offset = check_offset;
 219                 break;
 220         case COMBIOS_EXT_TDMS_INFO_TABLE:
 221                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x58);
 222                 if (check_offset)
 223                         offset = check_offset;
 224                 break;
 225         case COMBIOS_MEM_CLK_INFO_TABLE:
 226                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x5a);
 227                 if (check_offset)
 228                         offset = check_offset;
 229                 break;
 230         case COMBIOS_EXT_DAC_INFO_TABLE:
 231                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x5c);
 232                 if (check_offset)
 233                         offset = check_offset;
 234                 break;
 235         case COMBIOS_MISC_INFO_TABLE:
 236                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x5e);
 237                 if (check_offset)
 238                         offset = check_offset;
 239                 break;
 240         case COMBIOS_CRT_INFO_TABLE:
 241                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x60);
 242                 if (check_offset)
 243                         offset = check_offset;
 244                 break;
 245         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 246                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x62);
 247                 if (check_offset)
 248                         offset = check_offset;
 249                 break;
 250         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 251                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x64);
 252                 if (check_offset)
 253                         offset = check_offset;
 254                 break;
 255         case COMBIOS_FAN_SPEED_INFO_TABLE:
 256                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x66);
 257                 if (check_offset)
 258                         offset = check_offset;
 259                 break;
 260         case COMBIOS_OVERDRIVE_INFO_TABLE:
 261                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x68);
 262                 if (check_offset)
 263                         offset = check_offset;
 264                 break;
 265         case COMBIOS_OEM_INFO_TABLE:
 266                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x6a);
 267                 if (check_offset)
 268                         offset = check_offset;
 269                 break;
 270         case COMBIOS_DYN_CLK_2_TABLE:
 271                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x6c);
 272                 if (check_offset)
 273                         offset = check_offset;
 274                 break;
 275         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 276                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x6e);
 277                 if (check_offset)
 278                         offset = check_offset;
 279                 break;
 280         case COMBIOS_I2C_INFO_TABLE:
 281                 check_offset = radeon_bios16(dev_priv, dev_priv->bios_header_start + 0x70);
 282                 if (check_offset)
 283                         offset = check_offset;
 284                 break;
 285         /* relative offset tables */
 286         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 287                 check_offset = combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 288                 if (check_offset) {
 289                         rev = radeon_bios8(dev_priv, check_offset);
 290                         if (rev > 0) {
 291                                 check_offset = radeon_bios16(dev_priv, check_offset + 0x3);
 292                                 if (check_offset)
 293                                         offset = check_offset;
 294                         }
 295                 }
 296                 break;
 297         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 298                 check_offset = combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 299                 if (check_offset) {
 300                         rev = radeon_bios8(dev_priv, check_offset);
 301                         if (rev > 0) {
 302                                 check_offset = radeon_bios16(dev_priv, check_offset + 0x5);
 303                                 if (check_offset)
 304                                         offset = check_offset;
 305                         }
 306                 }
 307                 break;
 308         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 309                 check_offset = combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 310                 if (check_offset) {
 311                         rev = radeon_bios8(dev_priv, check_offset);
 312                         if (rev == 2) {
 313                                 check_offset = radeon_bios16(dev_priv, check_offset + 0x9);
 314                                 if (check_offset)
 315                                         offset = check_offset;
 316                         }
 317                 }
 318                 break;
 319         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 320                 check_offset = combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 321                 if (check_offset) {
 322                         while (radeon_bios8(dev_priv, check_offset++));
 323                         check_offset += 2;
 324                         if (check_offset)
 325                                 offset = check_offset;
 326                 }
 327                 break;
 328         case COMBIOS_POWERPLAY_TABLE:   /* offset from mobile info */
 329                 check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 330                 if (check_offset) {
 331                         check_offset = radeon_bios16(dev_priv, check_offset + 0x11);
 332                         if (check_offset)
 333                                 offset = check_offset;
 334                 }
 335                 break;
 336         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 337                 check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 338                 if (check_offset) {
 339                         check_offset = radeon_bios16(dev_priv, check_offset + 0x13);
 340                         if (check_offset)
 341                                 offset = check_offset;
 342                 }
 343                 break;
 344         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 345                 check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 346                 if (check_offset) {
 347                         check_offset = radeon_bios16(dev_priv, check_offset + 0x15);
 348                         if (check_offset)
 349                                 offset = check_offset;
 350                 }
 351                 break;
 352         case COMBIOS_TMDS_POWER_TABLE:          /* offset from mobile info */
 353                 check_offset = combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 354                 if (check_offset) {
 355                         check_offset = radeon_bios16(dev_priv, check_offset + 0x17);
 356                         if (check_offset)
 357                                 offset = check_offset;
 358                 }
 359                 break;
 360         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 361                 check_offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 362                 if (check_offset) {
 363                         check_offset = radeon_bios16(dev_priv, check_offset + 0x2);
 364                         if (check_offset)
 365                                 offset = check_offset;
 366                 }
 367                 break;
 368         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 369                 check_offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 370                 if (check_offset) {
 371                         check_offset = radeon_bios16(dev_priv, check_offset + 0x4);
 372                         if (check_offset)
 373                                 offset = check_offset;
 374                 }
 375                 break;
 376         default:
 377                 break;
 378         }
 379
 380         return offset;
 381
 382 }
 383
 384 struct radeon_i2c_bus_rec combios_setup_i2c_bus(int ddc_line)
 385 {
 386         struct radeon_i2c_bus_rec i2c;
 387
 388         i2c.mask_clk_mask = RADEON_GPIO_EN_1;
 389         i2c.mask_data_mask = RADEON_GPIO_EN_0;
 390         i2c.a_clk_mask = RADEON_GPIO_A_1;
 391         i2c.a_data_mask = RADEON_GPIO_A_0;
 392         i2c.put_clk_mask = RADEON_GPIO_EN_1;
 393         i2c.put_data_mask = RADEON_GPIO_EN_0;
 394         i2c.get_clk_mask = RADEON_GPIO_Y_1;
 395         i2c.get_data_mask = RADEON_GPIO_Y_0;
 396         if ((ddc_line == RADEON_LCD_GPIO_MASK) ||
 397             (ddc_line == RADEON_MDGPIO_EN_REG)) {
 398                 i2c.mask_clk_reg = ddc_line;
 399                 i2c.mask_data_reg = ddc_line;
 400                 i2c.a_clk_reg = ddc_line;
 401                 i2c.a_data_reg = ddc_line;
 402                 i2c.put_clk_reg = ddc_line;
 403                 i2c.put_data_reg = ddc_line;
 404                 i2c.get_clk_reg = ddc_line + 4;
 405                 i2c.get_data_reg = ddc_line + 4;
 406         } else {
 407                 i2c.mask_clk_reg = ddc_line;
 408                 i2c.mask_data_reg = ddc_line;
 409                 i2c.a_clk_reg = ddc_line;
 410                 i2c.a_data_reg = ddc_line;
 411                 i2c.put_clk_reg = ddc_line;
 412                 i2c.put_data_reg = ddc_line;
 413                 i2c.get_clk_reg = ddc_line;
 414                 i2c.get_data_reg = ddc_line;
 415         }
 416
 417         if (ddc_line)
 418                 i2c.valid = true;
 419         else
 420                 i2c.valid = false;
 421
 422         return i2c;
 423 }
 424
 425 bool radeon_combios_get_clock_info(struct drm_device *dev)
 426 {
 427         struct drm_radeon_private *dev_priv = dev->dev_private;
 428         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 429         uint16_t pll_info;
 430         struct radeon_pll *pll = &mode_info->pll;
 431         int8_t rev;
 432
 433         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 434         if (pll_info) {
 435                 rev = radeon_bios8(dev_priv, pll_info);
 436
 437                 pll->reference_freq = radeon_bios16(dev_priv, pll_info + 0xe);
 438                 pll->reference_div = radeon_bios16(dev_priv, pll_info + 0x10);
 439                 pll->pll_out_min = radeon_bios32(dev_priv, pll_info + 0x12);
 440                 pll->pll_out_max = radeon_bios32(dev_priv, pll_info + 0x16);
 441
 442                 if (rev > 9) {
 443                         pll->pll_in_min = radeon_bios32(dev_priv, pll_info + 0x36);
 444                         pll->pll_in_max = radeon_bios32(dev_priv, pll_info + 0x3a);
 445                 } else {
 446                         pll->pll_in_min = 40;
 447                         pll->pll_in_max = 500;
 448                 }
 449
 450                 pll->xclk = radeon_bios16(dev_priv, pll_info + 0x08);
 451
 452                 // sclk/mclk use fixed point
 453                 //sclk = radeon_bios16(pll_info + 8) / 100.0;
 454                 //mclk = radeon_bios16(pll_info + 10) / 100.0;
 455                 //if (sclk == 0) sclk = 200;
 456                 //if (mclk == 0) mclk = 200;
 457
 458                 return true;
 459         }
 460         return false;
 461 }
 462
 463 bool radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder)
 464 {
 465         struct drm_device *dev = encoder->base.dev;
 466         struct drm_radeon_private *dev_priv = dev->dev_private;
 467         uint16_t dac_info;
 468         uint8_t rev, bg, dac;
 469
 470         /* check CRT table */
 471         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 472         if (dac_info) {
 473                 rev = radeon_bios8(dev_priv, dac_info) & 0x3;
 474                 if (rev < 2) {
 475                         bg = radeon_bios8(dev_priv, dac_info + 0x2) & 0xf;
 476                         dac = (radeon_bios8(dev_priv, dac_info + 0x2) >> 4) & 0xf;
 477                         encoder->ps2_pdac_adj = (bg << 8) | (dac);
 478
 479                         return true;
 480                 } else {
 481                         bg = radeon_bios8(dev_priv, dac_info + 0x2) & 0xf;
 482                         dac = radeon_bios8(dev_priv, dac_info + 0x3) & 0xf;
 483                         encoder->ps2_pdac_adj = (bg << 8) | (dac);
 484
 485                         return true;
 486                 }
 487
 488         }
 489
 490         return false;
 491 }
 492
 493 bool radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder)
 494 {
 495         struct drm_device *dev = encoder->base.dev;
 496         struct drm_radeon_private *dev_priv = dev->dev_private;
 497         uint16_t dac_info;
 498         uint8_t rev, bg, dac;
 499
 500         /* first check TV table */
 501         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 502         if (dac_info) {
 503                 rev = radeon_bios8(dev_priv, dac_info + 0x3);
 504                 if (rev > 4) {
 505                         bg = radeon_bios8(dev_priv, dac_info + 0xc) & 0xf;
 506                         dac = radeon_bios8(dev_priv, dac_info + 0xd) & 0xf;
 507                         encoder->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 508
 509                         bg = radeon_bios8(dev_priv, dac_info + 0xe) & 0xf;
 510                         dac = radeon_bios8(dev_priv, dac_info + 0xf) & 0xf;
 511                         encoder->pal_tvdac_adj = (bg << 16) | (dac << 20);
 512
 513                         bg = radeon_bios8(dev_priv, dac_info + 0x10) & 0xf;
 514                         dac = radeon_bios8(dev_priv, dac_info + 0x11) & 0xf;
 515                         encoder->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 516
 517                         return true;
 518                 } else if (rev > 1) {
 519                         bg = radeon_bios8(dev_priv, dac_info + 0xc) & 0xf;
 520                         dac = (radeon_bios8(dev_priv, dac_info + 0xc) >> 4) & 0xf;
 521                         encoder->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 522
 523                         bg = radeon_bios8(dev_priv, dac_info + 0xd) & 0xf;
 524                         dac = (radeon_bios8(dev_priv, dac_info + 0xd) >> 4) & 0xf;
 525                         encoder->pal_tvdac_adj = (bg << 16) | (dac << 20);
 526
 527                         bg = radeon_bios8(dev_priv, dac_info + 0xe) & 0xf;
 528                         dac = (radeon_bios8(dev_priv, dac_info + 0xe) >> 4) & 0xf;
 529                         encoder->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 530
 531                         return true;
 532                 }
 533         }
 534
 535         /* then check CRT table */
 536         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 537         if (dac_info) {
 538                 rev = radeon_bios8(dev_priv, dac_info) & 0x3;
 539                 if (rev < 2) {
 540                         bg = radeon_bios8(dev_priv, dac_info + 0x3) & 0xf;
 541                         dac = (radeon_bios8(dev_priv, dac_info + 0x3) >> 4) & 0xf;
 542                         encoder->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 543                         encoder->pal_tvdac_adj = encoder->ps2_tvdac_adj;
 544                         encoder->ntsc_tvdac_adj = encoder->ps2_tvdac_adj;
 545
 546                         return true;
 547                 } else {
 548                         bg = radeon_bios8(dev_priv, dac_info + 0x4) & 0xf;
 549                         dac = radeon_bios8(dev_priv, dac_info + 0x5) & 0xf;
 550                         encoder->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 551                         encoder->pal_tvdac_adj = encoder->ps2_tvdac_adj;
 552                         encoder->ntsc_tvdac_adj = encoder->ps2_tvdac_adj;
 553
 554                         return true;
 555                 }
 556
 557         }
 558
 559         return false;
 560 }
 561
 562 bool radeon_combios_get_tv_info(struct radeon_encoder *encoder)
 563 {
 564         struct drm_device *dev = encoder->base.dev;
 565         struct drm_radeon_private *dev_priv = dev->dev_private;
 566         uint16_t tv_info;
 567
 568         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 569         if (tv_info) {
 570                 if (radeon_bios8(dev_priv, tv_info + 6) == 'T') {
 571                         switch (radeon_bios8(dev_priv, tv_info + 7) & 0xf) {
 572                         case 1:
 573                                 encoder->tv_std = TV_STD_NTSC;
 574                                 DRM_INFO("Default TV standard: NTSC\n");
 575                                 break;
 576                         case 2:
 577                                 encoder->tv_std = TV_STD_PAL;
 578                                 DRM_INFO("Default TV standard: PAL\n");
 579                                 break;
 580                         case 3:
 581                                 encoder->tv_std = TV_STD_PAL_M;
 582                                 DRM_INFO("Default TV standard: PAL-M\n");
 583                                 break;
 584                         case 4:
 585                                 encoder->tv_std = TV_STD_PAL_60;
 586                                 DRM_INFO("Default TV standard: PAL-60\n");
 587                                 break;
 588                         case 5:
 589                                 encoder->tv_std = TV_STD_NTSC_J;
 590                                 DRM_INFO("Default TV standard: NTSC-J\n");
 591                                 break;
 592                         case 6:
 593                                 encoder->tv_std = TV_STD_SCART_PAL;
 594                                 DRM_INFO("Default TV standard: SCART-PAL\n");
 595                                 break;
 596                         default:
 597                                 encoder->tv_std = TV_STD_NTSC;
 598                                 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
 599                                 break;
 600                         }
 601
 602                         switch ((radeon_bios8(dev_priv, tv_info + 9) >> 2) & 0x3) {
 603                         case 0:
 604                                 DRM_INFO("29.498928713 MHz TV ref clk\n");
 605                                 break;
 606                         case 1:
 607                                 DRM_INFO("28.636360000 MHz TV ref clk\n");
 608                                 break;
 609                         case 2:
 610                                 DRM_INFO("14.318180000 MHz TV ref clk\n");
 611                                 break;
 612                         case 3:
 613                                 DRM_INFO("27.000000000 MHz TV ref clk\n");
 614                                 break;
 615                         default:
 616                                 break;
 617                         }
 618                         return true;
 619                 }
 620         }
 621         return false;
 622 }
 623
 624 bool radeon_combios_get_lvds_info(struct radeon_encoder *encoder)
 625 {
 626         struct drm_device *dev = encoder->base.dev;
 627         struct drm_radeon_private *dev_priv = dev->dev_private;
 628         uint16_t lcd_info;
 629         uint32_t panel_setup;
 630         char stmp[30];
 631         int tmp, i;
 632
 633         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
 634
 635         if (lcd_info) {
 636                 for (i = 0; i < 24; i++)
 637                         stmp[i] = radeon_bios8(dev_priv, lcd_info + i + 1);
 638                 stmp[24] = 0;
 639
 640                 DRM_INFO("Panel ID String: %s\n", stmp);
 641
 642                 encoder->panel_xres = radeon_bios16(dev_priv, lcd_info + 25);
 643                 encoder->panel_yres = radeon_bios16(dev_priv, lcd_info + 27);
 644
 645                 DRM_INFO("Panel Size %dx%d\n", encoder->panel_xres, encoder->panel_yres);
 646
 647                 encoder->panel_vcc_delay = radeon_bios16(dev_priv, lcd_info + 44);
 648                 if (encoder->panel_vcc_delay > 2000 || encoder->panel_vcc_delay < 0)
 649                         encoder->panel_vcc_delay = 2000;
 650
 651                 encoder->panel_pwr_delay = radeon_bios16(dev_priv, lcd_info + 0x24);
 652                 encoder->panel_digon_delay = radeon_bios16(dev_priv, lcd_info + 0x38) & 0xf;
 653                 encoder->panel_blon_delay = (radeon_bios16(dev_priv, lcd_info + 0x38) >> 4) & 0xf;
 654
 655                 encoder->panel_ref_divider = radeon_bios16(dev_priv, lcd_info + 46);
 656                 encoder->panel_post_divider = radeon_bios8(dev_priv, lcd_info + 48);
 657                 encoder->panel_fb_divider = radeon_bios16(dev_priv, lcd_info + 49);
 658                 if ((encoder->panel_ref_divider != 0) &&
 659                     (encoder->panel_fb_divider > 3))
 660                         encoder->use_bios_dividers = true;
 661
 662                 panel_setup = radeon_bios32(dev_priv, lcd_info + 0x39);
 663                 encoder->lvds_gen_cntl = 0;
 664                 if (panel_setup & 0x1)
 665                         encoder->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
 666
 667                 if ((panel_setup >> 4) & 0x1)
 668                         encoder->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
 669
 670                 switch ((panel_setup >> 8) & 0x8) {
 671                 case 0:
 672                         encoder->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
 673                         break;
 674                 case 1:
 675                         encoder->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
 676                         break;
 677                 case 2:
 678                         encoder->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
 679                         break;
 680                 default:
 681                         break;
 682                 }
 683
 684                 if ((panel_setup >> 16) & 0x1)
 685                         encoder->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
 686
 687                 if ((panel_setup >> 17) & 0x1)
 688                         encoder->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
 689
 690                 if ((panel_setup >> 18) & 0x1)
 691                         encoder->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
 692
 693                 if ((panel_setup >> 23) & 0x1)
 694                         encoder->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
 695
 696                 encoder->lvds_gen_cntl |= (panel_setup & 0xf0000000);
 697
 698
 699                 for (i = 0; i < 32; i++) {
 700                         tmp = radeon_bios16(dev_priv, lcd_info + 64 + i * 2);
 701                         if (tmp == 0) break;
 702
 703                         if ((radeon_bios16(dev_priv, tmp) == encoder->panel_xres) &&
 704                             (radeon_bios16(dev_priv, tmp + 2) == encoder->panel_yres)) {
 705                                 encoder->hblank = (radeon_bios16(dev_priv, tmp + 17) -
 706                                                    radeon_bios16(dev_priv, tmp + 19)) * 8;
 707                                 encoder->hoverplus = (radeon_bios16(dev_priv, tmp + 21) -
 708                                                       radeon_bios16(dev_priv, tmp + 19) - 1) * 8;
 709                                 encoder->hsync_width = radeon_bios8(dev_priv, tmp + 23) * 8;
 710
 711                                 encoder->vblank = (radeon_bios16(dev_priv, tmp + 24) -
 712                                                    radeon_bios16(dev_priv, tmp + 26));
 713                                 encoder->voverplus = ((radeon_bios16(dev_priv, tmp + 28) & 0x7fff) -
 714                                                       radeon_bios16(dev_priv, tmp + 26));
 715                                 encoder->vsync_width = ((radeon_bios16(dev_priv, tmp + 28) & 0xf800) >> 11);
 716                                 encoder->dotclock = radeon_bios16(dev_priv, tmp + 9) * 10;
 717                                 encoder->flags = 0;
 718                         }
 719                 }
 720                 return true;
 721         }
 722         DRM_INFO("No panel info found in BIOS\n");
 723         return false;
 724
 725 }
 726
 727 bool radeon_combios_get_tmds_info(struct radeon_encoder *encoder)
 728 {
 729         struct drm_device *dev = encoder->base.dev;
 730         struct drm_radeon_private *dev_priv = dev->dev_private;
 731         uint16_t tmds_info;
 732         int i, n;
 733         uint8_t ver;
 734
 735         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
 736
 737         if (tmds_info) {
 738                 ver = radeon_bios8(dev_priv, tmds_info);
 739                 DRM_INFO("DFP table revision: %d\n", ver);
 740                 if (ver == 3) {
 741                         n = radeon_bios8(dev_priv, tmds_info + 5) + 1;
 742                         if (n > 4)
 743                                 n = 4;
 744                         for (i = 0; i < n; i++) {
 745                                 encoder->tmds_pll[i].value = radeon_bios32(dev_priv, tmds_info + i * 10 + 0x08);
 746                                 encoder->tmds_pll[i].freq = radeon_bios16(dev_priv, tmds_info + i * 10 + 0x10);
 747                         }
 748                         return true;
 749                 } else if (ver == 4) {
 750                         int stride = 0;
 751                         n = radeon_bios8(dev_priv, tmds_info + 5) + 1;
 752                         if (n > 4)
 753                                 n = 4;
 754                         for (i = 0; i < n; i++) {
 755                                 encoder->tmds_pll[i].value = radeon_bios32(dev_priv, tmds_info + stride + 0x08);
 756                                 encoder->tmds_pll[i].freq = radeon_bios16(dev_priv, tmds_info + stride + 0x10);
 757                                 if (i == 0)
 758                                         stride += 10;
 759                                 else
 760                                         stride += 6;
 761                         }
 762                         return true;
 763                 }
 764         }
 765
 766         DRM_INFO("No TMDS info found in BIOS\n");
 767         return false;
 768 }
 769
 770 static void radeon_apply_legacy_quirks(struct drm_device *dev, int bios_index)
 771 {
 772         struct drm_radeon_private *dev_priv = dev->dev_private;
 773         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 774
 775         /* XPRESS DDC quirks */
 776         if ((dev_priv->chip_family == CHIP_RS400 ||
 777              dev_priv->chip_family == CHIP_RS480) &&
 778             mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) {
 779                 mode_info->bios_connector[bios_index].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
 780         } else if ((dev_priv->chip_family == CHIP_RS400 ||
 781                     dev_priv->chip_family == CHIP_RS480) &&
 782                    mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_reg == RADEON_GPIO_MONID) {
 783                 mode_info->bios_connector[bios_index].ddc_i2c.valid = true;
 784                 mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_mask = (0x20 << 8);
 785                 mode_info->bios_connector[bios_index].ddc_i2c.mask_data_mask = 0x80;
 786                 mode_info->bios_connector[bios_index].ddc_i2c.a_clk_mask = (0x20 << 8);
 787                 mode_info->bios_connector[bios_index].ddc_i2c.a_data_mask = 0x80;
 788                 mode_info->bios_connector[bios_index].ddc_i2c.put_clk_mask = (0x20 << 8);
 789                 mode_info->bios_connector[bios_index].ddc_i2c.put_data_mask = 0x80;
 790                 mode_info->bios_connector[bios_index].ddc_i2c.get_clk_mask = (0x20 << 8);
 791                 mode_info->bios_connector[bios_index].ddc_i2c.get_data_mask = 0x80;
 792                 mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 793                 mode_info->bios_connector[bios_index].ddc_i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 794                 mode_info->bios_connector[bios_index].ddc_i2c.a_clk_reg = RADEON_GPIOPAD_A;
 795                 mode_info->bios_connector[bios_index].ddc_i2c.a_data_reg = RADEON_GPIOPAD_A;
 796                 mode_info->bios_connector[bios_index].ddc_i2c.put_clk_reg = RADEON_GPIOPAD_EN;
 797                 mode_info->bios_connector[bios_index].ddc_i2c.put_data_reg = RADEON_GPIOPAD_EN;
 798                 mode_info->bios_connector[bios_index].ddc_i2c.get_clk_reg = RADEON_LCD_GPIO_Y_REG;
 799                 mode_info->bios_connector[bios_index].ddc_i2c.get_data_reg = RADEON_LCD_GPIO_Y_REG;
 800         }
 801
 802         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
 803            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
 804         if (dev->pdev->device == 0x515e &&
 805             dev->pdev->subsystem_vendor == 0x1014) {
 806                 if (mode_info->bios_connector[bios_index].connector_type == CONNECTOR_VGA &&
 807                     mode_info->bios_connector[bios_index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) {
 808                         mode_info->bios_connector[bios_index].valid = false;
 809                 }
 810         }
 811
 812         /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
 813         if (dev->pdev->device == 0x5159 &&
 814             dev->pdev->subsystem_vendor == 0x1002 &&
 815             dev->pdev->subsystem_device == 0x013a) {
 816                 if (mode_info->bios_connector[bios_index].connector_type == CONNECTOR_DVI_I)
 817                         mode_info->bios_connector[bios_index].connector_type = CONNECTOR_VGA;
 818
 819         }
 820
 821         /* X300 card with extra non-existent DVI port */
 822         if (dev->pdev->device == 0x5B60 &&
 823             dev->pdev->subsystem_vendor == 0x17af &&
 824             dev->pdev->subsystem_device == 0x201e &&
 825             bios_index == 2) {
 826                 if (mode_info->bios_connector[bios_index].connector_type == CONNECTOR_DVI_I)
 827                         mode_info->bios_connector[bios_index].valid = false;
 828         }
 829
 830 }
 831
 832 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
 833 {
 834         struct drm_radeon_private *dev_priv = dev->dev_private;
 835         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 836         uint32_t conn_info, entry;
 837         uint16_t tmp;
 838         enum radeon_combios_ddc ddc_type;
 839         enum radeon_combios_connector connector_type;
 840         int i;
 841
 842         DRM_DEBUG("\n");
 843         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
 844         if (conn_info) {
 845                 for (i = 0; i < 4; i++) {
 846                         entry = conn_info + 2 + i * 2;
 847
 848                         if (!radeon_bios16(dev_priv, entry))
 849                                     break;
 850
 851                         mode_info->bios_connector[i].valid = true;
 852
 853                         tmp = radeon_bios16(dev_priv, entry);
 854
 855                         connector_type = (tmp >> 12) & 0xf;
 856                         mode_info->bios_connector[i].connector_type = connector_type;
 857
 858                         switch(connector_type) {
 859                         case CONNECTOR_PROPRIETARY_LEGACY:
 860                                 mode_info->bios_connector[i].connector_type = CONNECTOR_DVI_D;
 861                                 break;
 862                         case CONNECTOR_CRT_LEGACY:
 863                                 mode_info->bios_connector[i].connector_type = CONNECTOR_VGA;
 864                                 break;
 865                         case CONNECTOR_DVI_I_LEGACY:
 866                                 mode_info->bios_connector[i].connector_type = CONNECTOR_DVI_I;
 867                                 break;
 868                         case CONNECTOR_DVI_D_LEGACY:
 869                                 mode_info->bios_connector[i].connector_type = CONNECTOR_DVI_D;
 870                                 break;
 871                         case CONNECTOR_CTV_LEGACY:
 872                                 mode_info->bios_connector[i].connector_type = CONNECTOR_CTV;
 873                                 break;
 874                         case CONNECTOR_STV_LEGACY:
 875                                 mode_info->bios_connector[i].connector_type = CONNECTOR_STV;
 876                                 break;
 877                         default:
 878                                 DRM_ERROR("Unknown connector type: %d\n", connector_type);
 879                                 mode_info->bios_connector[i].valid = false;
 880                                 break;
 881                         }
 882
 883                         mode_info->bios_connector[i].ddc_i2c.valid = false;
 884
 885                         ddc_type = (tmp >> 8) & 0xf;
 886                         switch (ddc_type) {
 887                         case DDC_MONID:
 888                                 mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
 889                                 break;
 890                         case DDC_DVI:
 891                                 mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
 892                                 break;
 893                         case DDC_VGA:
 894                                 mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
 895                                 break;
 896                         case DDC_CRT2:
 897                                 mode_info->bios_connector[i].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
 898                                 break;
 899                         default:
 900                                 break;
 901                         }
 902
 903                         if (tmp & 0x1)
 904                                 mode_info->bios_connector[i].dac_type = DAC_TVDAC;
 905                         else
 906                                 mode_info->bios_connector[i].dac_type = DAC_PRIMARY;
 907
 908                         if ((dev_priv->chip_family == CHIP_RS300) ||
 909                             (dev_priv->chip_family == CHIP_RS400) ||
 910                             (dev_priv->chip_family == CHIP_RS480))
 911                                 mode_info->bios_connector[i].dac_type = DAC_TVDAC;
 912
 913                         if ((tmp >> 4) & 0x1)
 914                                 mode_info->bios_connector[i].tmds_type = TMDS_EXT;
 915                         else
 916                                 mode_info->bios_connector[i].tmds_type = TMDS_INT;
 917
 918                         radeon_apply_legacy_quirks(dev, i);
 919                 }
 920         } else {
 921                 uint16_t tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
 922                 if (tmds_info) {
 923                         DRM_DEBUG("Found DFP table, assuming DVI connector\n");
 924
 925                         mode_info->bios_connector[0].valid = true;
 926                         mode_info->bios_connector[0].connector_type = CONNECTOR_DVI_I;
 927                         mode_info->bios_connector[0].dac_type = DAC_PRIMARY;
 928                         mode_info->bios_connector[0].tmds_type = TMDS_INT;
 929                         mode_info->bios_connector[0].ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
 930                 } else {
 931                         DRM_DEBUG("No connector info found\n");
 932                         return false;
 933                 }
 934         }
 935
 936         if (dev_priv->flags & RADEON_IS_MOBILITY ||
 937             dev_priv->chip_family == CHIP_RS400 ||
 938             dev_priv->chip_family == CHIP_RS480) {
 939                 uint16_t lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
 940                 if (lcd_info) {
 941                         uint16_t lcd_ddc_info = combios_get_table_offset(dev, COMBIOS_LCD_DDC_INFO_TABLE);
 942
 943                         mode_info->bios_connector[4].valid = true;
 944                         mode_info->bios_connector[4].connector_type = CONNECTOR_LVDS;
 945                         mode_info->bios_connector[4].dac_type = DAC_NONE;
 946                         mode_info->bios_connector[4].tmds_type = TMDS_NONE;
 947                         mode_info->bios_connector[4].ddc_i2c.valid = false;
 948
 949                         if (lcd_ddc_info) {
 950                                 ddc_type = radeon_bios8(dev_priv, lcd_ddc_info + 2);
 951                                 switch(ddc_type) {
 952                                 case DDC_MONID:
 953                                         mode_info->bios_connector[4].ddc_i2c =
 954                                                 combios_setup_i2c_bus(RADEON_GPIO_MONID);
 955                                         break;
 956                                 case DDC_DVI:
 957                                         mode_info->bios_connector[4].ddc_i2c =
 958                                                 combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
 959                                         break;
 960                                 case DDC_VGA:
 961                                         mode_info->bios_connector[4].ddc_i2c =
 962                                                 combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
 963                                         break;
 964                                 case DDC_CRT2:
 965                                         mode_info->bios_connector[4].ddc_i2c =
 966                                                 combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
 967                                         break;
 968                                 case DDC_LCD:
 969                                         mode_info->bios_connector[4].ddc_i2c =
 970                                                 combios_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
 971                                         mode_info->bios_connector[4].ddc_i2c.mask_clk_mask =
 972                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
 973                                         mode_info->bios_connector[4].ddc_i2c.mask_data_mask =
 974                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
 975                                         mode_info->bios_connector[4].ddc_i2c.a_clk_mask =
 976                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
 977                                         mode_info->bios_connector[4].ddc_i2c.a_data_mask =
 978                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
 979                                         mode_info->bios_connector[4].ddc_i2c.put_clk_mask =
 980                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
 981                                         mode_info->bios_connector[4].ddc_i2c.put_data_mask =
 982                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
 983                                         mode_info->bios_connector[4].ddc_i2c.get_clk_mask =
 984                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
 985                                         mode_info->bios_connector[4].ddc_i2c.get_data_mask =
 986                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
 987                                         break;
 988                                 case DDC_GPIO:
 989                                         mode_info->bios_connector[4].ddc_i2c =
 990                                                 combios_setup_i2c_bus(RADEON_MDGPIO_EN_REG);
 991                                         mode_info->bios_connector[4].ddc_i2c.mask_clk_mask =
 992                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
 993                                         mode_info->bios_connector[4].ddc_i2c.mask_data_mask =
 994                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
 995                                         mode_info->bios_connector[4].ddc_i2c.a_clk_mask =
 996                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
 997                                         mode_info->bios_connector[4].ddc_i2c.a_data_mask =
 998                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
 999                                         mode_info->bios_connector[4].ddc_i2c.put_clk_mask =
1000                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
1001                                         mode_info->bios_connector[4].ddc_i2c.put_data_mask =
1002                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
1003                                         mode_info->bios_connector[4].ddc_i2c.get_clk_mask =
1004                                                 radeon_bios32(dev_priv, lcd_ddc_info + 3);
1005                                         mode_info->bios_connector[4].ddc_i2c.get_data_mask =
1006                                                 radeon_bios32(dev_priv, lcd_ddc_info + 7);
1007                                         break;
1008                                 default:
1009                                         break;
1010                                 }
1011                                 DRM_DEBUG("LCD DDC Info Table found!\n");
1012                         }
1013                 } else
1014                         mode_info->bios_connector[4].ddc_i2c.valid = false;
1015         }
1016
1017         /* check TV table */
1018         if (dev_priv->chip_family != CHIP_R100 &&
1019             dev_priv->chip_family != CHIP_R200) {
1020                 uint32_t tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1021                 if (tv_info) {
1022                         if (radeon_bios8(dev_priv, tv_info + 6) == 'T') {
1023                                 mode_info->bios_connector[5].valid = true;
1024                                 mode_info->bios_connector[5].connector_type = CONNECTOR_DIN;
1025                                 mode_info->bios_connector[5].dac_type = DAC_TVDAC;
1026                                 mode_info->bios_connector[5].tmds_type = TMDS_NONE;
1027                                 mode_info->bios_connector[5].ddc_i2c.valid = false;
1028                         }
1029                 }
1030         }
1031
1032
1033         DRM_DEBUG("BIOS Connector table\n");
1034         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
1035                 if (!mode_info->bios_connector[i].valid)
1036                         continue;
1037
1038                 DRM_DEBUG("Port %d: ddc_type 0x%x, dac_type %d, tmds_type %d, connector type %d, hpd_mask %d\n",
1039                           i, mode_info->bios_connector[i].ddc_i2c.mask_clk_reg,
1040                           mode_info->bios_connector[i].dac_type,
1041                           mode_info->bios_connector[i].tmds_type,
1042                           mode_info->bios_connector[i].connector_type,
1043                           mode_info->bios_connector[i].hpd_mask);
1044         }
1045
1046         return true;
1047 }
1048
1049 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
1050 {
1051         struct drm_radeon_private *dev_priv = dev->dev_private;
1052
1053         if (offset) {
1054                 while (radeon_bios16(dev_priv, offset)) {
1055                         uint16_t cmd  = ((radeon_bios16(dev_priv, offset) & 0xe000) >> 13);
1056                         uint32_t addr = (radeon_bios16(dev_priv, offset) & 0x1fff);
1057                         uint32_t val, and_mask, or_mask;
1058                         uint32_t tmp;
1059
1060                         offset += 2;
1061                         switch (cmd) {
1062                         case 0:
1063                                 val = radeon_bios32(dev_priv, offset);
1064                                 offset += 4;
1065                                 RADEON_WRITE(addr, val);
1066                                 break;
1067                         case 1:
1068                                 val = radeon_bios32(dev_priv, offset);
1069                                 offset += 4;
1070                                 RADEON_WRITE(addr, val);
1071                                 break;
1072                         case 2:
1073                                 and_mask = radeon_bios32(dev_priv, offset);
1074                                 offset += 4;
1075                                 or_mask = radeon_bios32(dev_priv, offset);
1076                                 offset += 4;
1077                                 tmp = RADEON_READ(addr);
1078                                 tmp &= and_mask;
1079                                 tmp |= or_mask;
1080                                 RADEON_WRITE(addr, tmp);
1081                                 break;
1082                         case 3:
1083                                 and_mask = radeon_bios32(dev_priv, offset);
1084                                 offset += 4;
1085                                 or_mask = radeon_bios32(dev_priv, offset);
1086                                 offset += 4;
1087                                 tmp = RADEON_READ(addr);
1088                                 tmp &= and_mask;
1089                                 tmp |= or_mask;
1090                                 RADEON_WRITE(addr, tmp);
1091                                 break;
1092                         case 4:
1093                                 val = radeon_bios16(dev_priv, offset);
1094                                 offset += 2;
1095                                 udelay(val);
1096                                 break;
1097                         case 5:
1098                                 val = radeon_bios16(dev_priv, offset);
1099                                 offset += 2;
1100                                 switch (addr) {
1101                                 case 8:
1102                                         while (val--) {
1103                                                 if (!(RADEON_READ_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL) &
1104                                                       RADEON_MC_BUSY))
1105                                                         break;
1106                                         }
1107                                         break;
1108                                 case 9:
1109                                         while (val--) {
1110                                                 if ((RADEON_READ(RADEON_MC_STATUS) &
1111                                                       RADEON_MC_IDLE))
1112                                                         break;
1113                                         }
1114                                         break;
1115                                 default:
1116                                         break;
1117                                 }
1118                                 break;
1119                         default:
1120                                 break;
1121                         }
1122                 }
1123         }
1124 }
1125
1126 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
1127 {
1128         struct drm_radeon_private *dev_priv = dev->dev_private;
1129
1130         if (offset) {
1131                 while (radeon_bios8(dev_priv, offset)) {
1132                         uint8_t cmd  = ((radeon_bios8(dev_priv, offset) & 0xc0) >> 6);
1133                         uint8_t addr = (radeon_bios8(dev_priv, offset) & 0x3f);
1134                         uint32_t val, shift, tmp;
1135                         uint32_t and_mask, or_mask;
1136
1137                         offset++;
1138                         switch (cmd) {
1139                         case 0:
1140                                 val = radeon_bios32(dev_priv, offset);
1141                                 offset += 4;
1142                                 RADEON_WRITE_PLL(dev_priv, addr, val);
1143                                 break;
1144                         case 1:
1145                                 shift = radeon_bios8(dev_priv, offset) * 8;
1146                                 offset++;
1147                                 and_mask = radeon_bios8(dev_priv, offset) << shift;
1148                                 and_mask |= ~(0xff << shift);
1149                                 offset++;
1150                                 or_mask = radeon_bios8(dev_priv, offset) << shift;
1151                                 offset++;
1152                                 tmp = RADEON_READ_PLL(dev_priv, addr);
1153                                 tmp &= and_mask;
1154                                 tmp |= or_mask;
1155                                 RADEON_WRITE_PLL(dev_priv, addr, tmp);
1156                                 break;
1157                         case 2:
1158                         case 3:
1159                                 tmp = 1000;
1160                                 switch (addr) {
1161                                 case 1:
1162                                         udelay(150);
1163                                         break;
1164                                 case 2:
1165                                         udelay(1000);
1166                                         break;
1167                                 case 3:
1168                                         while (tmp--) {
1169                                                 if (!(RADEON_READ_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL) &
1170                                                       RADEON_MC_BUSY))
1171                                                         break;
1172                                         }
1173                                         break;
1174                                 case 4:
1175                                         while (tmp--) {
1176                                                 if (RADEON_READ_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL) &
1177                                                     RADEON_DLL_READY)
1178                                                         break;
1179                                         }
1180                                         break;
1181                                 case 5:
1182                                         tmp = RADEON_READ_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL);
1183                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
1184 #if 0
1185                                                 uint32_t mclk_cntl = RADEON_READ_PLL(RADEON_MCLK_CNTL);
1186                                                 mclk_cntl &= 0xffff0000;
1187                                                 //mclk_cntl |= 0x00001111; /* ??? */
1188                                                 RADEON_WRITE_PLL(dev_priv, RADEON_MCLK_CNTL, mclk_cntl);
1189                                                 udelay(10000);
1190 #endif
1191                                                 RADEON_WRITE_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL,
1192                                                                  tmp & ~RADEON_CG_NO1_DEBUG_0);
1193                                                 udelay(10000);
1194                                         }
1195                                         break;
1196                                 default:
1197                                         break;
1198                                 }
1199                                 break;
1200                         default:
1201                                 break;
1202                         }
1203                 }
1204         }
1205 }
1206
1207 static void combios_parse_ram_reset_table(struct drm_device *dev, uint16_t offset)
1208 {
1209         struct drm_radeon_private *dev_priv = dev->dev_private;
1210         uint32_t tmp;
1211
1212         if (offset) {
1213                 uint8_t val = radeon_bios8(dev_priv, offset);
1214                 while (val != 0xff) {
1215                         offset++;
1216
1217                         if (val == 0x0f) {
1218                                 uint32_t channel_complete_mask;
1219
1220                                 if (radeon_is_r300(dev_priv))
1221                                         channel_complete_mask = R300_MEM_PWRUP_COMPLETE;
1222                                 else
1223                                         channel_complete_mask = RADEON_MEM_PWRUP_COMPLETE;
1224                                 tmp = 20000;
1225                                 while (tmp--) {
1226                                         if ((RADEON_READ(RADEON_MEM_STR_CNTL) &
1227                                              channel_complete_mask) ==
1228                                             channel_complete_mask)
1229                                                 break;
1230                                 }
1231                         } else {
1232                                 uint32_t or_mask = radeon_bios16(dev_priv, offset);
1233                                 offset += 2;
1234
1235                                 tmp = RADEON_READ(RADEON_MEM_SDRAM_MODE_REG);
1236                                 tmp &= RADEON_SDRAM_MODE_MASK;
1237                                 tmp |= or_mask;
1238                                 RADEON_WRITE(RADEON_MEM_SDRAM_MODE_REG, tmp);
1239
1240                                 or_mask = val << 24;
1241                                 tmp = RADEON_READ(RADEON_MEM_SDRAM_MODE_REG);
1242                                 tmp &= RADEON_B3MEM_RESET_MASK;
1243                                 tmp |= or_mask;
1244                                 RADEON_WRITE(RADEON_MEM_SDRAM_MODE_REG, tmp);
1245                         }
1246                         val = radeon_bios8(dev_priv, offset);
1247                 }
1248         }
1249 }
1250
1251 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
1252 {
1253         uint16_t dyn_clk_info = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
1254
1255         if (dyn_clk_info)
1256                 combios_parse_pll_table(dev, dyn_clk_info);
1257 }
1258
1259 void radeon_combios_asic_init(struct drm_device *dev)
1260 {
1261         uint16_t table;
1262
1263         /* ASIC INIT 1 */
1264         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
1265         if (table)
1266                 combios_parse_mmio_table(dev, table);
1267
1268         /* PLL INIT */
1269         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
1270         if (table)
1271                 combios_parse_pll_table(dev, table);
1272
1273         /* ASIC INIT 2 */
1274         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
1275         if (table)
1276                 combios_parse_mmio_table(dev, table);
1277
1278         /* ASIC INIT 4 */
1279         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
1280         if (table)
1281                 combios_parse_mmio_table(dev, table);
1282
1283         /* RAM RESET */
1284         table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
1285         if (table)
1286                 combios_parse_ram_reset_table(dev, table);
1287
1288         /* ASIC INIT 3 */
1289         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
1290         if (table)
1291                 combios_parse_mmio_table(dev, table);
1292
1293         /* DYN CLK 1 */
1294         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
1295         if (table)
1296                 combios_parse_pll_table(dev, table);
1297
1298         /* ASIC INIT 5 */
1299         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_5_TABLE);
1300         if (table)
1301                 combios_parse_mmio_table(dev, table);
1302
1303 }
1304
1305 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
1306 {
1307         struct drm_radeon_private *dev_priv = dev->dev_private;
1308         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
1309
1310         bios_0_scratch = RADEON_READ(RADEON_BIOS_0_SCRATCH);
1311         bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
1312         //bios_7_scratch = RADEON_READ(RADEON_BIOS_7_SCRATCH);
1313
1314         /* let the bios control the backlight */
1315         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
1316
1317         /* tell the bios not to handle mode switching */
1318         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
1319                                  RADEON_ACC_MODE_CHANGE);
1320
1321         /* tell the bios a driver is loaded */
1322         //bios_7_scratch |= RADEON_DRV_LOADED;
1323
1324         RADEON_WRITE(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1325         RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1326         //RADEON_WRITE(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
1327 }
1328
1329 void
1330 radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
1331 {
1332         struct drm_device *dev = encoder->dev;
1333         struct drm_radeon_private *dev_priv = dev->dev_private;
1334         uint32_t bios_6_scratch;
1335
1336         bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
1337
1338         if (lock)
1339                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
1340         else
1341                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
1342
1343         RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1344 }