linux-core/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon_drv.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33
  34 union atom_supported_devices {
  35   struct _ATOM_SUPPORTED_DEVICES_INFO info;
  36   struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  37   struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  38 };
  39
  40 static inline struct radeon_i2c_bus_rec radeon_lookup_gpio_for_ddc(struct drm_device *dev, uint8_t id)
  41 {
  42         struct drm_radeon_private *dev_priv = dev->dev_private;
  43         struct atom_context *ctx = dev_priv->mode_info.atom_context;
  44         ATOM_GPIO_I2C_ASSIGMENT gpio;
  45         struct radeon_i2c_bus_rec i2c;
  46         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  47         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  48         uint16_t data_offset;
  49
  50         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  51         i2c.valid = false;
  52
  53         atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
  54
  55         i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  56
  57         gpio = i2c_info->asGPIO_Info[id];
  58
  59         i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
  60         i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
  61         i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
  62         i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
  63         i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
  64         i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
  65         i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
  66         i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
  67         i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
  68         i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
  69         i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
  70         i2c.put_data_mask = (1 << gpio.ucDataEnShift);
  71         i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
  72         i2c.get_data_mask = (1 <<  gpio.ucDataY_Shift);
  73         i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
  74         i2c.a_data_mask = (1 <<  gpio.ucDataA_Shift);
  75         i2c.valid = true;
  76
  77         return i2c;
  78 }
  79
  80 static void radeon_atom_apply_quirks(struct drm_device *dev, int index)
  81 {
  82         struct drm_radeon_private *dev_priv = dev->dev_private;
  83         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
  84
  85         if ((dev->pdev->device == 0x791e) &&
  86             (dev->pdev->subsystem_vendor == 0x1043) &&
  87             (dev->pdev->subsystem_device == 0x826d)) {
  88                 if ((mode_info->bios_connector[index].connector_type == CONNECTOR_HDMI_TYPE_A) &&
  89                     (mode_info->bios_connector[index].tmds_type == TMDS_LVTMA)) {
  90                         mode_info->bios_connector[index].connector_type = CONNECTOR_DVI_D;
  91                 }
  92         }
  93
  94         if ((dev->pdev->device == 0x5653) &&
  95             (dev->pdev->subsystem_vendor == 0x1462) &&
  96             (dev->pdev->subsystem_device == 0x0291)) {
  97                 if (mode_info->bios_connector[index].connector_type == CONNECTOR_LVDS) {
  98                         mode_info->bios_connector[index].ddc_i2c.valid = false;
  99                 }
 100         }
 101 }
 102
 103 bool radeon_get_atom_connector_info_from_bios_connector_table(struct drm_device *dev)
 104 {
 105         struct drm_radeon_private *dev_priv = dev->dev_private;
 106         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 107         struct atom_context *ctx = mode_info->atom_context;
 108         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 109         uint16_t size, data_offset;
 110         uint8_t frev, crev;
 111         uint16_t device_support;
 112
 113         union atom_supported_devices *supported_devices;
 114         int i,j;
 115         atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
 116
 117         supported_devices = (union atom_supported_devices *)(ctx->bios + data_offset);
 118
 119         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 120
 121         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
 122
 123                 ATOM_CONNECTOR_INFO_I2C ci = supported_devices->info.asConnInfo[i];
 124
 125                 if (!(device_support & (1 << i))) {
 126                         mode_info->bios_connector[i].valid = false;
 127                         continue;
 128                 }
 129
 130                 if (i == ATOM_DEVICE_CV_INDEX) {
 131                         DRM_DEBUG("Skipping Component Video\n");
 132                         mode_info->bios_connector[i].valid = false;
 133                         continue;
 134                 }
 135
 136                 if (i == ATOM_DEVICE_TV1_INDEX) {
 137                         DRM_DEBUG("Skipping TV Out\n");
 138                         mode_info->bios_connector[i].valid = false;
 139                         continue;
 140                 }
 141
 142                 mode_info->bios_connector[i].valid = true;
 143                 mode_info->bios_connector[i].output_id = ci.sucI2cId.sbfAccess.bfI2C_LineMux;
 144                 mode_info->bios_connector[i].devices = 1 << i;
 145                 mode_info->bios_connector[i].connector_type = ci.sucConnectorInfo.sbfAccess.bfConnectorType;
 146
 147                 if (mode_info->bios_connector[i].connector_type == CONNECTOR_NONE) {
 148                         mode_info->bios_connector[i].valid = false;
 149                         continue;
 150                 }
 151
 152                 mode_info->bios_connector[i].dac_type = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 153
 154                 if ((i == ATOM_DEVICE_TV1_INDEX) ||
 155                     (i == ATOM_DEVICE_TV2_INDEX) ||
 156                     (i == ATOM_DEVICE_TV1_INDEX))
 157                         mode_info->bios_connector[i].ddc_i2c.valid = false;
 158                 else if ((dev_priv->chip_family == CHIP_RS600) ||
 159                          (dev_priv->chip_family == CHIP_RS690) ||
 160                          (dev_priv->chip_family == CHIP_RS740)) {
 161                         if ((i == ATOM_DEVICE_DFP2_INDEX) || (i == ATOM_DEVICE_DFP3_INDEX))
 162                                 mode_info->bios_connector[i].ddc_i2c =
 163                                         radeon_lookup_gpio_for_ddc(dev, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1);
 164                         else
 165                                 mode_info->bios_connector[i].ddc_i2c =
 166                                         radeon_lookup_gpio_for_ddc(dev, ci.sucI2cId.sbfAccess.bfI2C_LineMux);
 167                 } else
 168                         mode_info->bios_connector[i].ddc_i2c =
 169                                 radeon_lookup_gpio_for_ddc(dev, ci.sucI2cId.sbfAccess.bfI2C_LineMux);
 170
 171                 if (i == ATOM_DEVICE_DFP1_INDEX)
 172                         mode_info->bios_connector[i].tmds_type = TMDS_INT;
 173                 else if (i == ATOM_DEVICE_DFP2_INDEX) {
 174                         if ((dev_priv->chip_family == CHIP_RS600) ||
 175                             (dev_priv->chip_family == CHIP_RS690) ||
 176                             (dev_priv->chip_family == CHIP_RS740))
 177                                 mode_info->bios_connector[i].tmds_type = TMDS_DDIA;
 178                         else
 179                                 mode_info->bios_connector[i].tmds_type = TMDS_EXT;
 180                 } else if (i == ATOM_DEVICE_DFP3_INDEX)
 181                         mode_info->bios_connector[i].tmds_type = TMDS_LVTMA;
 182                 else
 183                         mode_info->bios_connector[i].tmds_type = TMDS_NONE;
 184
 185                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 186                  * shared with a DVI port, we'll pick up the DVI connector below when we
 187                  * merge the outputs
 188                  */
 189                 if ((i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) &&
 190                     (mode_info->bios_connector[i].connector_type == CONNECTOR_DVI_I ||
 191                      mode_info->bios_connector[i].connector_type == CONNECTOR_DVI_D ||
 192                      mode_info->bios_connector[i].connector_type == CONNECTOR_DVI_A)) {
 193                         mode_info->bios_connector[i].connector_type = CONNECTOR_VGA;
 194                 }
 195
 196                 if (crev > 1) {
 197                         ATOM_CONNECTOR_INC_SRC_BITMAP isb = supported_devices->info_2.asIntSrcInfo[i];
 198
 199                         switch(isb.ucIntSrcBitmap) {
 200                         case 0x4:
 201                                 mode_info->bios_connector[i].hpd_mask = 0x1;
 202                                 break;
 203                         case 0xa:
 204                                 mode_info->bios_connector[i].hpd_mask = 0x100;
 205                                 break;
 206                         default:
 207                                 mode_info->bios_connector[i].hpd_mask = 0;
 208                                 break;
 209                         }
 210                 } else {
 211                         mode_info->bios_connector[i].hpd_mask = 0;
 212                 }
 213
 214                 radeon_atom_apply_quirks(dev, i);
 215         }
 216
 217         /* CRTs/DFPs may share a port */
 218         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
 219                 if (!mode_info->bios_connector[i].valid)
 220                         continue;
 221
 222                 for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
 223                         if (mode_info->bios_connector[j].valid && (i != j)) {
 224                                 if (mode_info->bios_connector[i].output_id ==
 225                                     mode_info->bios_connector[j].output_id) {
 226                                         if (((i == ATOM_DEVICE_DFP1_INDEX) ||
 227                                              (i == ATOM_DEVICE_DFP2_INDEX) ||
 228                                              (i == ATOM_DEVICE_DFP3_INDEX)) &&
 229                                             ((j == ATOM_DEVICE_CRT1_INDEX) ||
 230                                              (j == ATOM_DEVICE_CRT2_INDEX))) {
 231                                                 mode_info->bios_connector[i].dac_type = mode_info->bios_connector[j].dac_type;
 232                                                 mode_info->bios_connector[i].devices |= mode_info->bios_connector[j].devices;
 233                                                 mode_info->bios_connector[i].hpd_mask = mode_info->bios_connector[j].hpd_mask;
 234                                                 mode_info->bios_connector[j].valid = false;
 235                                         } else if (((j == ATOM_DEVICE_DFP1_INDEX) ||
 236                                                     (j == ATOM_DEVICE_DFP2_INDEX) ||
 237                                                     (j == ATOM_DEVICE_DFP3_INDEX)) &&
 238                                                    ((i == ATOM_DEVICE_CRT1_INDEX) ||
 239                                                     (i == ATOM_DEVICE_CRT2_INDEX))) {
 240                                                 mode_info->bios_connector[j].dac_type = mode_info->bios_connector[i].dac_type;
 241                                                 mode_info->bios_connector[j].devices |= mode_info->bios_connector[i].devices;
 242                                                 mode_info->bios_connector[j].hpd_mask = mode_info->bios_connector[i].hpd_mask;
 243                                                 mode_info->bios_connector[i].valid = false;
 244                                         }
 245                                 }
 246                         }
 247                 }
 248         }
 249
 250
 251         DRM_DEBUG("BIOS Connector table\n");
 252         for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
 253                 if (!mode_info->bios_connector[i].valid)
 254                         continue;
 255
 256                 DRM_DEBUG("Port %d: ddc_type 0x%x, dac_type %d, tmds_type %d, connector type %d, hpd_mask %d\n",
 257                           i, mode_info->bios_connector[i].ddc_i2c.mask_clk_reg,
 258                           mode_info->bios_connector[i].dac_type,
 259                           mode_info->bios_connector[i].tmds_type,
 260                           mode_info->bios_connector[i].connector_type,
 261                           mode_info->bios_connector[i].hpd_mask);
 262         }
 263         return true;
 264 }
 265
 266 union firmware_info {
 267         ATOM_FIRMWARE_INFO info;
 268         ATOM_FIRMWARE_INFO_V1_2 info_12;
 269         ATOM_FIRMWARE_INFO_V1_3 info_13;
 270         ATOM_FIRMWARE_INFO_V1_4 info_14;
 271 };
 272
 273 bool radeon_atom_get_clock_info(struct drm_device *dev)
 274 {
 275         struct drm_radeon_private *dev_priv = dev->dev_private;
 276         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 277         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 278         union firmware_info *firmware_info;
 279         uint8_t frev, crev;
 280         struct radeon_pll *pll = &mode_info->pll;
 281         uint16_t data_offset;
 282
 283         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
 284
 285         firmware_info = (union firmware_info *)(mode_info->atom_context->bios + data_offset);
 286
 287         pll->reference_freq = le16_to_cpu(firmware_info->info.usReferenceClock);
 288         pll->reference_div = 0;
 289
 290         pll->pll_out_min = le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
 291         pll->pll_out_max = le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 292
 293         if (pll->pll_out_min == 0) {
 294                 if (radeon_is_avivo(dev_priv))
 295                         pll->pll_out_min = 64800;
 296                 else
 297                         pll->pll_out_min = 20000;
 298         }
 299
 300         pll->pll_in_min = le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 301         pll->pll_in_max = le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 302
 303         pll->xclk = le16_to_cpu(firmware_info->info.usMaxPixelClock);
 304
 305         return true;
 306 }
 307
 308 union lvds_info {
 309         struct _ATOM_LVDS_INFO info;
 310         struct _ATOM_LVDS_INFO_V12 info_12;
 311 };
 312
 313 void radeon_get_lvds_info(struct radeon_encoder *encoder)
 314 {
 315         struct drm_device *dev = encoder->base.dev;
 316         struct drm_radeon_private *dev_priv = dev->dev_private;
 317         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 318         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
 319         uint16_t data_offset;
 320         union lvds_info *lvds_info;
 321         uint8_t frev, crev;
 322
 323         atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
 324
 325         lvds_info = (union lvds_info *)(mode_info->atom_context->bios + data_offset);
 326
 327         encoder->dotclock = le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
 328         encoder->panel_xres = le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
 329         encoder->panel_yres = le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
 330         encoder->hblank = le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
 331         encoder->hoverplus = le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
 332         encoder->hsync_width = le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
 333
 334         encoder->vblank = le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
 335         encoder->hoverplus = le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
 336         encoder->hsync_width = le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
 337         encoder->panel_pwr_delay = le16_to_cpu(lvds_info->info.usOffDelayInMs);
 338 }
 339
 340 void radeon_atom_dyn_clk_setup(struct drm_device *dev, int enable)
 341 {
 342         struct drm_radeon_private *dev_priv = dev->dev_private;
 343         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 344         struct atom_context *ctx = mode_info->atom_context;
 345         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
 346         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
 347
 348         args.ucEnable = enable;
 349
 350         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 351 }
 352
 353 void radeon_atom_static_pwrmgt_setup(struct drm_device *dev, int enable)
 354 {
 355         struct drm_radeon_private *dev_priv = dev->dev_private;
 356         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 357         struct atom_context *ctx = mode_info->atom_context;
 358         ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
 359         int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
 360
 361         args.ucEnable = enable;
 362
 363         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
 364 }
 365
 366 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
 367 {
 368         struct drm_radeon_private *dev_priv = dev->dev_private;
 369         uint32_t bios_2_scratch, bios_6_scratch;
 370
 371         if (dev_priv->chip_family >= CHIP_R600) {
 372                 bios_2_scratch = RADEON_READ(RADEON_BIOS_0_SCRATCH);
 373                 bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
 374         } else {
 375                 bios_2_scratch = RADEON_READ(RADEON_BIOS_0_SCRATCH);
 376                 bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
 377         }
 378
 379         /* let the bios control the backlight */
 380         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
 381
 382         /* tell the bios not to handle mode switching */
 383         bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH |
 384                            ATOM_S6_ACC_MODE);
 385
 386         if (dev_priv->chip_family >= CHIP_R600) {
 387                 RADEON_WRITE(R600_BIOS_2_SCRATCH, bios_2_scratch);
 388                 RADEON_WRITE(R600_BIOS_6_SCRATCH, bios_6_scratch);
 389         } else {
 390                 RADEON_WRITE(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
 391                 RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
 392         }
 393
 394 }
 395
 396 void
 397 radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
 398 {
 399         struct drm_device *dev = encoder->dev;
 400         struct drm_radeon_private *dev_priv = dev->dev_private;
 401         uint32_t bios_6_scratch;
 402
 403         if (dev_priv->chip_family >= CHIP_R600)
 404                 bios_6_scratch = RADEON_READ(R600_BIOS_6_SCRATCH);
 405         else
 406                 bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
 407
 408         if (lock)
 409                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
 410         else
 411                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
 412
 413         if (dev_priv->chip_family >= CHIP_R600)
 414                 RADEON_WRITE(R600_BIOS_6_SCRATCH, bios_6_scratch);
 415         else
 416                 RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
 417 }