2 * Copyright (C) 2008 Maarten Maathuis.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "nv50_output.h"
29 static int nv50_sor_validate_mode(struct nv50_output *output, struct nouveau_hw_mode *mode)
33 if (mode->clock > 165000) /* no dual link until we figure it out completely */
34 return MODE_CLOCK_HIGH;
36 if (mode->clock < 25000)
37 return MODE_CLOCK_LOW;
39 if (output->native_mode->hdisplay > 0 && output->native_mode->vdisplay > 0) {
40 if (mode->hdisplay > output->native_mode->hdisplay || mode->vdisplay > output->native_mode->vdisplay)
47 static int nv50_sor_execute_mode(struct nv50_output *output, bool disconnect)
49 struct drm_nouveau_private *dev_priv = output->dev->dev_private;
50 struct nv50_crtc *crtc = output->crtc;
51 struct nouveau_hw_mode *desired_mode = NULL;
53 uint32_t offset = nv50_output_or_offset(output) * 0x40;
55 uint32_t mode_ctl = NV50_SOR_MODE_CTRL_OFF;
57 NV50_DEBUG("or %d\n", nv50_output_or_offset(output));
60 NV50_DEBUG("Disconnecting SOR\n");
61 OUT_MODE(NV50_SOR0_MODE_CTRL + offset, mode_ctl);
65 desired_mode = (crtc->use_native_mode ? crtc->native_mode : crtc->mode);
67 if (output->type == OUTPUT_LVDS) {
68 mode_ctl |= NV50_SOR_MODE_CTRL_LVDS;
70 mode_ctl |= NV50_SOR_MODE_CTRL_TMDS;
71 if (desired_mode->clock > 165000)
72 mode_ctl |= NV50_SOR_MODE_CTRL_TMDS_DUAL_LINK;
76 mode_ctl |= NV50_SOR_MODE_CTRL_CRTC1;
78 mode_ctl |= NV50_SOR_MODE_CTRL_CRTC0;
80 if (desired_mode->flags & V_NHSYNC)
81 mode_ctl |= NV50_SOR_MODE_CTRL_NHSYNC;
83 if (desired_mode->flags & V_NVSYNC)
84 mode_ctl |= NV50_SOR_MODE_CTRL_NVSYNC;
86 OUT_MODE(NV50_SOR0_MODE_CTRL + offset, mode_ctl);
91 static int nv50_sor_set_clock_mode(struct nv50_output *output)
93 struct drm_nouveau_private *dev_priv = output->dev->dev_private;
94 struct nv50_crtc *crtc = output->crtc;
96 uint32_t limit = 165000;
97 struct nouveau_hw_mode *hw_mode;
99 NV50_DEBUG("or %d\n", nv50_output_or_offset(output));
101 /* We don't yet know what to do, if anything at all. */
102 if (output->type == OUTPUT_LVDS)
105 if (crtc->use_native_mode)
106 hw_mode = crtc->native_mode;
108 hw_mode = crtc->mode;
110 /* 0x70000 was a late addition to nv, mentioned as fixing tmds initialisation on certain gpu's. */
111 /* I presume it's some kind of clock setting, but what precisely i do not know. */
112 NV_WRITE(NV50_PDISPLAY_SOR_CLK_CLK_CTRL2(nv50_output_or_offset(output)), 0x70000 | ((hw_mode->clock > limit) ? 0x101 : 0));
117 static int nv50_sor_set_power_mode(struct nv50_output *output, int mode)
119 struct drm_nouveau_private *dev_priv = output->dev->dev_private;
121 int or = nv50_output_or_offset(output);
123 NV50_DEBUG("or %d\n", nv50_output_or_offset(output));
125 /* wait for it to be done */
126 while (NV_READ(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or)) & NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING);
128 val = NV_READ(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or));
130 if (mode == DPMSModeOn)
131 val |= NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_ON;
133 val &= ~NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_ON;
135 NV_WRITE(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or), val | NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING);
140 static int nv50_sor_destroy(struct nv50_output *output)
142 struct drm_device *dev = output->dev;
143 struct drm_nouveau_private *dev_priv = dev->dev_private;
144 struct nv50_display *display = nv50_get_display(dev);
148 if (!display || !output)
151 list_del(&output->head);
153 kfree(output->native_mode);
154 if (dev_priv->free_output)
155 dev_priv->free_output(output);
160 int nv50_sor_create(struct drm_device *dev, int dcb_entry)
162 struct drm_nouveau_private *dev_priv = dev->dev_private;
163 struct nv50_output *output = NULL;
164 struct nv50_display *display = NULL;
165 struct dcb_entry *entry = NULL;
170 /* This allows the public layer to do it's thing. */
171 if (dev_priv->alloc_output)
172 output = dev_priv->alloc_output(dev);
179 display = nv50_get_display(dev);
185 entry = &dev_priv->dcb_table.entry[dcb_entry];
191 switch (entry->type) {
192 case DCB_OUTPUT_TMDS:
193 output->type = OUTPUT_TMDS;
194 DRM_INFO("Detected a TMDS output\n");
196 case DCB_OUTPUT_LVDS:
197 output->type = OUTPUT_LVDS;
198 DRM_INFO("Detected a LVDS output\n");
205 output->dcb_entry = dcb_entry;
206 output->bus = entry->bus;
208 list_add_tail(&output->head, &display->outputs);
210 output->native_mode = kzalloc(sizeof(struct nouveau_hw_mode), GFP_KERNEL);
211 if (!output->native_mode) {
216 /* Set function pointers. */
217 output->validate_mode = nv50_sor_validate_mode;
218 output->execute_mode = nv50_sor_execute_mode;
219 output->set_clock_mode = nv50_sor_set_clock_mode;
220 output->set_power_mode = nv50_sor_set_power_mode;
221 output->detect = NULL;
222 output->destroy = nv50_sor_destroy;
224 /* Some default state, unknown what it precisely means. */
225 if (output->type == OUTPUT_TMDS) {
226 NV_WRITE(NV50_PDISPLAY_SOR_REGS_UNK_00C(nv50_output_or_offset(output)), 0x03010700);
227 NV_WRITE(NV50_PDISPLAY_SOR_REGS_UNK_010(nv50_output_or_offset(output)), 0x0000152f);
228 NV_WRITE(NV50_PDISPLAY_SOR_REGS_UNK_014(nv50_output_or_offset(output)), 0x00000000);
229 NV_WRITE(NV50_PDISPLAY_SOR_REGS_UNK_018(nv50_output_or_offset(output)), 0x00245af8);
235 if (output->native_mode)
236 kfree(output->native_mode);
237 if (dev_priv->free_output)
238 dev_priv->free_output(output);