linux-core/nv50_display_commands.h

   1 /*
   2  * Copyright (C) 2008 Maarten Maathuis.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 /* copied from ddx definitions, until rules-ng can handle this */
  28
  29 #define NV50_UPDATE_DISPLAY             0x80
  30 #define NV50_UNK84                              0x84
  31 #define NV50_UNK88                              0x88
  32
  33 #define NV50_DAC0_MODE_CTRL             0x400
  34         #define NV50_DAC_MODE_CTRL_OFF                  (0 << 0)
  35         #define NV50_DAC_MODE_CTRL_CRTC0                        (1 << 0)
  36         #define NV50_DAC_MODE_CTRL_CRTC1                        (1 << 1)
  37 #define NV50_DAC1_MODE_CTRL             0x480
  38 #define NV50_DAC2_MODE_CTRL             0x500
  39
  40 #define NV50_DAC0_MODE_CTRL2            0x404
  41         #define NV50_DAC_MODE_CTRL2_NHSYNC                      (1 << 0)
  42         #define NV50_DAC_MODE_CTRL2_NVSYNC                      (2 << 0)
  43 #define NV50_DAC1_MODE_CTRL2            0x484
  44 #define NV50_DAC2_MODE_CTRL2            0x504
  45
  46 #define NV50_SOR0_MODE_CTRL             0x600
  47         #define NV50_SOR_MODE_CTRL_OFF                  (0 << 0)
  48         #define NV50_SOR_MODE_CTRL_CRTC0                        (1 << 0)
  49         #define NV50_SOR_MODE_CTRL_CRTC1                        (1 << 1)
  50         #define NV50_SOR_MODE_CTRL_LVDS                 (0 << 8)
  51         #define NV50_SOR_MODE_CTRL_TMDS                 (1 << 8)
  52         #define NV50_SOR_MODE_CTRL_TMDS_DUAL_LINK       (4 << 8)
  53         #define NV50_SOR_MODE_CTRL_NHSYNC                       (1 << 12)
  54         #define NV50_SOR_MODE_CTRL_NVSYNC                       (2 << 12)
  55 #define NV50_SOR1_MODE_CTRL             0x640
  56
  57 #define NV50_CRTC0_UNK800                       0x800
  58 #define NV50_CRTC0_CLOCK                        0x804
  59 #define NV50_CRTC0_INTERLACE            0x808
  60
  61 /* 0x810 is a reasonable guess, nothing more. */
  62 #define NV50_CRTC0_DISPLAY_START                                0x810
  63 #define NV50_CRTC0_DISPLAY_TOTAL                                0x814
  64 #define NV50_CRTC0_SYNC_DURATION                                0x818
  65 #define NV50_CRTC0_SYNC_START_TO_BLANK_END              0x81C
  66 #define NV50_CRTC0_MODE_UNK1                                    0x820
  67 #define NV50_CRTC0_MODE_UNK2                                    0x824
  68
  69 #define NV50_CRTC0_UNK82C                                               0x82C
  70
  71 /* You can't have a palette in 8 bit mode (=OFF) */
  72 #define NV50_CRTC0_CLUT_MODE            0x840
  73         #define NV50_CRTC0_CLUT_MODE_BLANK              0x00000000
  74         #define NV50_CRTC0_CLUT_MODE_OFF                0x80000000
  75         #define NV50_CRTC0_CLUT_MODE_ON         0xC0000000
  76 #define NV50_CRTC0_CLUT_OFFSET          0x844
  77
  78 /* Anyone know what part of the chip is triggered here precisely? */
  79 #define NV84_CRTC0_BLANK_UNK1           0x85C
  80         #define NV84_CRTC0_BLANK_UNK1_BLANK     0x0
  81         #define NV84_CRTC0_BLANK_UNK1_UNBLANK   0x1
  82
  83 #define NV50_CRTC0_FB_OFFSET            0x860
  84
  85 #define NV50_CRTC0_FB_SIZE                      0x868
  86 #define NV50_CRTC0_FB_PITCH             0x86C
  87
  88 #define NV50_CRTC0_DEPTH                        0x870
  89         #define NV50_CRTC0_DEPTH_8BPP           0x1E00
  90         #define NV50_CRTC0_DEPTH_15BPP  0xE900
  91         #define NV50_CRTC0_DEPTH_16BPP  0xE800
  92         #define NV50_CRTC0_DEPTH_24BPP  0xCF00
  93
  94 /* I'm openminded to better interpretations. */
  95 /* This is an educated guess. */
  96 /* NV50 has RAMDAC and TMDS offchip, so it's unlikely to be that. */
  97 #define NV50_CRTC0_BLANK_CTRL           0x874
  98         #define NV50_CRTC0_BLANK_CTRL_BLANK     0x0
  99         #define NV50_CRTC0_BLANK_CTRL_UNBLANK   0x1
 100
 101 #define NV50_CRTC0_CURSOR_CTRL  0x880
 102         #define NV50_CRTC0_CURSOR_CTRL_SHOW     0x85000000
 103         #define NV50_CRTC0_CURSOR_CTRL_HIDE     0x05000000
 104
 105 #define NV50_CRTC0_CURSOR_OFFSET        0x884
 106
 107 /* Anyone know what part of the chip is triggered here precisely? */
 108 #define NV84_CRTC0_BLANK_UNK2           0x89C
 109         #define NV84_CRTC0_BLANK_UNK2_BLANK     0x0
 110         #define NV84_CRTC0_BLANK_UNK2_UNBLANK   0x1
 111
 112 #define NV50_CRTC0_DITHERING_CTRL       0x8A0
 113         #define NV50_CRTC0_DITHERING_CTRL_ON    0x11
 114         #define NV50_CRTC0_DITHERING_CTRL_OFF   0x0
 115
 116 #define NV50_CRTC0_SCALE_CTRL           0x8A4
 117         #define NV50_CRTC0_SCALE_CTRL_SCALER_INACTIVE   (0 << 0)
 118         /* It doesn't seem to be needed, hence i wonder what it does precisely. */
 119         #define NV50_CRTC0_SCALE_CTRL_SCALER_ACTIVE     (9 << 0)
 120 #define NV50_CRTC0_COLOR_CTRL           0x8A8
 121         #define NV50_CRTC_COLOR_CTRL_MODE_COLOR         (4 << 16)
 122
 123 #define NV50_CRTC0_FB_POS                       0x8C0
 124 #define NV50_CRTC0_REAL_RES             0x8C8
 125
 126 /* Added a macro, because the signed stuff can cause you problems very quickly. */
 127 #define NV50_CRTC0_SCALE_CENTER_OFFSET          0x8D4
 128         #define NV50_CRTC_SCALE_CENTER_OFFSET_VAL(x, y) ((((unsigned)y << 16) & 0xFFFF0000) | (((unsigned)x) & 0x0000FFFF))
 129 /* Both of these are needed, otherwise nothing happens. */
 130 #define NV50_CRTC0_SCALE_RES1           0x8D8
 131 #define NV50_CRTC0_SCALE_RES2           0x8DC
 132
 133 #define NV50_CRTC1_UNK800                       0xC00
 134 #define NV50_CRTC1_CLOCK                        0xC04
 135 #define NV50_CRTC1_INTERLACE            0xC08
 136
 137 /* 0xC10 is a reasonable guess, nothing more. */
 138 #define NV50_CRTC1_DISPLAY_START                                0xC10
 139 #define NV50_CRTC1_DISPLAY_TOTAL                                0xC14
 140 #define NV50_CRTC1_SYNC_DURATION                                0xC18
 141 #define NV50_CRTC1_SYNC_START_TO_BLANK_END              0xC1C
 142 #define NV50_CRTC1_MODE_UNK1                                    0xC20
 143 #define NV50_CRTC1_MODE_UNK2                                    0xC24
 144
 145 #define NV50_CRTC1_CLUT_MODE            0xC40
 146         #define NV50_CRTC1_CLUT_MODE_BLANK              0x00000000
 147         #define NV50_CRTC1_CLUT_MODE_OFF                0x80000000
 148         #define NV50_CRTC1_CLUT_MODE_ON         0xC0000000
 149 #define NV50_CRTC1_CLUT_OFFSET          0xC44
 150
 151 /* Anyone know what part of the chip is triggered here precisely? */
 152 #define NV84_CRTC1_BLANK_UNK1           0xC5C
 153         #define NV84_CRTC1_BLANK_UNK1_BLANK     0x0
 154         #define NV84_CRTC1_BLANK_UNK1_UNBLANK   0x1
 155
 156 #define NV50_CRTC1_FB_OFFSET            0xC60
 157
 158 #define NV50_CRTC1_FB_SIZE                      0xC68
 159 #define NV50_CRTC1_FB_PITCH             0xC6C
 160
 161 #define NV50_CRTC1_DEPTH                        0xC70
 162         #define NV50_CRTC1_DEPTH_8BPP           0x1E00
 163         #define NV50_CRTC1_DEPTH_15BPP  0xE900
 164         #define NV50_CRTC1_DEPTH_16BPP  0xE800
 165         #define NV50_CRTC1_DEPTH_24BPP  0xCF00
 166
 167 /* I'm openminded to better interpretations. */
 168 #define NV50_CRTC1_BLANK_CTRL           0xC74
 169         #define NV50_CRTC1_BLANK_CTRL_BLANK     0x0
 170         #define NV50_CRTC1_BLANK_CTRL_UNBLANK   0x1
 171
 172 #define NV50_CRTC1_CURSOR_CTRL          0xC80
 173         #define NV50_CRTC1_CURSOR_CTRL_SHOW     0x85000000
 174         #define NV50_CRTC1_CURSOR_CTRL_HIDE     0x05000000
 175
 176 #define NV50_CRTC1_CURSOR_OFFSET        0xC84
 177
 178 /* Anyone know what part of the chip is triggered here precisely? */
 179 #define NV84_CRTC1_BLANK_UNK2           0xC9C
 180         #define NV84_CRTC1_BLANK_UNK2_BLANK     0x0
 181         #define NV84_CRTC1_BLANK_UNK2_UNBLANK   0x1
 182
 183 #define NV50_CRTC1_DITHERING_CTRL       0xCA0
 184         #define NV50_CRTC1_DITHERING_CTRL_ON    0x11
 185         #define NV50_CRTC1_DITHERING_CTRL_OFF   0x0
 186
 187 #define NV50_CRTC1_SCALE_CTRL           0xCA4
 188 #define NV50_CRTC1_COLOR_CTRL           0xCA8
 189
 190 #define NV50_CRTC1_FB_POS                       0xCC0
 191 #define NV50_CRTC1_REAL_RES             0xCC8
 192
 193 #define NV50_CRTC1_SCALE_CENTER_OFFSET          0xCD4
 194 /* Both of these are needed, otherwise nothing happens. */
 195 #define NV50_CRTC1_SCALE_RES1           0xCD8
 196 #define NV50_CRTC1_SCALE_RES2           0xCDC