linux-core/nv50_display.c

   1 /*
   2  * Copyright (C) 2008 Maarten Maathuis.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "nv50_display.h"
  28 #include "nv50_crtc.h"
  29 #include "nv50_output.h"
  30 #include "nv50_connector.h"
  31
  32 static int nv50_display_pre_init(struct nv50_display *display)
  33 {
  34         struct drm_device *dev = display->dev;
  35         struct drm_nouveau_private *dev_priv = dev->dev_private;
  36         int i;
  37         uint32_t ram_amount;
  38
  39         NV50_DEBUG("\n");
  40
  41         NV_WRITE(0x00610184, NV_READ(0x00614004));
  42         /*
  43          * I think the 0x006101XX range is some kind of main control area that enables things.
  44          */
  45         /* CRTC? */
  46         NV_WRITE(0x00610190 + 0 * 0x10, NV_READ(0x00616100 + 0 * 0x800));
  47         NV_WRITE(0x00610190 + 1 * 0x10, NV_READ(0x00616100 + 1 * 0x800));
  48         NV_WRITE(0x00610194 + 0 * 0x10, NV_READ(0x00616104 + 0 * 0x800));
  49         NV_WRITE(0x00610194 + 1 * 0x10, NV_READ(0x00616104 + 1 * 0x800));
  50         NV_WRITE(0x00610198 + 0 * 0x10, NV_READ(0x00616108 + 0 * 0x800));
  51         NV_WRITE(0x00610198 + 1 * 0x10, NV_READ(0x00616108 + 1 * 0x800));
  52         NV_WRITE(0x0061019c + 0 * 0x10, NV_READ(0x0061610c + 0 * 0x800));
  53         NV_WRITE(0x0061019c + 1 * 0x10, NV_READ(0x0061610c + 1 * 0x800));
  54         /* DAC */
  55         NV_WRITE(0x006101d0 + 0 * 0x4, NV_READ(0x0061a000 + 0 * 0x800));
  56         NV_WRITE(0x006101d0 + 1 * 0x4, NV_READ(0x0061a000 + 1 * 0x800));
  57         NV_WRITE(0x006101d0 + 2 * 0x4, NV_READ(0x0061a000 + 2 * 0x800));
  58         /* SOR */
  59         NV_WRITE(0x006101e0 + 0 * 0x4, NV_READ(0x0061c000 + 0 * 0x800));
  60         NV_WRITE(0x006101e0 + 1 * 0x4, NV_READ(0x0061c000 + 1 * 0x800));
  61         /* Something not yet in use, tv-out maybe. */
  62         NV_WRITE(0x006101f0 + 0 * 0x4, NV_READ(0x0061e000 + 0 * 0x800));
  63         NV_WRITE(0x006101f0 + 1 * 0x4, NV_READ(0x0061e000 + 1 * 0x800));
  64         NV_WRITE(0x006101f0 + 2 * 0x4, NV_READ(0x0061e000 + 2 * 0x800));
  65
  66         for (i = 0; i < 3; i++) {
  67                 NV_WRITE(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(i), 0x00550000 | NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING);
  68                 NV_WRITE(NV50_PDISPLAY_DAC_REGS_CLK_CTRL1(i), 0x00000001);
  69         }
  70
  71         /* This used to be in crtc unblank, but seems out of place there. */
  72         NV_WRITE(NV50_PDISPLAY_UNK_380, 0);
  73         /* RAM is clamped to 256 MiB. */
  74         ram_amount = nouveau_mem_fb_amount(display->dev);
  75         NV50_DEBUG("ram_amount %d\n", ram_amount);
  76         if (ram_amount > 256*1024*1024)
  77                 ram_amount = 256*1024*1024;
  78         NV_WRITE(NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1);
  79         NV_WRITE(NV50_PDISPLAY_UNK_388, 0x150000);
  80         NV_WRITE(NV50_PDISPLAY_UNK_38C, 0);
  81
  82         display->preinit_done = TRUE;
  83
  84         return 0;
  85 }
  86
  87 static int nv50_display_init(struct nv50_display *display)
  88 {
  89         struct drm_device *dev = display->dev;
  90         struct drm_nouveau_private *dev_priv = dev->dev_private;
  91         uint32_t val;
  92
  93         NV50_DEBUG("\n");
  94
  95         /* The precise purpose is unknown, i suspect it has something to do with text mode. */
  96         if (NV_READ(NV50_PDISPLAY_SUPERVISOR) & 0x100) {
  97                 NV_WRITE(NV50_PDISPLAY_SUPERVISOR, 0x100);
  98                 NV_WRITE(0x006194e8, NV_READ(0x006194e8) & ~1);
  99                 while (NV_READ(0x006194e8) & 2);
 100         }
 101
 102         /* taken from nv bug #12637 */
 103         NV_WRITE(NV50_PDISPLAY_UNK200_CTRL, 0x2b00);
 104         do {
 105                 val = NV_READ(NV50_PDISPLAY_UNK200_CTRL);
 106                 if ((val & 0x9f0000) == 0x20000)
 107                         NV_WRITE(NV50_PDISPLAY_UNK200_CTRL, val | 0x800000);
 108
 109                 if ((val & 0x3f0000) == 0x30000)
 110                         NV_WRITE(NV50_PDISPLAY_UNK200_CTRL, val | 0x200000);
 111         } while (val & 0x1e0000);
 112
 113         NV_WRITE(NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE);
 114         NV_WRITE(NV50_PDISPLAY_UNK200_CTRL, 0x1000b03);
 115         while (!(NV_READ(NV50_PDISPLAY_UNK200_CTRL) & 0x40000000));
 116
 117         /* For the moment this is just a wrapper, which should be replaced with a real fifo at some point. */
 118         OUT_MODE(NV50_UNK84, 0);
 119         OUT_MODE(NV50_UNK88, 0);
 120         OUT_MODE(NV50_CRTC0_BLANK_CTRL, NV50_CRTC0_BLANK_CTRL_BLANK);
 121         OUT_MODE(NV50_CRTC0_UNK800, 0);
 122         OUT_MODE(NV50_CRTC0_DISPLAY_START, 0);
 123         OUT_MODE(NV50_CRTC0_UNK82C, 0);
 124
 125         /* enable clock change interrupts. */
 126         NV_WRITE(NV50_PDISPLAY_SUPERVISOR_INTR, NV_READ(NV50_PDISPLAY_SUPERVISOR_INTR) | 0x70);
 127
 128         display->init_done = TRUE;
 129
 130         return 0;
 131 }
 132
 133 static int nv50_display_disable(struct nv50_display *display)
 134 {
 135         struct drm_device *dev = display->dev;
 136         struct drm_nouveau_private *dev_priv = dev->dev_private;
 137         struct nv50_crtc *crtc = NULL;
 138         int i;
 139
 140         NV50_DEBUG("\n");
 141
 142         list_for_each_entry(crtc, &display->crtcs, head) {
 143                 crtc->blank(crtc, TRUE);
 144         }
 145
 146         display->update(display);
 147
 148         /* Almost like ack'ing a vblank interrupt, maybe in the spirit of cleaning up? */
 149         list_for_each_entry(crtc, &display->crtcs, head) {
 150                 if (crtc->active) {
 151                         uint32_t mask;
 152
 153                         if (crtc->index == 1)
 154                                 mask = NV50_PDISPLAY_SUPERVISOR_CRTC1;
 155                         else
 156                                 mask = NV50_PDISPLAY_SUPERVISOR_CRTC0;
 157
 158                         NV_WRITE(NV50_PDISPLAY_SUPERVISOR, mask);
 159                         while (!(NV_READ(NV50_PDISPLAY_SUPERVISOR) & mask));
 160                 }
 161         }
 162
 163         NV_WRITE(NV50_PDISPLAY_UNK200_CTRL, 0);
 164         NV_WRITE(NV50_PDISPLAY_CTRL_STATE, 0);
 165         while ((NV_READ(NV50_PDISPLAY_UNK200_CTRL) & 0x1e0000) != 0);
 166
 167         for (i = 0; i < 2; i++) {
 168                 while (NV_READ(NV50_PDISPLAY_SOR_REGS_DPMS_STATE(i)) & NV50_PDISPLAY_SOR_REGS_DPMS_STATE_WAIT);
 169         }
 170
 171         /* disable clock change interrupts. */
 172         NV_WRITE(NV50_PDISPLAY_SUPERVISOR_INTR, NV_READ(NV50_PDISPLAY_SUPERVISOR_INTR) & ~0x70);
 173
 174         display->init_done = FALSE;
 175
 176         return 0;
 177 }
 178
 179 static int nv50_display_update(struct nv50_display *display)
 180 {
 181         struct drm_device *dev = display->dev;
 182         struct drm_nouveau_private *dev_priv = dev->dev_private;
 183
 184         NV50_DEBUG("\n");
 185
 186         OUT_MODE(NV50_UPDATE_DISPLAY, 0);
 187
 188         return 0;
 189 }
 190
 191 int nv50_display_create(struct drm_device *dev)
 192 {
 193         struct drm_nouveau_private *dev_priv = dev->dev_private;
 194         struct nv50_display *display = kzalloc(sizeof(struct nv50_display), GFP_KERNEL);
 195         int i, type, output_index, bus;
 196         /* DAC0, DAC1, DAC2, SOR0, SOR1*/
 197         int or_counter[5] = {0, 0, 0, 0, 0};
 198         int i2c_index[5] = {0, 0, 0, 0, 0};
 199         uint32_t bus_mask = 0;
 200         uint32_t bus_digital = 0, bus_analog = 0;
 201
 202         NV50_DEBUG("\n");
 203
 204         if (!display)
 205                 return -ENOMEM;
 206
 207         INIT_LIST_HEAD(&display->crtcs);
 208         INIT_LIST_HEAD(&display->outputs);
 209         INIT_LIST_HEAD(&display->connectors);
 210
 211         dev_priv->display_priv = display;
 212
 213         for (i = 0; i < 2; i++) {
 214                 nv50_crtc_create(dev, i);
 215         }
 216
 217         /* we setup the outputs up from the BIOS table */
 218         for (i = 0 ; i < dev_priv->dcb_table.entries; i++) {
 219                 type = dev_priv->dcb_table.entry[i].type;
 220                 output_index = ffs(dev_priv->dcb_table.entry[i].or) - 1;
 221                 bus = dev_priv->dcb_table.entry[i].bus;
 222
 223                 switch (type) {
 224                         case DCB_OUTPUT_TMDS:
 225                         case DCB_OUTPUT_LVDS:
 226                                 or_counter[output_index + 3] += 1;
 227                                 i2c_index[output_index + 3] = dev_priv->dcb_table.entry[i].i2c_index;
 228                                 bus_digital |= (1 << bus);
 229                                 nv50_sor_create(dev, i);
 230                                 break;
 231                         case DCB_OUTPUT_ANALOG:
 232                                 or_counter[output_index] += 1;
 233                                 i2c_index[output_index] = dev_priv->dcb_table.entry[i].i2c_index;
 234                                 bus_analog |= (1 << bus);
 235                                 nv50_dac_create(dev, i);
 236                                 break;
 237                         default:
 238                                 break;
 239                 }
 240
 241         }
 242
 243         /* setup the connectors based on the output tables. */
 244         for (i = 0 ; i < dev_priv->dcb_table.entries; i++) {
 245                 int connector_type = 0;
 246                 type = dev_priv->dcb_table.entry[i].type;
 247                 bus = dev_priv->dcb_table.entry[i].bus;
 248
 249                 /* already done? */
 250                 if (bus_mask & (1 << bus))
 251                         continue;
 252
 253                 /* only do it for supported outputs */
 254                 if (type != DCB_OUTPUT_ANALOG && type != DCB_OUTPUT_TMDS
 255                         && type != DCB_OUTPUT_LVDS)
 256                         continue;
 257
 258                 switch (type) {
 259                         case DCB_OUTPUT_TMDS:
 260                         case DCB_OUTPUT_ANALOG:
 261                                 if ((bus_digital & (1 << bus)) && (bus_analog & (1 << bus)))
 262                                         connector_type = CONNECTOR_DVI_I;
 263                                 else if (bus_digital & (1 << bus))
 264                                         connector_type = CONNECTOR_DVI_D;
 265                                 else if (bus_analog & (1 << bus))
 266                                         connector_type = CONNECTOR_VGA;
 267                                 break;
 268                         case DCB_OUTPUT_LVDS:
 269                                 connector_type = CONNECTOR_LVDS;
 270                                 break;
 271                         default:
 272                                 connector_type = CONNECTOR_UNKNOWN;
 273                                 break;
 274                 }
 275
 276                 if (connector_type == CONNECTOR_UNKNOWN)
 277                         continue;
 278
 279                 nv50_connector_create(dev, bus, dev_priv->dcb_table.entry[i].i2c_index, connector_type);
 280
 281                 bus_mask |= (1 << bus);
 282         }
 283
 284         display->dev = dev;
 285
 286         /* function pointers */
 287         display->init = nv50_display_init;
 288         display->pre_init = nv50_display_pre_init;
 289         display->disable = nv50_display_disable;
 290         display->update = nv50_display_update;
 291
 292         return 0;
 293 }
 294
 295 int nv50_display_destroy(struct drm_device *dev)
 296 {
 297         struct drm_nouveau_private *dev_priv = dev->dev_private;
 298         struct nv50_display *display = nv50_get_display(dev);
 299         struct nv50_crtc *crtc = NULL;
 300         struct nv50_output *output = NULL;
 301         struct nv50_connector *connector = NULL;
 302
 303         NV50_DEBUG("\n");
 304
 305         if (display->init_done)
 306                 display->disable(display);
 307
 308         list_for_each_entry(connector, &display->connectors, head) {
 309                 connector->destroy(connector);
 310         }
 311
 312         list_for_each_entry(output, &display->outputs, head) {
 313                 output->destroy(output);
 314         }
 315
 316         list_for_each_entry(crtc, &display->crtcs, head) {
 317                 crtc->destroy(crtc);
 318         }
 319
 320         kfree(display);
 321         dev_priv->display_priv = NULL;
 322
 323         return 0;
 324 }
 325
 326 /* This can be replaced with a real fifo in the future. */
 327 void nv50_display_command(struct drm_nouveau_private *dev_priv, uint32_t mthd, uint32_t val)
 328 {
 329         uint32_t counter = 0;
 330
 331 #if 1
 332         DRM_INFO("mthd 0x%03X val 0x%08X\n", mthd, val);
 333 #endif
 334
 335         NV_WRITE(NV50_PDISPLAY_CTRL_VAL, val);
 336         NV_WRITE(NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_PENDING | 0x10000 | mthd | NV50_PDISPLAY_CTRL_STATE_ENABLE);
 337
 338         while (NV_READ(NV50_PDISPLAY_CTRL_STATE) & NV50_PDISPLAY_CTRL_STATE_PENDING) {
 339                 counter++;
 340                 if (counter > 25000) {
 341                         DRM_ERROR("You probably need a reboot now\n");
 342                         break;
 343                 }
 344         }
 345 }
 346
 347 struct nv50_display *nv50_get_display(struct drm_device *dev)
 348 {
 349         struct drm_nouveau_private *dev_priv = dev->dev_private;
 350
 351         return (struct nv50_display *) dev_priv->display_priv;
 352 }