2 * Copyright (C) 2005-2006 Erik Waling
3 * Copyright (C) 2006 Stephane Marchesin
4 * Copyright (C) 2007-2008 Stuart Bennett
5 * Copyright (C) 2008 Maarten Maathuis.
8 * Permission is hereby granted, free of charge, to any person obtaining
9 * a copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sublicense, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial
18 * portions of the Software.
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <asm/byteorder.h>
31 #include "nouveau_bios.h"
32 #include "nouveau_drv.h"
34 /* returns true if it mismatches */
35 static bool nv_checksum(const uint8_t *data, unsigned int length)
37 /* there's a few checksums in the BIOS, so here's a generic checking function */
41 for (i = 0; i < length; i++)
50 static int nv_valid_bios(struct drm_device *dev, uint8_t *data)
52 /* check for BIOS signature */
53 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
54 DRM_ERROR("BIOS signature not found.\n");
58 if (nv_checksum(data, data[2] * 512)) {
59 DRM_ERROR("BIOS checksum invalid.\n");
66 static void nv_shadow_bios_rom(struct drm_device *dev, uint8_t *data)
68 struct drm_nouveau_private *dev_priv = dev->dev_private;
71 /* enable access to rom */
72 NV_WRITE(NV04_PBUS_PCI_NV_20, NV04_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED);
74 /* This is also valid for pre-NV50, it just happened to be the only define already present. */
75 for (i=0; i < NV50_PROM__ESIZE; i++) {
76 /* Appearantly needed for a 6600GT/6800LE bug. */
77 data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i);
78 data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i);
79 data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i);
80 data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i);
81 data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i);
84 /* disable access to rom */
85 NV_WRITE(NV04_PBUS_PCI_NV_20, NV04_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
88 static void nv_shadow_bios_ramin(struct drm_device *dev, uint8_t *data)
90 struct drm_nouveau_private *dev_priv = dev->dev_private;
91 uint32_t old_bar0_pramin = 0;
94 /* Move the bios copy to the start of ramin? */
95 if (dev_priv->card_type >= NV_50) {
96 uint32_t vbios_vram = (NV_READ(0x619f04) & ~0xff) << 8;
99 vbios_vram = (NV_READ(0x1700) << 16) + 0xf0000;
101 old_bar0_pramin = NV_READ(0x1700);
102 NV_WRITE(0x1700, vbios_vram >> 16);
105 for (i=0; i < NV50_PROM__ESIZE; i++)
106 data[i] = DRM_READ8(dev_priv->mmio, NV04_PRAMIN + i);
108 if (dev_priv->card_type >= NV_50)
109 NV_WRITE(0x1700, old_bar0_pramin);
112 static bool nv_shadow_bios(struct drm_device *dev, uint8_t *data)
114 nv_shadow_bios_rom(dev, data);
115 if (nv_valid_bios(dev, data) == 2)
118 nv_shadow_bios_ramin(dev, data);
119 if (nv_valid_bios(dev, data))
131 static int parse_bit_A_tbl_entry(struct drm_device *dev, struct bios *bios, struct bit_entry *bitentry)
133 /* Parses the load detect value table.
135 * Starting at bitentry->offset:
137 * offset + 0 (16 bits): table pointer
140 uint16_t load_table_pointer;
142 if (bitentry->length != 3) {
143 DRM_ERROR("Do not understand BIT loadval table\n");
147 load_table_pointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
149 if (load_table_pointer == 0x0) {
150 DRM_ERROR("Pointer to loadval table invalid\n");
154 /* Some kind of signature */
155 if (bios->data[load_table_pointer] != 16 || bios->data[load_table_pointer + 1] != 4 ||
156 bios->data[load_table_pointer + 2] != 4 || bios->data[load_table_pointer + 3] != 2)
159 bios->dactestval = le32_to_cpu(*((uint32_t *)&bios->data[load_table_pointer + 4])) & 0x3FF;
164 static int parse_bit_C_tbl_entry(struct drm_device *dev, struct bios *bios, struct bit_entry *bitentry)
166 /* offset + 8 (16 bits): PLL limits table pointer
168 * There's more in here, but that's unknown.
171 if (bitentry->length < 10) {
172 DRM_ERROR("Do not understand BIT C table\n");
176 bios->pll_limit_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8])));
181 static void parse_bit_structure(struct drm_device *dev, struct bios *bios, const uint16_t bitoffset)
183 int entries = bios->data[bitoffset + 4];
184 /* parse i first, I next (which needs C & M before it), and L before D */
185 char parseorder[] = "iCMILDTA";
186 struct bit_entry bitentry;
189 for (i = 0; i < sizeof(parseorder); i++) {
190 for (j = 0, offset = bitoffset + 6; j < entries; j++, offset += 6) {
191 bitentry.id[0] = bios->data[offset];
192 bitentry.id[1] = bios->data[offset + 1];
193 bitentry.length = le16_to_cpu(*((uint16_t *)&bios->data[offset + 2]));
194 bitentry.offset = le16_to_cpu(*((uint16_t *)&bios->data[offset + 4]));
196 if (bitentry.id[0] != parseorder[i])
199 switch (bitentry.id[0]) {
201 parse_bit_A_tbl_entry(dev, bios, &bitentry);
204 parse_bit_C_tbl_entry(dev, bios, &bitentry);
211 static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
215 for (i = 0; i <= (n - len); i++) {
216 for (j = 0; j < len; j++)
217 if (data[i + j] != str[j])
227 read_dcb_i2c_entry(struct drm_device *dev, uint8_t dcb_version, uint16_t i2ctabptr, int index)
229 struct drm_nouveau_private *dev_priv = dev->dev_private;
230 struct bios *bios = &dev_priv->bios;
231 uint8_t *i2ctable = &bios->data[i2ctabptr];
232 uint8_t headerlen = 0;
233 int i2c_entries = MAX_NUM_DCB_ENTRIES;
234 int recordoffset = 0, rdofs = 1, wrofs = 0;
239 if (dcb_version >= 0x30) {
240 if (i2ctable[0] != dcb_version) /* necessary? */
242 "DCB I2C table version mismatch (%02X vs %02X)\n",
243 i2ctable[0], dcb_version);
244 headerlen = i2ctable[1];
245 i2c_entries = i2ctable[2];
247 /* same address offset used for read and write for C51 and G80 */
248 if (bios->chip_version == 0x51)
250 if (i2ctable[0] >= 0x40)
253 /* it's your own fault if you call this function on a DCB 1.1 BIOS --
254 * the test below is for DCB 1.2
256 if (dcb_version < 0x14) {
264 if (index > i2c_entries) {
266 "DCB I2C index too big (%d > %d)\n",
270 if (i2ctable[headerlen + 4 * index + 3] == 0xff) {
272 "DCB I2C entry invalid\n");
276 if (bios->chip_version == 0x51) {
277 int port_type = i2ctable[headerlen + 4 * index + 3];
281 "DCB I2C table has port type %d\n", port_type);
283 if (i2ctable[0] >= 0x40) {
284 int port_type = i2ctable[headerlen + 4 * index + 3];
288 "DCB I2C table has port type %d\n", port_type);
291 dev_priv->dcb_table.i2c_read[index] = i2ctable[headerlen + recordoffset + rdofs + 4 * index];
292 dev_priv->dcb_table.i2c_write[index] = i2ctable[headerlen + recordoffset + wrofs + 4 * index];
296 parse_dcb_entry(struct drm_device *dev, int index, uint8_t dcb_version, uint16_t i2ctabptr, uint32_t conn, uint32_t conf)
298 struct drm_nouveau_private *dev_priv = dev->dev_private;
299 struct dcb_entry *entry = &dev_priv->dcb_table.entry[index];
301 memset(entry, 0, sizeof (struct dcb_entry));
303 entry->index = index;
304 /* safe defaults for a crt */
306 entry->i2c_index = 0;
309 entry->location = LOC_ON_CHIP;
311 entry->duallink_possible = false;
313 if (dcb_version >= 0x20) {
314 entry->type = conn & 0xf;
315 entry->i2c_index = (conn >> 4) & 0xf;
316 entry->heads = (conn >> 8) & 0xf;
317 entry->bus = (conn >> 16) & 0xf;
318 entry->location = (conn >> 20) & 0xf;
319 entry->or = (conn >> 24) & 0xf;
320 /* Normal entries consist of a single bit, but dual link has the
321 * adjacent more significant bit set too
323 if ((1 << (ffs(entry->or) - 1)) * 3 == entry->or)
324 entry->duallink_possible = true;
326 switch (entry->type) {
327 case DCB_OUTPUT_LVDS:
331 entry->lvdsconf.use_straps_for_mode = true;
332 if (dcb_version < 0x22) {
334 /* both 0x4 and 0x8 show up in v2.0 tables; assume they mean
335 * the same thing, which is probably wrong, but might work */
336 if (conf & 0x4 || conf & 0x8)
337 entry->lvdsconf.use_power_scripts = true;
341 entry->lvdsconf.use_power_scripts = true;
344 if (dcb_version < 0x40) { /* we know g80 cards have unknown bits */
345 DRM_ERROR("Unknown LVDS configuration bits, please report\n");
346 /* cause output setting to fail, so message is seen */
347 dev_priv->dcb_table.entries = 0;
354 /* weird type that appears on g80 mobile bios; nv driver treats it as a terminator */
357 read_dcb_i2c_entry(dev, dcb_version, i2ctabptr, entry->i2c_index);
358 } else if (dcb_version >= 0x14 ) {
359 if (conn != 0xf0003f00 && conn != 0xf2247f10 && conn != 0xf2204001 && conn != 0xf2204301 && conn != 0xf2244311 && conn != 0xf2045f14 && conn != 0xf2205004 && conn != 0xf2208001 && conn != 0xf4204011 && conn != 0xf4208011 && conn != 0xf4248011) {
361 "Unknown DCB 1.4 / 1.5 entry, please report\n");
362 /* cause output setting to fail, so message is seen */
363 dev_priv->dcb_table.entries = 0;
366 /* most of the below is a "best guess" atm */
367 entry->type = conn & 0xf;
368 if (entry->type == 4) { /* digital */
370 entry->type = DCB_OUTPUT_LVDS;
372 entry->type = DCB_OUTPUT_TMDS;
374 /* what's in bits 5-13? could be some brooktree/chrontel/philips thing, in tv case */
375 entry->i2c_index = (conn >> 14) & 0xf;
376 /* raw heads field is in range 0-1, so move to 1-2 */
377 entry->heads = ((conn >> 18) & 0x7) + 1;
378 entry->location = (conn >> 21) & 0xf;
379 entry->bus = (conn >> 25) & 0x7;
380 /* set or to be same as heads -- hopefully safe enough */
381 entry->or = entry->heads;
383 switch (entry->type) {
384 case DCB_OUTPUT_LVDS:
385 /* this is probably buried in conn's unknown bits */
386 entry->lvdsconf.use_power_scripts = true;
388 case DCB_OUTPUT_TMDS:
389 /* invent a DVI-A output, by copying the fields of the DVI-D output
390 * reported to work by math_b on an NV20(!) */
391 memcpy(&entry[1], &entry[0], sizeof(struct dcb_entry));
392 entry[1].type = DCB_OUTPUT_ANALOG;
393 dev_priv->dcb_table.entries++;
395 read_dcb_i2c_entry(dev, dcb_version, i2ctabptr, entry->i2c_index);
396 } else if (dcb_version >= 0x12) {
397 /* v1.2 tables normally have the same 5 entries, which are not
398 * specific to the card, so use the defaults for a crt */
399 /* DCB v1.2 does have an I2C table that read_dcb_i2c_table can handle, but cards
400 * exist (seen on nv11) where the pointer to the table points to the wrong
401 * place, so for now, we rely on the indices parsed in parse_bmp_structure
403 entry->i2c_index = dev_priv->bios.legacy.i2c_indices.crt;
404 } else { /* pre DCB / v1.1 - use the safe defaults for a crt */
406 "No information in BIOS output table; assuming a CRT output exists\n");
407 entry->i2c_index = dev_priv->bios.legacy.i2c_indices.crt;
410 if (entry->type == DCB_OUTPUT_LVDS && dev_priv->bios.fp.strapping != 0xff)
411 entry->lvdsconf.use_straps_for_mode = true;
413 dev_priv->dcb_table.entries++;
418 static void merge_like_dcb_entries(struct drm_device *dev)
420 struct drm_nouveau_private *dev_priv = dev->dev_private;
422 /* DCB v2.0 lists each output combination separately.
423 * Here we merge compatible entries to have fewer outputs, with more options
425 int i, newentries = 0;
427 for (i = 0; i < dev_priv->dcb_table.entries; i++) {
428 struct dcb_entry *ient = &dev_priv->dcb_table.entry[i];
431 for (j = i + 1; j < dev_priv->dcb_table.entries; j++) {
432 struct dcb_entry *jent = &dev_priv->dcb_table.entry[j];
434 if (jent->type == 100) /* already merged entry */
437 /* merge heads field when all other fields the same */
438 if (jent->i2c_index == ient->i2c_index && jent->type == ient->type && jent->location == ient->location && jent->or == ient->or) {
440 "Merging DCB entries %d and %d\n", i, j);
441 ient->heads |= jent->heads;
442 jent->type = 100; /* dummy value */
447 /* Compact entries merged into others out of dcb_table */
448 for (i = 0; i < dev_priv->dcb_table.entries; i++) {
449 if ( dev_priv->dcb_table.entry[i].type == 100 )
453 memcpy(&dev_priv->dcb_table.entry[newentries], &dev_priv->dcb_table.entry[i], sizeof(struct dcb_entry));
457 dev_priv->dcb_table.entries = newentries;
460 static unsigned int parse_dcb_table(struct drm_device *dev, struct bios *bios)
462 struct drm_nouveau_private *dev_priv = dev->dev_private;
463 uint16_t dcbptr, i2ctabptr = 0;
465 uint8_t dcb_version, headerlen = 0x4, entries = MAX_NUM_DCB_ENTRIES;
466 bool configblock = true;
467 int recordlength = 8, confofs = 4;
470 dev_priv->dcb_table.entries = 0;
472 /* get the offset from 0x36 */
473 dcbptr = le16_to_cpu(*(uint16_t *)&bios->data[0x36]);
477 "No Display Configuration Block pointer found\n");
478 /* this situation likely means a really old card, pre DCB, so we'll add the safe CRT entry */
479 parse_dcb_entry(dev, 0, 0, 0, 0, 0);
483 dcbtable = &bios->data[dcbptr];
485 /* get DCB version */
486 dcb_version = dcbtable[0];
488 "Display Configuration Block version %d.%d found\n",
489 dcb_version >> 4, dcb_version & 0xf);
491 if (dcb_version >= 0x20) { /* NV17+ */
494 if (dcb_version >= 0x30) { /* NV40+ */
495 headerlen = dcbtable[1];
496 entries = dcbtable[2];
497 recordlength = dcbtable[3];
498 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[4]);
499 sig = le32_to_cpu(*(uint32_t *)&dcbtable[6]);
502 "DCB header length %d, with %d possible entries\n",
505 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
506 sig = le32_to_cpu(*(uint32_t *)&dcbtable[4]);
510 if (sig != 0x4edcbdcb) {
512 "Bad Display Configuration Block signature (%08X)\n", sig);
515 } else if (dcb_version >= 0x14) { /* some NV15/16, and NV11+ */
519 strncpy(sig, (char *)&dcbtable[-7], 7);
520 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
524 if (strcmp(sig, "DEV_REC")) {
526 "Bad Display Configuration Block signature (%s)\n", sig);
529 } else if (dcb_version >= 0x12) { /* some NV6/10, and NV15+ */
530 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
532 } else { /* NV5+, maybe NV4 */
533 /* DCB 1.1 seems to be quite unhelpful - we'll just add the safe CRT entry */
534 parse_dcb_entry(dev, 0, dcb_version, 0, 0, 0);
538 if (entries >= MAX_NUM_DCB_ENTRIES)
539 entries = MAX_NUM_DCB_ENTRIES;
541 for (i = 0; i < entries; i++) {
542 uint32_t connection, config = 0;
544 connection = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + recordlength * i]);
546 config = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + confofs + recordlength * i]);
548 /* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */
549 if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
551 if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */
554 DRM_INFO("Raw DCB entry %d: %08x %08x\n", i, connection, config);
555 if (!parse_dcb_entry(dev, dev_priv->dcb_table.entries, dcb_version, i2ctabptr, connection, config))
559 merge_like_dcb_entries(dev);
561 return dev_priv->dcb_table.entries;
564 int nouveau_parse_bios(struct drm_device *dev)
566 struct drm_nouveau_private *dev_priv = dev->dev_private;
568 const uint8_t bit_signature[] = { 'B', 'I', 'T' };
571 dev_priv->bios.data = kzalloc(NV50_PROM__ESIZE, GFP_KERNEL);
572 if (!dev_priv->bios.data)
575 if (!nv_shadow_bios(dev, dev_priv->bios.data))
578 dev_priv->bios.length = dev_priv->bios.data[2] * 512;
579 if (dev_priv->bios.length > NV50_PROM__ESIZE)
580 dev_priv->bios.length = NV50_PROM__ESIZE;
582 if ((offset = findstr(dev_priv->bios.data, dev_priv->bios.length, bit_signature, sizeof(bit_signature)))) {
583 DRM_INFO("BIT BIOS found\n");
584 parse_bit_structure(dev, &dev_priv->bios, offset + 4);
586 DRM_ERROR("BIT BIOS not found\n");
590 if (parse_dcb_table(dev, &dev_priv->bios))
591 DRM_INFO("Found %d entries in DCB\n", dev_priv->dcb_table.entries);
597 #define NV_RAMDAC_NVPLL 0x00680500
598 #define NV_RAMDAC_MPLL 0x00680504
599 #define NV_RAMDAC_VPLL 0x00680508
600 # define NV_RAMDAC_PLL_COEFF_MDIV 0x000000FF
601 # define NV_RAMDAC_PLL_COEFF_NDIV 0x0000FF00
602 # define NV_RAMDAC_PLL_COEFF_PDIV 0x00070000
603 # define NV30_RAMDAC_ENABLE_VCO2 (1 << 7)
604 #define NV_RAMDAC_VPLL2 0x00680520
606 bool get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
611 * One byte header (version), one record of 24 bytes
612 * Version 0x11: NV36 - Not implemented
613 * Seems to have same record style as 0x10, but 3 records rather than 1
614 * Version 0x20: Found on Geforce 6 cards
615 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
616 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
617 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
618 * length in general, some (integrated) have an extra configuration byte
621 struct drm_nouveau_private *dev_priv = dev->dev_private;
622 struct bios *bios = &dev_priv->bios;
623 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
625 uint32_t crystal_strap_mask, crystal_straps;
627 if (!bios->pll_limit_tbl_ptr) {
628 if (bios->chip_version >= 0x40 || bios->chip_version == 0x31 || bios->chip_version == 0x36) {
629 DRM_ERROR("Pointer to PLL limits table invalid\n");
633 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
635 DRM_INFO("Found PLL limits table version 0x%X\n", pll_lim_ver);
638 crystal_strap_mask = 1 << 6;
639 /* open coded pNv->twoHeads test */
640 if (bios->chip_version > 0x10 && bios->chip_version != 0x15 &&
641 bios->chip_version != 0x1a && bios->chip_version != 0x20)
642 crystal_strap_mask |= 1 << 22;
643 crystal_straps = NV_READ(NV50_PEXTDEV + 0x0) & crystal_strap_mask;
645 switch (pll_lim_ver) {
646 /* we use version 0 to indicate a pre limit table bios (single stage pll)
647 * and load the hard coded limits instead */
651 case 0x11: /* strictly v0x11 has 3 entries, but the last two don't seem to get used */
659 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
660 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
661 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
664 DRM_ERROR("PLL limits table revision not currently supported\n");
668 /* initialize all members to zero */
669 memset(pll_lim, 0, sizeof(struct pll_lims));
671 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
672 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex;
674 pll_lim->vco1.minfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs])));
675 pll_lim->vco1.maxfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 4])));
676 pll_lim->vco2.minfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 8])));
677 pll_lim->vco2.maxfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 12])));
678 pll_lim->vco1.min_inputfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 16])));
679 pll_lim->vco2.min_inputfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 20])));
680 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
682 /* these values taken from nv30/31/36 */
683 pll_lim->vco1.min_n = 0x1;
684 if (bios->chip_version == 0x36)
685 pll_lim->vco1.min_n = 0x5;
686 pll_lim->vco1.max_n = 0xff;
687 pll_lim->vco1.min_m = 0x1;
688 pll_lim->vco1.max_m = 0xd;
689 pll_lim->vco2.min_n = 0x4;
690 /* on nv30, 31, 36 (i.e. all cards with two stage PLLs with this
691 * table version (apart from nv35)), N2 is compared to
692 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
695 pll_lim->vco2.max_n = 0x28;
696 if (bios->chip_version == 0x30 || bios->chip_version == 0x35)
697 /* only 5 bits available for N2 on nv30/35 */
698 pll_lim->vco2.max_n = 0x1f;
699 pll_lim->vco2.min_m = 0x1;
700 pll_lim->vco2.max_m = 0x4;
701 } else if (pll_lim_ver) { /* ver 0x20, 0x21 */
702 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
703 uint32_t reg = 0; /* default match */
706 /* first entry is default match, if nothing better. warn if reg field nonzero */
707 if (le32_to_cpu(*((uint32_t *)&bios->data[plloffs])))
708 DRM_ERROR("Default PLL limit entry has non-zero register field\n");
710 if (limit_match > MAX_PLL_TYPES)
711 /* we've been passed a reg as the match */
713 else /* limit match is a pll type */
714 for (i = 1; i < entries && !reg; i++) {
715 uint32_t cmpreg = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + recordlen * i])));
717 if (limit_match == NVPLL && (cmpreg == NV_RAMDAC_NVPLL || cmpreg == 0x4000))
719 if (limit_match == MPLL && (cmpreg == NV_RAMDAC_MPLL || cmpreg == 0x4020))
721 if (limit_match == VPLL1 && (cmpreg == NV_RAMDAC_VPLL || cmpreg == 0x4010))
723 if (limit_match == VPLL2 && (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018))
727 for (i = 1; i < entries; i++)
728 if (le32_to_cpu(*((uint32_t *)&bios->data[plloffs + recordlen * i])) == reg) {
733 plloffs += recordlen * pllindex;
735 DRM_INFO("Loading PLL limits for reg 0x%08x\n", pllindex ? reg : 0);
737 /* frequencies are stored in tables in MHz, kHz are more useful, so we convert */
739 /* What output frequencies can each VCO generate? */
740 pll_lim->vco1.minfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 4]))) * 1000;
741 pll_lim->vco1.maxfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 6]))) * 1000;
742 pll_lim->vco2.minfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 8]))) * 1000;
743 pll_lim->vco2.maxfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 10]))) * 1000;
745 /* What input frequencies do they accept (past the m-divider)? */
746 pll_lim->vco1.min_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 12]))) * 1000;
747 pll_lim->vco2.min_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 14]))) * 1000;
748 pll_lim->vco1.max_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 16]))) * 1000;
749 pll_lim->vco2.max_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 18]))) * 1000;
751 /* What values are accepted as multiplier and divider? */
752 pll_lim->vco1.min_n = bios->data[plloffs + 20];
753 pll_lim->vco1.max_n = bios->data[plloffs + 21];
754 pll_lim->vco1.min_m = bios->data[plloffs + 22];
755 pll_lim->vco1.max_m = bios->data[plloffs + 23];
756 pll_lim->vco2.min_n = bios->data[plloffs + 24];
757 pll_lim->vco2.max_n = bios->data[plloffs + 25];
758 pll_lim->vco2.min_m = bios->data[plloffs + 26];
759 pll_lim->vco2.max_m = bios->data[plloffs + 27];
761 pll_lim->unk1c = bios->data[plloffs + 28];
762 pll_lim->max_log2p_bias = bios->data[plloffs + 29];
763 pll_lim->log2p_bias = bios->data[plloffs + 30];
765 if (recordlen > 0x22)
766 pll_lim->refclk = le32_to_cpu(*((uint32_t *)&bios->data[plloffs + 31]));
768 if (recordlen > 0x23)
769 if (bios->data[plloffs + 35])
770 DRM_ERROR("Bits set in PLL configuration byte (%x)\n", bios->data[plloffs + 35]);
772 /* C51 special not seen elsewhere */
773 /*if (bios->chip_version == 0x51 && !pll_lim->refclk) {
774 uint32_t sel_clk = nv32_rd(pScrn, NV_RAMDAC_SEL_CLK);
776 if (((limit_match == NV_RAMDAC_VPLL || limit_match == VPLL1) && sel_clk & 0x20) ||
777 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) {
778 if (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_REVISION) < 0xa3)
779 pll_lim->refclk = 200000;
781 pll_lim->refclk = 25000;
786 /* By now any valid limit table ought to have set a max frequency for
787 * vco1, so if it's zero it's either a pre limit table bios, or one
788 * with an empty limit table (seen on nv18)
790 if (!pll_lim->vco1.maxfreq) {
791 pll_lim->vco1.minfreq = bios->fminvco;
792 pll_lim->vco1.maxfreq = bios->fmaxvco;
793 pll_lim->vco1.min_inputfreq = 0;
794 pll_lim->vco1.max_inputfreq = INT_MAX;
795 pll_lim->vco1.min_n = 0x1;
796 pll_lim->vco1.max_n = 0xff;
797 pll_lim->vco1.min_m = 0x1;
798 if (crystal_straps == 0) {
799 /* nv05 does this, nv11 doesn't, nv10 unknown */
800 if (bios->chip_version < 0x11)
801 pll_lim->vco1.min_m = 0x7;
802 pll_lim->vco1.max_m = 0xd;
804 if (bios->chip_version < 0x11)
805 pll_lim->vco1.min_m = 0x8;
806 pll_lim->vco1.max_m = 0xe;
810 if (!pll_lim->refclk)
811 switch (crystal_straps) {
813 pll_lim->refclk = 13500;
816 pll_lim->refclk = 14318;
819 pll_lim->refclk = 27000;
821 case (1 << 22 | 1 << 6):
822 pll_lim->refclk = 25000;
826 #if 1 /* for easy debugging */
827 DRM_INFO("pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
828 DRM_INFO("pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
829 DRM_INFO("pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
830 DRM_INFO("pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
832 DRM_INFO("pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
833 DRM_INFO("pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
834 DRM_INFO("pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
835 DRM_INFO("pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
837 DRM_INFO("pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
838 DRM_INFO("pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
839 DRM_INFO("pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
840 DRM_INFO("pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
841 DRM_INFO("pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
842 DRM_INFO("pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
843 DRM_INFO("pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
844 DRM_INFO("pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
846 DRM_INFO("pll.unk1c: %d\n", pll_lim->unk1c);
847 DRM_INFO("pll.max_log2p_bias: %d\n", pll_lim->max_log2p_bias);
848 DRM_INFO("pll.log2p_bias: %d\n", pll_lim->log2p_bias);
850 DRM_INFO("pll.refclk: %d\n", pll_lim->refclk);