2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 * Copyright 2006 Dave Airlie <airlied@linux.ie>
28 * Jesse Barnes <jesse.barnes@intel.com>
31 #include <linux/i2c.h>
32 #include <linux/delay.h>
36 #include "intel_drv.h"
39 #include "intel_sdvo_regs.h"
41 struct intel_sdvo_priv {
42 struct intel_i2c_chan *i2c_bus;
48 struct intel_sdvo_caps caps;
49 int pixel_clock_min, pixel_clock_max;
52 u16 save_active_outputs;
53 struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
54 struct intel_sdvo_dtd save_output_dtd[16];
59 * Writes the SDVOB or SDVOC with the given value, but always writes both
60 * SDVOB and SDVOC to work around apparent hardware issues (according to
61 * comments in the BIOS).
63 void intel_sdvo_write_sdvox(struct drm_output *output, u32 val)
65 struct drm_device *dev = output->dev;
66 struct drm_i915_private *dev_priv = dev->dev_private;
67 struct intel_output *intel_output = to_intel_output(output);
68 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
69 u32 bval = val, cval = val;
72 if (sdvo_priv->output_device == SDVOB) {
73 cval = I915_READ(SDVOC);
75 bval = I915_READ(SDVOB);
78 * Write the registers twice for luck. Sometimes,
79 * writing them only once doesn't appear to 'stick'.
80 * The BIOS does this too. Yay, magic
82 for (i = 0; i < 2; i++)
84 I915_WRITE(SDVOB, bval);
86 I915_WRITE(SDVOC, cval);
91 static bool intel_sdvo_read_byte(struct drm_output *output, u8 addr,
94 struct intel_output *intel_output = to_intel_output(output);
95 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
100 struct i2c_msg msgs[] = {
102 .addr = sdvo_priv->i2c_bus->slave_addr,
108 .addr = sdvo_priv->i2c_bus->slave_addr,
118 if ((ret = i2c_transfer(&sdvo_priv->i2c_bus->adapter, msgs, 2)) == 2)
120 // DRM_DEBUG("got back from addr %02X = %02x\n", out_buf[0], buf[0]);
125 DRM_DEBUG("i2c transfer returned %d\n", ret);
129 static bool intel_sdvo_write_byte(struct drm_output *output, int addr,
132 struct intel_output *intel_output = to_intel_output(output);
134 struct i2c_msg msgs[] = {
136 .addr = intel_output->i2c_bus->slave_addr,
146 if (i2c_transfer(&intel_output->i2c_bus->adapter, msgs, 1) == 1)
153 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
154 /** Mapping of command numbers to names, for debug output */
155 const static struct _sdvo_cmd_name {
158 } sdvo_cmd_names[] = {
159 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
160 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
161 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
162 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
163 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
164 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
165 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
166 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
167 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
168 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
169 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
170 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
171 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
172 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
173 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
174 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
175 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
176 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
177 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
178 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
179 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
180 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
181 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
182 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
183 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
184 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
185 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
186 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
187 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
188 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
189 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
190 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
191 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
192 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
193 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
194 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_RESOLUTION_SUPPORT),
195 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
198 #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
199 #define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv)
201 static void intel_sdvo_write_cmd(struct drm_output *output, u8 cmd,
202 void *args, int args_len)
204 struct intel_output *intel_output = to_intel_output(output);
205 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
209 DRM_DEBUG("%s: W: %02X ", SDVO_NAME(sdvo_priv), cmd);
210 for (i = 0; i < args_len; i++)
211 printk("%02X ", ((u8 *)args)[i]);
214 for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
215 if (cmd == sdvo_cmd_names[i].cmd) {
216 printk("(%s)", sdvo_cmd_names[i].name);
220 if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
221 printk("(%02X)",cmd);
225 for (i = 0; i < args_len; i++) {
226 intel_sdvo_write_byte(output, SDVO_I2C_ARG_0 - i, ((u8*)args)[i]);
229 intel_sdvo_write_byte(output, SDVO_I2C_OPCODE, cmd);
232 static const char *cmd_status_names[] = {
238 "Target not specified",
239 "Scaling not supported"
242 static u8 intel_sdvo_read_response(struct drm_output *output, void *response,
245 struct intel_output *intel_output = to_intel_output(output);
246 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
252 /* Read the command response */
253 for (i = 0; i < response_len; i++) {
254 intel_sdvo_read_byte(output, SDVO_I2C_RETURN_0 + i,
255 &((u8 *)response)[i]);
258 /* read the return status */
259 intel_sdvo_read_byte(output, SDVO_I2C_CMD_STATUS, &status);
262 DRM_DEBUG("%s: R: ", SDVO_NAME(sdvo_priv));
263 for (i = 0; i < response_len; i++)
264 printk("%02X ", ((u8 *)response)[i]);
267 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
268 printk("(%s)", cmd_status_names[status]);
270 printk("(??? %d)", status);
274 if (status != SDVO_CMD_STATUS_PENDING)
283 int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
285 if (mode->clock >= 100000)
287 else if (mode->clock >= 50000)
294 * Don't check status code from this as it switches the bus back to the
295 * SDVO chips which defeats the purpose of doing a bus switch in the first
298 void intel_sdvo_set_control_bus_switch(struct drm_output *output, u8 target)
300 intel_sdvo_write_cmd(output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1);
303 static bool intel_sdvo_set_target_input(struct drm_output *output, bool target_0, bool target_1)
305 struct intel_sdvo_set_target_input_args targets = {0};
308 if (target_0 && target_1)
309 return SDVO_CMD_STATUS_NOTSUPP;
312 targets.target_1 = 1;
314 intel_sdvo_write_cmd(output, SDVO_CMD_SET_TARGET_INPUT, &targets,
317 status = intel_sdvo_read_response(output, NULL, 0);
319 return (status == SDVO_CMD_STATUS_SUCCESS);
323 * Return whether each input is trained.
325 * This function is making an assumption about the layout of the response,
326 * which should be checked against the docs.
328 static bool intel_sdvo_get_trained_inputs(struct drm_output *output, bool *input_1, bool *input_2)
330 struct intel_sdvo_get_trained_inputs_response response;
333 intel_sdvo_write_cmd(output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
334 status = intel_sdvo_read_response(output, &response, sizeof(response));
335 if (status != SDVO_CMD_STATUS_SUCCESS)
338 *input_1 = response.input0_trained;
339 *input_2 = response.input1_trained;
343 static bool intel_sdvo_get_active_outputs(struct drm_output *output,
348 intel_sdvo_write_cmd(output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
349 status = intel_sdvo_read_response(output, outputs, sizeof(*outputs));
351 return (status == SDVO_CMD_STATUS_SUCCESS);
354 static bool intel_sdvo_set_active_outputs(struct drm_output *output,
359 intel_sdvo_write_cmd(output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
361 status = intel_sdvo_read_response(output, NULL, 0);
362 return (status == SDVO_CMD_STATUS_SUCCESS);
365 static bool intel_sdvo_set_encoder_power_state(struct drm_output *output,
368 u8 status, state = SDVO_ENCODER_STATE_ON;
372 state = SDVO_ENCODER_STATE_ON;
374 case DPMSModeStandby:
375 state = SDVO_ENCODER_STATE_STANDBY;
377 case DPMSModeSuspend:
378 state = SDVO_ENCODER_STATE_SUSPEND;
381 state = SDVO_ENCODER_STATE_OFF;
385 intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
387 status = intel_sdvo_read_response(output, NULL, 0);
389 return (status == SDVO_CMD_STATUS_SUCCESS);
392 static bool intel_sdvo_get_input_pixel_clock_range(struct drm_output *output,
396 struct intel_sdvo_pixel_clock_range clocks;
399 intel_sdvo_write_cmd(output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
402 status = intel_sdvo_read_response(output, &clocks, sizeof(clocks));
404 if (status != SDVO_CMD_STATUS_SUCCESS)
407 /* Convert the values from units of 10 kHz to kHz. */
408 *clock_min = clocks.min * 10;
409 *clock_max = clocks.max * 10;
414 static bool intel_sdvo_set_target_output(struct drm_output *output,
419 intel_sdvo_write_cmd(output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
422 status = intel_sdvo_read_response(output, NULL, 0);
423 return (status == SDVO_CMD_STATUS_SUCCESS);
426 static bool intel_sdvo_get_timing(struct drm_output *output, u8 cmd,
427 struct intel_sdvo_dtd *dtd)
431 intel_sdvo_write_cmd(output, cmd, NULL, 0);
432 status = intel_sdvo_read_response(output, &dtd->part1,
434 if (status != SDVO_CMD_STATUS_SUCCESS)
437 intel_sdvo_write_cmd(output, cmd + 1, NULL, 0);
438 status = intel_sdvo_read_response(output, &dtd->part2,
440 if (status != SDVO_CMD_STATUS_SUCCESS)
446 static bool intel_sdvo_get_input_timing(struct drm_output *output,
447 struct intel_sdvo_dtd *dtd)
449 return intel_sdvo_get_timing(output,
450 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
453 static bool intel_sdvo_get_output_timing(struct drm_output *output,
454 struct intel_sdvo_dtd *dtd)
456 return intel_sdvo_get_timing(output,
457 SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
460 static bool intel_sdvo_set_timing(struct drm_output *output, u8 cmd,
461 struct intel_sdvo_dtd *dtd)
465 intel_sdvo_write_cmd(output, cmd, &dtd->part1, sizeof(dtd->part1));
466 status = intel_sdvo_read_response(output, NULL, 0);
467 if (status != SDVO_CMD_STATUS_SUCCESS)
470 intel_sdvo_write_cmd(output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
471 status = intel_sdvo_read_response(output, NULL, 0);
472 if (status != SDVO_CMD_STATUS_SUCCESS)
478 static bool intel_sdvo_set_input_timing(struct drm_output *output,
479 struct intel_sdvo_dtd *dtd)
481 return intel_sdvo_set_timing(output,
482 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
485 static bool intel_sdvo_set_output_timing(struct drm_output *output,
486 struct intel_sdvo_dtd *dtd)
488 return intel_sdvo_set_timing(output,
489 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
493 static bool intel_sdvo_get_preferred_input_timing(struct drm_output *output,
494 struct intel_sdvo_dtd *dtd)
496 struct intel_output *intel_output = to_intel_output(output);
497 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
500 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
503 status = intel_sdvo_read_response(output, &dtd->part1,
505 if (status != SDVO_CMD_STATUS_SUCCESS)
508 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
510 status = intel_sdvo_read_response(output, &dtd->part2,
512 if (status != SDVO_CMD_STATUS_SUCCESS)
519 static int intel_sdvo_get_clock_rate_mult(struct drm_output *output)
523 intel_sdvo_write_cmd(output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
524 status = intel_sdvo_read_response(output, &response, 1);
526 if (status != SDVO_CMD_STATUS_SUCCESS) {
527 DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n");
528 return SDVO_CLOCK_RATE_MULT_1X;
530 DRM_DEBUG("Current clock rate multiplier: %d\n", response);
536 static bool intel_sdvo_set_clock_rate_mult(struct drm_output *output, u8 val)
540 intel_sdvo_write_cmd(output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
541 status = intel_sdvo_read_response(output, NULL, 0);
542 if (status != SDVO_CMD_STATUS_SUCCESS)
548 static bool intel_sdvo_mode_fixup(struct drm_output *output,
549 struct drm_display_mode *mode,
550 struct drm_display_mode *adjusted_mode)
552 /* Make the CRTC code factor in the SDVO pixel multiplier. The SDVO
553 * device will be told of the multiplier during mode_set.
555 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
559 static void intel_sdvo_mode_set(struct drm_output *output,
560 struct drm_display_mode *mode,
561 struct drm_display_mode *adjusted_mode)
563 struct drm_device *dev = output->dev;
564 struct drm_i915_private *dev_priv = dev->dev_private;
565 struct drm_crtc *crtc = output->crtc;
566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
567 struct intel_output *intel_output = to_intel_output(output);
568 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
570 u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len;
571 u16 h_sync_offset, v_sync_offset;
573 struct intel_sdvo_dtd output_dtd;
574 int sdvo_pixel_multiply;
579 width = mode->crtc_hdisplay;
580 height = mode->crtc_vdisplay;
582 /* do some mode translations */
583 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
584 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
586 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
587 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
589 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
590 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
592 output_dtd.part1.clock = mode->clock / 10;
593 output_dtd.part1.h_active = width & 0xff;
594 output_dtd.part1.h_blank = h_blank_len & 0xff;
595 output_dtd.part1.h_high = (((width >> 8) & 0xf) << 4) |
596 ((h_blank_len >> 8) & 0xf);
597 output_dtd.part1.v_active = height & 0xff;
598 output_dtd.part1.v_blank = v_blank_len & 0xff;
599 output_dtd.part1.v_high = (((height >> 8) & 0xf) << 4) |
600 ((v_blank_len >> 8) & 0xf);
602 output_dtd.part2.h_sync_off = h_sync_offset;
603 output_dtd.part2.h_sync_width = h_sync_len & 0xff;
604 output_dtd.part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
606 output_dtd.part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
607 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
608 ((v_sync_len & 0x30) >> 4);
610 output_dtd.part2.dtd_flags = 0x18;
611 if (mode->flags & V_PHSYNC)
612 output_dtd.part2.dtd_flags |= 0x2;
613 if (mode->flags & V_PVSYNC)
614 output_dtd.part2.dtd_flags |= 0x4;
616 output_dtd.part2.sdvo_flags = 0;
617 output_dtd.part2.v_sync_off_high = v_sync_offset & 0xc0;
618 output_dtd.part2.reserved = 0;
620 /* Set the output timing to the screen */
621 intel_sdvo_set_target_output(output, sdvo_priv->active_outputs);
622 intel_sdvo_set_output_timing(output, &output_dtd);
624 /* Set the input timing to the screen. Assume always input 0. */
625 intel_sdvo_set_target_input(output, true, false);
627 /* We would like to use i830_sdvo_create_preferred_input_timing() to
628 * provide the device with a timing it can support, if it supports that
629 * feature. However, presumably we would need to adjust the CRTC to
630 * output the preferred timing, and we don't support that currently.
633 success = intel_sdvo_create_preferred_input_timing(output, clock,
636 struct intel_sdvo_dtd *input_dtd;
638 intel_sdvo_get_preferred_input_timing(output, &input_dtd);
639 intel_sdvo_set_input_timing(output, &input_dtd);
642 intel_sdvo_set_input_timing(output, &output_dtd);
645 switch (intel_sdvo_get_pixel_multiplier(mode)) {
647 intel_sdvo_set_clock_rate_mult(output,
648 SDVO_CLOCK_RATE_MULT_1X);
651 intel_sdvo_set_clock_rate_mult(output,
652 SDVO_CLOCK_RATE_MULT_2X);
655 intel_sdvo_set_clock_rate_mult(output,
656 SDVO_CLOCK_RATE_MULT_4X);
660 /* Set the SDVO control regs. */
661 if (0/*IS_I965GM(dev)*/) {
662 sdvox = SDVO_BORDER_ENABLE;
664 sdvox = I915_READ(sdvo_priv->output_device);
665 switch (sdvo_priv->output_device) {
667 sdvox &= SDVOB_PRESERVE_MASK;
670 sdvox &= SDVOC_PRESERVE_MASK;
673 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
675 if (intel_crtc->pipe == 1)
676 sdvox |= SDVO_PIPE_B_SELECT;
678 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
680 /* done in crtc_mode_set as the dpll_md reg must be written
682 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
683 /* done in crtc_mode_set as it lives inside the
686 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
689 intel_sdvo_write_sdvox(output, sdvox);
692 static void intel_sdvo_dpms(struct drm_output *output, int mode)
694 struct drm_device *dev = output->dev;
695 struct drm_i915_private *dev_priv = dev->dev_private;
696 struct intel_output *intel_output = to_intel_output(output);
697 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
700 if (mode != DPMSModeOn) {
701 intel_sdvo_set_active_outputs(output, 0);
703 intel_sdvo_set_encoder_power_state(output, mode);
705 if (mode == DPMSModeOff) {
706 temp = I915_READ(sdvo_priv->output_device);
707 if ((temp & SDVO_ENABLE) != 0) {
708 intel_sdvo_write_sdvox(output, temp & ~SDVO_ENABLE);
716 temp = I915_READ(sdvo_priv->output_device);
717 if ((temp & SDVO_ENABLE) == 0)
718 intel_sdvo_write_sdvox(output, temp | SDVO_ENABLE);
719 for (i = 0; i < 2; i++)
720 intel_wait_for_vblank(dev);
722 status = intel_sdvo_get_trained_inputs(output, &input1,
726 /* Warn if the device reported failure to sync.
727 * A lot of SDVO devices fail to notify of sync, but it's
728 * a given it the status is a success, we succeeded.
730 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
731 DRM_DEBUG("First %s output reported failure to sync\n",
732 SDVO_NAME(sdvo_priv));
736 intel_sdvo_set_encoder_power_state(output, mode);
737 intel_sdvo_set_active_outputs(output, sdvo_priv->active_outputs);
742 static void intel_sdvo_save(struct drm_output *output)
744 struct drm_device *dev = output->dev;
745 struct drm_i915_private *dev_priv = dev->dev_private;
746 struct intel_output *intel_output = to_intel_output(output);
747 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
750 sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(output);
751 intel_sdvo_get_active_outputs(output, &sdvo_priv->save_active_outputs);
753 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
754 intel_sdvo_set_target_input(output, true, false);
755 intel_sdvo_get_input_timing(output,
756 &sdvo_priv->save_input_dtd_1);
759 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
760 intel_sdvo_set_target_input(output, false, true);
761 intel_sdvo_get_input_timing(output,
762 &sdvo_priv->save_input_dtd_2);
765 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
767 u16 this_output = (1 << o);
768 if (sdvo_priv->caps.output_flags & this_output)
770 intel_sdvo_set_target_output(output, this_output);
771 intel_sdvo_get_output_timing(output,
772 &sdvo_priv->save_output_dtd[o]);
776 sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);
779 static void intel_sdvo_restore(struct drm_output *output)
781 struct drm_device *dev = output->dev;
782 struct drm_i915_private *dev_priv = dev->dev_private;
783 struct intel_output *intel_output = to_intel_output(output);
784 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
790 intel_sdvo_set_active_outputs(output, 0);
792 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
794 u16 this_output = (1 << o);
795 if (sdvo_priv->caps.output_flags & this_output) {
796 intel_sdvo_set_target_output(output, this_output);
797 intel_sdvo_set_output_timing(output, &sdvo_priv->save_output_dtd[o]);
801 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
802 intel_sdvo_set_target_input(output, true, false);
803 intel_sdvo_set_input_timing(output, &sdvo_priv->save_input_dtd_1);
806 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
807 intel_sdvo_set_target_input(output, false, true);
808 intel_sdvo_set_input_timing(output, &sdvo_priv->save_input_dtd_2);
811 intel_sdvo_set_clock_rate_mult(output, sdvo_priv->save_sdvo_mult);
813 I915_WRITE(sdvo_priv->output_device, sdvo_priv->save_SDVOX);
815 if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
817 for (i = 0; i < 2; i++)
818 intel_wait_for_vblank(dev);
819 status = intel_sdvo_get_trained_inputs(output, &input1, &input2);
820 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
821 DRM_DEBUG("First %s output reported failure to sync\n",
822 SDVO_NAME(sdvo_priv));
825 intel_sdvo_set_active_outputs(output, sdvo_priv->save_active_outputs);
828 static int intel_sdvo_mode_valid(struct drm_output *output,
829 struct drm_display_mode *mode)
831 struct intel_output *intel_output = to_intel_output(output);
832 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
834 if (mode->flags & V_DBLSCAN)
835 return MODE_NO_DBLESCAN;
837 if (sdvo_priv->pixel_clock_min > mode->clock)
838 return MODE_CLOCK_LOW;
840 if (sdvo_priv->pixel_clock_max < mode->clock)
841 return MODE_CLOCK_HIGH;
846 static bool intel_sdvo_get_capabilities(struct drm_output *output, struct intel_sdvo_caps *caps)
850 intel_sdvo_write_cmd(output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
851 status = intel_sdvo_read_response(output, caps, sizeof(*caps));
852 if (status != SDVO_CMD_STATUS_SUCCESS)
858 struct drm_output* intel_sdvo_find(struct drm_device *dev, int sdvoB)
860 struct drm_output *output = 0;
861 struct intel_output *iout = 0;
862 struct intel_sdvo_priv *sdvo;
864 /* find the sdvo output */
865 list_for_each_entry(output, &dev->mode_config.output_list, head) {
866 iout = to_intel_output(output);
868 if (iout->type != INTEL_OUTPUT_SDVO)
871 sdvo = iout->dev_priv;
873 if (sdvo->output_device == SDVOB && sdvoB)
876 if (sdvo->output_device == SDVOC && !sdvoB)
884 int intel_sdvo_supports_hotplug(struct drm_output *output)
893 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
894 status = intel_sdvo_read_response(output, &response, 2);
902 void intel_sdvo_set_hotplug(struct drm_output *output, int on)
907 intel_sdvo_write_cmd(output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
908 intel_sdvo_read_response(output, &response, 2);
911 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
912 status = intel_sdvo_read_response(output, &response, 2);
914 intel_sdvo_write_cmd(output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
918 intel_sdvo_write_cmd(output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
921 intel_sdvo_write_cmd(output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
922 intel_sdvo_read_response(output, &response, 2);
925 static enum drm_output_status intel_sdvo_detect(struct drm_output *output)
930 intel_sdvo_write_cmd(output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
931 status = intel_sdvo_read_response(output, &response, 2);
933 DRM_DEBUG("SDVO response %d %d\n", response[0], response[1]);
934 if ((response[0] != 0) || (response[1] != 0))
935 return output_status_connected;
937 return output_status_disconnected;
940 static int intel_sdvo_get_modes(struct drm_output *output)
942 /* set the bus switch and get the modes */
943 intel_sdvo_set_control_bus_switch(output, SDVO_CONTROL_BUS_DDC2);
944 intel_ddc_get_modes(output);
946 if (list_empty(&output->probed_modes))
950 /* Mac mini hack. On this device, I get DDC through the analog, which
951 * load-detects as disconnected. I fail to DDC through the SDVO DDC,
952 * but it does load-detect as connected. So, just steal the DDC bits
953 * from analog when we fail at finding it the right way.
962 static void intel_sdvo_destroy(struct drm_output *output)
964 struct intel_output *intel_output = to_intel_output(output);
966 if (intel_output->i2c_bus)
967 intel_i2c_destroy(intel_output->i2c_bus);
969 drm_output_cleanup(output);
973 static const struct drm_output_helper_funcs intel_sdvo_helper_funcs = {
974 .mode_fixup = intel_sdvo_mode_fixup,
975 .prepare = intel_output_prepare,
976 .mode_set = intel_sdvo_mode_set,
977 .commit = intel_output_commit,
980 static const struct drm_output_funcs intel_sdvo_output_funcs = {
981 .dpms = intel_sdvo_dpms,
982 .save = intel_sdvo_save,
983 .restore = intel_sdvo_restore,
984 .detect = intel_sdvo_detect,
985 .get_modes = intel_sdvo_get_modes,
986 .destroy = intel_sdvo_destroy,
987 .mode_valid = intel_sdvo_mode_valid,
990 void intel_sdvo_init(struct drm_device *dev, int output_device)
992 struct drm_output *output;
993 struct intel_output *intel_output;
994 struct intel_sdvo_priv *sdvo_priv;
995 struct intel_i2c_chan *i2cbus = NULL;
999 int output_type, output_id;
1001 intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
1002 if (!intel_output) {
1006 output = &intel_output->base;
1008 drm_output_init(dev, output, &intel_sdvo_output_funcs,
1009 DRM_MODE_OUTPUT_NONE);
1011 sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
1012 intel_output->type = INTEL_OUTPUT_SDVO;
1013 drm_output_helper_add(output, &intel_sdvo_helper_funcs);
1014 output->interlace_allowed = 0;
1015 output->doublescan_allowed = 0;
1017 /* setup the DDC bus. */
1018 if (output_device == SDVOB)
1019 i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
1021 i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
1023 if (i2cbus == NULL) {
1024 intel_sdvo_destroy(output);
1028 sdvo_priv->i2c_bus = i2cbus;
1030 if (output_device == SDVOB) {
1032 sdvo_priv->i2c_bus->slave_addr = 0x38;
1035 sdvo_priv->i2c_bus->slave_addr = 0x39;
1038 sdvo_priv->output_device = output_device;
1039 intel_output->i2c_bus = i2cbus;
1040 intel_output->dev_priv = sdvo_priv;
1043 /* Read the regs to test if we can talk to the device */
1044 for (i = 0; i < 0x40; i++) {
1045 if (!intel_sdvo_read_byte(output, i, &ch[i])) {
1046 DRM_DEBUG("No SDVO device found on SDVO%c\n",
1047 output_device == SDVOB ? 'B' : 'C');
1048 intel_sdvo_destroy(output);
1053 intel_sdvo_get_capabilities(output, &sdvo_priv->caps);
1055 memset(&sdvo_priv->active_outputs, 0, sizeof(sdvo_priv->active_outputs));
1057 /* TODO, CVBS, SVID, YPRPB & SCART outputs. */
1058 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB0)
1060 sdvo_priv->active_outputs = SDVO_OUTPUT_RGB0;
1061 output->display_info.subpixel_order = SubPixelHorizontalRGB;
1062 output_type = DRM_MODE_OUTPUT_DAC;
1063 connector_type = ConnectorVGA;
1065 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB1)
1067 sdvo_priv->active_outputs = SDVO_OUTPUT_RGB1;
1068 output->display_info.subpixel_order = SubPixelHorizontalRGB;
1069 output_type = DRM_MODE_OUTPUT_DAC;
1070 connector_type = ConnectorVGA;
1072 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
1074 sdvo_priv->active_outputs = SDVO_OUTPUT_TMDS0;
1075 output->display_info.subpixel_order = SubPixelHorizontalRGB;
1076 output_type = DRM_MODE_OUTPUT_TMDS;
1077 connector_type = ConnectorDVID;
1079 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS1)
1081 sdvo_priv->active_outputs = SDVO_OUTPUT_TMDS1;
1082 output->display_info.subpixel_order = SubPixelHorizontalRGB;
1083 output_type = DRM_MODE_OUTPUT_TMDS;
1084 connector_type = ConnectorDVID;
1088 unsigned char bytes[2];
1090 memcpy (bytes, &sdvo_priv->caps.output_flags, 2);
1091 DRM_DEBUG("%s: No active RGB or TMDS outputs (0x%02x%02x)\n",
1092 SDVO_NAME(sdvo_priv),
1093 bytes[0], bytes[1]);
1094 intel_sdvo_destroy(output);
1098 output->output_type = output_type;
1099 output->output_type_id = output_id;
1101 drm_sysfs_output_add(output);
1103 /* Set the input timing to the screen. Assume always input 0. */
1104 intel_sdvo_set_target_input(output, true, false);
1106 intel_sdvo_get_input_pixel_clock_range(output,
1107 &sdvo_priv->pixel_clock_min,
1108 &sdvo_priv->pixel_clock_max);
1111 DRM_DEBUG("%s device VID/DID: %02X:%02X.%02X, "
1112 "clock range %dMHz - %dMHz, "
1113 "input 1: %c, input 2: %c, "
1114 "output 1: %c, output 2: %c\n",
1115 SDVO_NAME(sdvo_priv),
1116 sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
1117 sdvo_priv->caps.device_rev_id,
1118 sdvo_priv->pixel_clock_min / 1000,
1119 sdvo_priv->pixel_clock_max / 1000,
1120 (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
1121 (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
1122 /* check currently supported outputs */
1123 sdvo_priv->caps.output_flags &
1124 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
1125 sdvo_priv->caps.output_flags &
1126 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
1128 intel_output->ddc_bus = i2cbus;
1130 drm_output_attach_property(output, dev->mode_config.connector_type_property, connector_type);