2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 * Copyright 2006 Dave Airlie <airlied@linux.ie>
28 * Jesse Barnes <jesse.barnes@intel.com>
31 #include <linux/i2c.h>
32 #include <linux/delay.h>
36 #include "intel_drv.h"
39 #include "intel_sdvo_regs.h"
41 struct intel_sdvo_priv {
42 struct intel_i2c_chan *i2c_bus;
48 struct intel_sdvo_caps caps;
49 int pixel_clock_min, pixel_clock_max;
52 u16 save_active_outputs;
53 struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
54 struct intel_sdvo_dtd save_output_dtd[16];
59 * Writes the SDVOB or SDVOC with the given value, but always writes both
60 * SDVOB and SDVOC to work around apparent hardware issues (according to
61 * comments in the BIOS).
63 void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val)
65 struct drm_device *dev = intel_output->base.dev;
66 struct drm_i915_private *dev_priv = dev->dev_private;
67 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
68 u32 bval = val, cval = val;
71 if (sdvo_priv->output_device == SDVOB) {
72 cval = I915_READ(SDVOC);
74 bval = I915_READ(SDVOB);
77 * Write the registers twice for luck. Sometimes,
78 * writing them only once doesn't appear to 'stick'.
79 * The BIOS does this too. Yay, magic
81 for (i = 0; i < 2; i++)
83 I915_WRITE(SDVOB, bval);
85 I915_WRITE(SDVOC, cval);
90 static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
93 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
98 struct i2c_msg msgs[] = {
100 .addr = sdvo_priv->i2c_bus->slave_addr,
106 .addr = sdvo_priv->i2c_bus->slave_addr,
116 if ((ret = i2c_transfer(&sdvo_priv->i2c_bus->adapter, msgs, 2)) == 2)
118 // DRM_DEBUG("got back from addr %02X = %02x\n", out_buf[0], buf[0]);
123 DRM_DEBUG("i2c transfer returned %d\n", ret);
127 static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
131 struct i2c_msg msgs[] = {
133 .addr = intel_output->i2c_bus->slave_addr,
143 if (i2c_transfer(&intel_output->i2c_bus->adapter, msgs, 1) == 1)
150 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
151 /** Mapping of command numbers to names, for debug output */
152 const static struct _sdvo_cmd_name {
155 } sdvo_cmd_names[] = {
156 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
157 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
158 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
159 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
160 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
161 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
162 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
163 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
164 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
165 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
166 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
167 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
168 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
169 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
170 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
171 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
172 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
173 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
174 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
175 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
176 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
177 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
178 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
179 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
180 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
181 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
182 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
183 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
184 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
185 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
186 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
187 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
188 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
189 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
190 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
191 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_RESOLUTION_SUPPORT),
192 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
195 #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
196 #define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv)
198 static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
199 void *args, int args_len)
201 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
205 DRM_DEBUG("%s: W: %02X ", SDVO_NAME(sdvo_priv), cmd);
206 for (i = 0; i < args_len; i++)
207 printk("%02X ", ((u8 *)args)[i]);
210 for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
211 if (cmd == sdvo_cmd_names[i].cmd) {
212 printk("(%s)", sdvo_cmd_names[i].name);
216 if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
217 printk("(%02X)",cmd);
221 for (i = 0; i < args_len; i++) {
222 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i, ((u8*)args)[i]);
225 intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd);
228 static const char *cmd_status_names[] = {
234 "Target not specified",
235 "Scaling not supported"
238 static u8 intel_sdvo_read_response(struct intel_output *intel_output, void *response,
241 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
247 /* Read the command response */
248 for (i = 0; i < response_len; i++) {
249 intel_sdvo_read_byte(intel_output, SDVO_I2C_RETURN_0 + i,
250 &((u8 *)response)[i]);
253 /* read the return status */
254 intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS, &status);
257 DRM_DEBUG("%s: R: ", SDVO_NAME(sdvo_priv));
258 for (i = 0; i < response_len; i++)
259 printk("%02X ", ((u8 *)response)[i]);
262 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
263 printk("(%s)", cmd_status_names[status]);
265 printk("(??? %d)", status);
269 if (status != SDVO_CMD_STATUS_PENDING)
278 int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
280 if (mode->clock >= 100000)
282 else if (mode->clock >= 50000)
289 * Don't check status code from this as it switches the bus back to the
290 * SDVO chips which defeats the purpose of doing a bus switch in the first
293 void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output, u8 target)
295 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1);
298 static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
300 struct intel_sdvo_set_target_input_args targets = {0};
303 if (target_0 && target_1)
304 return SDVO_CMD_STATUS_NOTSUPP;
307 targets.target_1 = 1;
309 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets,
312 status = intel_sdvo_read_response(intel_output, NULL, 0);
314 return (status == SDVO_CMD_STATUS_SUCCESS);
318 * Return whether each input is trained.
320 * This function is making an assumption about the layout of the response,
321 * which should be checked against the docs.
323 static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2)
325 struct intel_sdvo_get_trained_inputs_response response;
328 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
329 status = intel_sdvo_read_response(intel_output, &response, sizeof(response));
330 if (status != SDVO_CMD_STATUS_SUCCESS)
333 *input_1 = response.input0_trained;
334 *input_2 = response.input1_trained;
338 static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output,
343 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
344 status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs));
346 return (status == SDVO_CMD_STATUS_SUCCESS);
349 static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output,
354 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
356 status = intel_sdvo_read_response(intel_output, NULL, 0);
357 return (status == SDVO_CMD_STATUS_SUCCESS);
360 static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output,
363 u8 status, state = SDVO_ENCODER_STATE_ON;
367 state = SDVO_ENCODER_STATE_ON;
369 case DPMSModeStandby:
370 state = SDVO_ENCODER_STATE_STANDBY;
372 case DPMSModeSuspend:
373 state = SDVO_ENCODER_STATE_SUSPEND;
376 state = SDVO_ENCODER_STATE_OFF;
380 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
382 status = intel_sdvo_read_response(intel_output, NULL, 0);
384 return (status == SDVO_CMD_STATUS_SUCCESS);
387 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output,
391 struct intel_sdvo_pixel_clock_range clocks;
394 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
397 status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks));
399 if (status != SDVO_CMD_STATUS_SUCCESS)
402 /* Convert the values from units of 10 kHz to kHz. */
403 *clock_min = clocks.min * 10;
404 *clock_max = clocks.max * 10;
409 static bool intel_sdvo_set_target_output(struct intel_output *intel_output,
414 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
417 status = intel_sdvo_read_response(intel_output, NULL, 0);
418 return (status == SDVO_CMD_STATUS_SUCCESS);
421 static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd,
422 struct intel_sdvo_dtd *dtd)
426 intel_sdvo_write_cmd(intel_output, cmd, NULL, 0);
427 status = intel_sdvo_read_response(intel_output, &dtd->part1,
429 if (status != SDVO_CMD_STATUS_SUCCESS)
432 intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0);
433 status = intel_sdvo_read_response(intel_output, &dtd->part2,
435 if (status != SDVO_CMD_STATUS_SUCCESS)
441 static bool intel_sdvo_get_input_timing(struct intel_output *intel_output,
442 struct intel_sdvo_dtd *dtd)
444 return intel_sdvo_get_timing(intel_output,
445 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
448 static bool intel_sdvo_get_output_timing(struct intel_output *intel_output,
449 struct intel_sdvo_dtd *dtd)
451 return intel_sdvo_get_timing(intel_output,
452 SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
455 static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd,
456 struct intel_sdvo_dtd *dtd)
460 intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1));
461 status = intel_sdvo_read_response(intel_output, NULL, 0);
462 if (status != SDVO_CMD_STATUS_SUCCESS)
465 intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
466 status = intel_sdvo_read_response(intel_output, NULL, 0);
467 if (status != SDVO_CMD_STATUS_SUCCESS)
473 static bool intel_sdvo_set_input_timing(struct intel_output *intel_output,
474 struct intel_sdvo_dtd *dtd)
476 return intel_sdvo_set_timing(intel_output,
477 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
480 static bool intel_sdvo_set_output_timing(struct intel_output *intel_output,
481 struct intel_sdvo_dtd *dtd)
483 return intel_sdvo_set_timing(intel_output,
484 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
488 static bool intel_sdvo_get_preferred_input_timing(struct intel_output *intel_output,
489 struct intel_sdvo_dtd *dtd)
491 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
494 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
497 status = intel_sdvo_read_response(intel_output, &dtd->part1,
499 if (status != SDVO_CMD_STATUS_SUCCESS)
502 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
504 status = intel_sdvo_read_response(intel_output, &dtd->part2,
506 if (status != SDVO_CMD_STATUS_SUCCESS)
513 static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
517 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
518 status = intel_sdvo_read_response(intel_output, &response, 1);
520 if (status != SDVO_CMD_STATUS_SUCCESS) {
521 DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n");
522 return SDVO_CLOCK_RATE_MULT_1X;
524 DRM_DEBUG("Current clock rate multiplier: %d\n", response);
530 static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val)
534 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
535 status = intel_sdvo_read_response(intel_output, NULL, 0);
536 if (status != SDVO_CMD_STATUS_SUCCESS)
542 static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
543 struct drm_display_mode *mode,
544 struct drm_display_mode *adjusted_mode)
546 /* Make the CRTC code factor in the SDVO pixel multiplier. The SDVO
547 * device will be told of the multiplier during mode_set.
549 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
553 static void intel_sdvo_mode_set(struct drm_encoder *encoder,
554 struct drm_display_mode *mode,
555 struct drm_display_mode *adjusted_mode)
557 struct drm_device *dev = encoder->dev;
558 struct drm_i915_private *dev_priv = dev->dev_private;
559 struct drm_crtc *crtc = encoder->crtc;
560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
561 struct intel_output *intel_output = enc_to_intel_output(encoder);
562 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
564 u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len;
565 u16 h_sync_offset, v_sync_offset;
567 struct intel_sdvo_dtd output_dtd;
568 int sdvo_pixel_multiply;
573 width = mode->crtc_hdisplay;
574 height = mode->crtc_vdisplay;
576 /* do some mode translations */
577 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
578 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
580 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
581 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
583 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
584 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
586 output_dtd.part1.clock = mode->clock / 10;
587 output_dtd.part1.h_active = width & 0xff;
588 output_dtd.part1.h_blank = h_blank_len & 0xff;
589 output_dtd.part1.h_high = (((width >> 8) & 0xf) << 4) |
590 ((h_blank_len >> 8) & 0xf);
591 output_dtd.part1.v_active = height & 0xff;
592 output_dtd.part1.v_blank = v_blank_len & 0xff;
593 output_dtd.part1.v_high = (((height >> 8) & 0xf) << 4) |
594 ((v_blank_len >> 8) & 0xf);
596 output_dtd.part2.h_sync_off = h_sync_offset;
597 output_dtd.part2.h_sync_width = h_sync_len & 0xff;
598 output_dtd.part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
600 output_dtd.part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
601 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
602 ((v_sync_len & 0x30) >> 4);
604 output_dtd.part2.dtd_flags = 0x18;
605 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
606 output_dtd.part2.dtd_flags |= 0x2;
607 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
608 output_dtd.part2.dtd_flags |= 0x4;
610 output_dtd.part2.sdvo_flags = 0;
611 output_dtd.part2.v_sync_off_high = v_sync_offset & 0xc0;
612 output_dtd.part2.reserved = 0;
614 /* Set the output timing to the screen */
615 intel_sdvo_set_target_output(intel_output, sdvo_priv->active_outputs);
616 intel_sdvo_set_output_timing(intel_output, &output_dtd);
618 /* Set the input timing to the screen. Assume always input 0. */
619 intel_sdvo_set_target_input(intel_output, true, false);
621 /* We would like to use i830_sdvo_create_preferred_input_timing() to
622 * provide the device with a timing it can support, if it supports that
623 * feature. However, presumably we would need to adjust the CRTC to
624 * output the preferred timing, and we don't support that currently.
627 success = intel_sdvo_create_preferred_input_timing(intel_output, clock,
630 struct intel_sdvo_dtd *input_dtd;
632 intel_sdvo_get_preferred_input_timing(intel_output, &input_dtd);
633 intel_sdvo_set_input_timing(intel_output, &input_dtd);
636 intel_sdvo_set_input_timing(intel_output, &output_dtd);
639 switch (intel_sdvo_get_pixel_multiplier(mode)) {
641 intel_sdvo_set_clock_rate_mult(intel_output,
642 SDVO_CLOCK_RATE_MULT_1X);
645 intel_sdvo_set_clock_rate_mult(intel_output,
646 SDVO_CLOCK_RATE_MULT_2X);
649 intel_sdvo_set_clock_rate_mult(intel_output,
650 SDVO_CLOCK_RATE_MULT_4X);
654 /* Set the SDVO control regs. */
655 if (0/*IS_I965GM(dev)*/) {
656 sdvox = SDVO_BORDER_ENABLE;
658 sdvox = I915_READ(sdvo_priv->output_device);
659 switch (sdvo_priv->output_device) {
661 sdvox &= SDVOB_PRESERVE_MASK;
664 sdvox &= SDVOC_PRESERVE_MASK;
667 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
669 if (intel_crtc->pipe == 1)
670 sdvox |= SDVO_PIPE_B_SELECT;
672 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
674 /* done in crtc_mode_set as the dpll_md reg must be written
676 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
677 /* done in crtc_mode_set as it lives inside the
680 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
683 intel_sdvo_write_sdvox(intel_output, sdvox);
686 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
688 struct drm_device *dev = encoder->dev;
689 struct drm_i915_private *dev_priv = dev->dev_private;
690 struct intel_output *intel_output = enc_to_intel_output(encoder);
691 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
694 if (mode != DPMSModeOn) {
695 intel_sdvo_set_active_outputs(intel_output, 0);
697 intel_sdvo_set_encoder_power_state(intel_output, mode);
699 if (mode == DPMSModeOff) {
700 temp = I915_READ(sdvo_priv->output_device);
701 if ((temp & SDVO_ENABLE) != 0) {
702 intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE);
710 temp = I915_READ(sdvo_priv->output_device);
711 if ((temp & SDVO_ENABLE) == 0)
712 intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE);
713 for (i = 0; i < 2; i++)
714 intel_wait_for_vblank(dev);
716 status = intel_sdvo_get_trained_inputs(intel_output, &input1,
720 /* Warn if the device reported failure to sync.
721 * A lot of SDVO devices fail to notify of sync, but it's
722 * a given it the status is a success, we succeeded.
724 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
725 DRM_DEBUG("First %s output reported failure to sync\n",
726 SDVO_NAME(sdvo_priv));
730 intel_sdvo_set_encoder_power_state(intel_output, mode);
731 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->active_outputs);
736 static void intel_sdvo_save(struct drm_connector *connector)
738 struct drm_device *dev = connector->dev;
739 struct drm_i915_private *dev_priv = dev->dev_private;
740 struct intel_output *intel_output = to_intel_output(connector);
741 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
744 sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output);
745 intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs);
747 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
748 intel_sdvo_set_target_input(intel_output, true, false);
749 intel_sdvo_get_input_timing(intel_output,
750 &sdvo_priv->save_input_dtd_1);
753 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
754 intel_sdvo_set_target_input(intel_output, false, true);
755 intel_sdvo_get_input_timing(intel_output,
756 &sdvo_priv->save_input_dtd_2);
759 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
761 u16 this_output = (1 << o);
762 if (sdvo_priv->caps.output_flags & this_output)
764 intel_sdvo_set_target_output(intel_output, this_output);
765 intel_sdvo_get_output_timing(intel_output,
766 &sdvo_priv->save_output_dtd[o]);
770 sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);
773 static void intel_sdvo_restore(struct drm_connector *connector)
775 struct drm_device *dev = connector->dev;
776 struct drm_i915_private *dev_priv = dev->dev_private;
777 struct intel_output *intel_output = to_intel_output(connector);
778 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
784 intel_sdvo_set_active_outputs(intel_output, 0);
786 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
788 u16 this_output = (1 << o);
789 if (sdvo_priv->caps.output_flags & this_output) {
790 intel_sdvo_set_target_output(intel_output, this_output);
791 intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]);
795 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
796 intel_sdvo_set_target_input(intel_output, true, false);
797 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1);
800 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
801 intel_sdvo_set_target_input(intel_output, false, true);
802 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2);
805 intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult);
807 I915_WRITE(sdvo_priv->output_device, sdvo_priv->save_SDVOX);
809 if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
811 for (i = 0; i < 2; i++)
812 intel_wait_for_vblank(dev);
813 status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
814 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
815 DRM_DEBUG("First %s output reported failure to sync\n",
816 SDVO_NAME(sdvo_priv));
819 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
822 static int intel_sdvo_mode_valid(struct drm_connector *connector,
823 struct drm_display_mode *mode)
825 struct intel_output *intel_output = to_intel_output(connector);
826 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
828 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
829 return MODE_NO_DBLESCAN;
831 if (sdvo_priv->pixel_clock_min > mode->clock)
832 return MODE_CLOCK_LOW;
834 if (sdvo_priv->pixel_clock_max < mode->clock)
835 return MODE_CLOCK_HIGH;
840 static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps)
844 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
845 status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps));
846 if (status != SDVO_CMD_STATUS_SUCCESS)
852 struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
854 struct drm_connector *connector = NULL;
855 struct intel_output *iout = NULL;
856 struct intel_sdvo_priv *sdvo;
858 /* find the sdvo connector */
859 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
860 iout = to_intel_output(connector);
862 if (iout->type != INTEL_OUTPUT_SDVO)
865 sdvo = iout->dev_priv;
867 if (sdvo->output_device == SDVOB && sdvoB)
870 if (sdvo->output_device == SDVOC && !sdvoB)
878 int intel_sdvo_supports_hotplug(struct drm_connector *connector)
882 struct intel_output *intel_output;
888 intel_output = to_intel_output(connector);
890 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
891 status = intel_sdvo_read_response(intel_output, &response, 2);
899 void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
903 struct intel_output *intel_output = to_intel_output(connector);
905 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
906 intel_sdvo_read_response(intel_output, &response, 2);
909 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
910 status = intel_sdvo_read_response(intel_output, &response, 2);
912 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
916 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
919 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
920 intel_sdvo_read_response(intel_output, &response, 2);
923 static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
927 struct intel_output *intel_output = to_intel_output(connector);
929 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
930 status = intel_sdvo_read_response(intel_output, &response, 2);
932 DRM_DEBUG("SDVO response %d %d\n", response[0], response[1]);
933 if ((response[0] != 0) || (response[1] != 0))
934 return connector_status_connected;
936 return connector_status_disconnected;
939 static int intel_sdvo_get_modes(struct drm_connector *connector)
941 struct intel_output *intel_output = to_intel_output(connector);
943 /* set the bus switch and get the modes */
944 intel_sdvo_set_control_bus_switch(intel_output, SDVO_CONTROL_BUS_DDC2);
945 intel_ddc_get_modes(intel_output);
947 if (list_empty(&connector->probed_modes))
951 /* Mac mini hack. On this device, I get DDC through the analog, which
952 * load-detects as disconnected. I fail to DDC through the SDVO DDC,
953 * but it does load-detect as connected. So, just steal the DDC bits
954 * from analog when we fail at finding it the right way.
963 static void intel_sdvo_destroy(struct drm_connector *connector)
965 struct intel_output *intel_output = to_intel_output(connector);
967 if (intel_output->i2c_bus)
968 intel_i2c_destroy(intel_output->i2c_bus);
969 drm_sysfs_connector_remove(connector);
970 drm_connector_cleanup(connector);
974 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
975 .dpms = intel_sdvo_dpms,
976 .mode_fixup = intel_sdvo_mode_fixup,
977 .prepare = intel_encoder_prepare,
978 .mode_set = intel_sdvo_mode_set,
979 .commit = intel_encoder_commit,
982 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
983 .save = intel_sdvo_save,
984 .restore = intel_sdvo_restore,
985 .detect = intel_sdvo_detect,
986 .fill_modes = drm_helper_probe_single_connector_modes,
987 .destroy = intel_sdvo_destroy,
990 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
991 .get_modes = intel_sdvo_get_modes,
992 .mode_valid = intel_sdvo_mode_valid,
993 .best_encoder = intel_best_encoder,
996 void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
998 drm_encoder_cleanup(encoder);
1001 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1002 .destroy = intel_sdvo_enc_destroy,
1006 void intel_sdvo_init(struct drm_device *dev, int output_device)
1008 struct drm_connector *connector;
1009 struct intel_output *intel_output;
1010 struct intel_sdvo_priv *sdvo_priv;
1011 struct intel_i2c_chan *i2cbus = NULL;
1015 int encoder_type, output_id;
1017 intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
1018 if (!intel_output) {
1022 connector = &intel_output->base;
1024 drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
1025 DRM_MODE_CONNECTOR_Unknown);
1026 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
1027 sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
1028 intel_output->type = INTEL_OUTPUT_SDVO;
1030 connector->interlace_allowed = 0;
1031 connector->doublescan_allowed = 0;
1033 /* setup the DDC bus. */
1034 if (output_device == SDVOB)
1035 i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
1037 i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
1042 sdvo_priv->i2c_bus = i2cbus;
1044 if (output_device == SDVOB) {
1046 sdvo_priv->i2c_bus->slave_addr = 0x38;
1049 sdvo_priv->i2c_bus->slave_addr = 0x39;
1052 sdvo_priv->output_device = output_device;
1053 intel_output->i2c_bus = i2cbus;
1054 intel_output->dev_priv = sdvo_priv;
1057 /* Read the regs to test if we can talk to the device */
1058 for (i = 0; i < 0x40; i++) {
1059 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
1060 DRM_DEBUG("No SDVO device found on SDVO%c\n",
1061 output_device == SDVOB ? 'B' : 'C');
1066 intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
1068 memset(&sdvo_priv->active_outputs, 0, sizeof(sdvo_priv->active_outputs));
1070 /* TODO, CVBS, SVID, YPRPB & SCART outputs. */
1071 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB0)
1073 sdvo_priv->active_outputs = SDVO_OUTPUT_RGB0;
1074 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1075 encoder_type = DRM_MODE_ENCODER_DAC;
1076 connector_type = DRM_MODE_CONNECTOR_VGA;
1078 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB1)
1080 sdvo_priv->active_outputs = SDVO_OUTPUT_RGB1;
1081 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1082 encoder_type = DRM_MODE_ENCODER_DAC;
1083 connector_type = DRM_MODE_CONNECTOR_VGA;
1085 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
1087 sdvo_priv->active_outputs = SDVO_OUTPUT_TMDS0;
1088 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1089 encoder_type = DRM_MODE_ENCODER_TMDS;
1090 connector_type = DRM_MODE_CONNECTOR_DVID;
1092 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS1)
1094 sdvo_priv->active_outputs = SDVO_OUTPUT_TMDS1;
1095 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1096 encoder_type = DRM_MODE_ENCODER_TMDS;
1097 connector_type = DRM_MODE_CONNECTOR_DVID;
1101 unsigned char bytes[2];
1103 memcpy (bytes, &sdvo_priv->caps.output_flags, 2);
1104 DRM_DEBUG("%s: No active RGB or TMDS outputs (0x%02x%02x)\n",
1105 SDVO_NAME(sdvo_priv),
1106 bytes[0], bytes[1]);
1110 drm_encoder_init(dev, &intel_output->enc, &intel_sdvo_enc_funcs, encoder_type);
1111 drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
1112 connector->connector_type = connector_type;
1114 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
1115 drm_sysfs_connector_add(connector);
1117 /* Set the input timing to the screen. Assume always input 0. */
1118 intel_sdvo_set_target_input(intel_output, true, false);
1120 intel_sdvo_get_input_pixel_clock_range(intel_output,
1121 &sdvo_priv->pixel_clock_min,
1122 &sdvo_priv->pixel_clock_max);
1125 DRM_DEBUG("%s device VID/DID: %02X:%02X.%02X, "
1126 "clock range %dMHz - %dMHz, "
1127 "input 1: %c, input 2: %c, "
1128 "output 1: %c, output 2: %c\n",
1129 SDVO_NAME(sdvo_priv),
1130 sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
1131 sdvo_priv->caps.device_rev_id,
1132 sdvo_priv->pixel_clock_min / 1000,
1133 sdvo_priv->pixel_clock_max / 1000,
1134 (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
1135 (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
1136 /* check currently supported outputs */
1137 sdvo_priv->caps.output_flags &
1138 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
1139 sdvo_priv->caps.output_flags &
1140 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
1142 intel_output->ddc_bus = i2cbus;
1147 intel_i2c_destroy(intel_output->i2c_bus);
1149 drm_connector_cleanup(connector);
1150 kfree(intel_output);