linux-core/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_compat.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33 #include <linux/swap.h>
  34
  35 static int
  36 i915_gem_object_set_domain_range(struct drm_gem_object *obj,
  37                                  uint64_t offset,
  38                                  uint64_t size,
  39                                  uint32_t read_domains,
  40                                  uint32_t write_domain);
  41 int
  42 i915_gem_set_domain(struct drm_gem_object *obj,
  43                     struct drm_file *file_priv,
  44                     uint32_t read_domains,
  45                     uint32_t write_domain);
  46 static int i915_gem_object_get_page_list(struct drm_gem_object *obj);
  47 static void i915_gem_object_free_page_list(struct drm_gem_object *obj);
  48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
  49
  50 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
  51                      unsigned long end)
  52 {
  53         struct drm_i915_private *dev_priv = dev->dev_private;
  54
  55         if (start >= end ||
  56             (start & (PAGE_SIZE - 1)) != 0 ||
  57             (end & (PAGE_SIZE - 1)) != 0) {
  58                 return -EINVAL;
  59         }
  60
  61         drm_mm_init(&dev_priv->mm.gtt_space, start,
  62                     end - start);
  63
  64         dev->gtt_total = (uint32_t) (end - start);
  65
  66         return 0;
  67 }
  68
  69 int
  70 i915_gem_init_ioctl(struct drm_device *dev, void *data,
  71                     struct drm_file *file_priv)
  72 {
  73         struct drm_i915_gem_init *args = data;
  74         int ret;
  75
  76         mutex_lock(&dev->struct_mutex);
  77         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
  78         mutex_unlock(&dev->struct_mutex);
  79
  80         return ret;
  81 }
  82
  83
  84 /**
  85  * Creates a new mm object and returns a handle to it.
  86  */
  87 int
  88 i915_gem_create_ioctl(struct drm_device *dev, void *data,
  89                       struct drm_file *file_priv)
  90 {
  91         struct drm_i915_gem_create *args = data;
  92         struct drm_gem_object *obj;
  93         int handle, ret;
  94
  95         args->size = roundup(args->size, PAGE_SIZE);
  96
  97         /* Allocate the new object */
  98         obj = drm_gem_object_alloc(dev, args->size);
  99         if (obj == NULL)
 100                 return -ENOMEM;
 101
 102         ret = drm_gem_handle_create(file_priv, obj, &handle);
 103         mutex_lock(&dev->struct_mutex);
 104         drm_gem_object_handle_unreference(obj);
 105         mutex_unlock(&dev->struct_mutex);
 106
 107         if (ret)
 108                 return ret;
 109
 110         args->handle = handle;
 111
 112         return 0;
 113 }
 114
 115 /**
 116  * Reads data from the object referenced by handle.
 117  *
 118  * On error, the contents of *data are undefined.
 119  */
 120 int
 121 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 122                      struct drm_file *file_priv)
 123 {
 124         struct drm_i915_gem_pread *args = data;
 125         struct drm_gem_object *obj;
 126         struct drm_i915_gem_object *obj_priv;
 127         ssize_t read;
 128         loff_t offset;
 129         int ret;
 130
 131         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 132         if (obj == NULL)
 133                 return -EBADF;
 134         obj_priv = obj->driver_private;
 135
 136         /* Bounds check source.
 137          *
 138          * XXX: This could use review for overflow issues...
 139          */
 140         if (args->offset > obj->size || args->size > obj->size ||
 141             args->offset + args->size > obj->size) {
 142                 drm_gem_object_unreference(obj);
 143                 return -EINVAL;
 144         }
 145
 146         mutex_lock(&dev->struct_mutex);
 147
 148         ret = i915_gem_object_set_domain_range(obj, args->offset, args->size,
 149                                                I915_GEM_DOMAIN_CPU, 0);
 150         if (ret != 0) {
 151                 drm_gem_object_unreference(obj);
 152                 mutex_unlock(&dev->struct_mutex);
 153         }
 154
 155         offset = args->offset;
 156
 157         read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr,
 158                         args->size, &offset);
 159         if (read != args->size) {
 160                 drm_gem_object_unreference(obj);
 161                 mutex_unlock(&dev->struct_mutex);
 162                 if (read < 0)
 163                         return read;
 164                 else
 165                         return -EINVAL;
 166         }
 167
 168         drm_gem_object_unreference(obj);
 169         mutex_unlock(&dev->struct_mutex);
 170
 171         return 0;
 172 }
 173
 174 #include "drm_compat.h"
 175
 176 static int
 177 i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
 178                     struct drm_i915_gem_pwrite *args,
 179                     struct drm_file *file_priv)
 180 {
 181         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 182         ssize_t remain;
 183         loff_t offset;
 184         char __user *user_data;
 185         char *vaddr;
 186         int i, o, l;
 187         int ret = 0;
 188         unsigned long pfn;
 189         unsigned long unwritten;
 190
 191         user_data = (char __user *) (uintptr_t) args->data_ptr;
 192         remain = args->size;
 193         if (!access_ok(VERIFY_READ, user_data, remain))
 194                 return -EFAULT;
 195
 196
 197         mutex_lock(&dev->struct_mutex);
 198         ret = i915_gem_object_pin(obj, 0);
 199         if (ret) {
 200                 mutex_unlock(&dev->struct_mutex);
 201                 return ret;
 202         }
 203         ret = i915_gem_set_domain(obj, file_priv,
 204                                   I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
 205         if (ret)
 206                 goto fail;
 207
 208         obj_priv = obj->driver_private;
 209         offset = obj_priv->gtt_offset + args->offset;
 210         obj_priv->dirty = 1;
 211
 212         while (remain > 0) {
 213                 /* Operation in this page
 214                  *
 215                  * i = page number
 216                  * o = offset within page
 217                  * l = bytes to copy
 218                  */
 219                 i = offset >> PAGE_SHIFT;
 220                 o = offset & (PAGE_SIZE-1);
 221                 l = remain;
 222                 if ((o + l) > PAGE_SIZE)
 223                         l = PAGE_SIZE - o;
 224
 225                 pfn = (dev->agp->base >> PAGE_SHIFT) + i;
 226
 227 #ifdef DRM_KMAP_ATOMIC_PROT_PFN
 228                 /* kmap_atomic can't map IO pages on non-HIGHMEM kernels
 229                  */
 230                 vaddr = kmap_atomic_prot_pfn(pfn, KM_USER0,
 231                                              __pgprot(__PAGE_KERNEL));
 232 #if WATCH_PWRITE
 233                 DRM_INFO("pwrite i %d o %d l %d pfn %ld vaddr %p\n",
 234                          i, o, l, pfn, vaddr);
 235 #endif
 236                 unwritten = __copy_from_user_inatomic_nocache(vaddr + o,
 237                                                               user_data, l);
 238                 kunmap_atomic(vaddr, KM_USER0);
 239
 240                 if (unwritten)
 241 #endif
 242                 {
 243                         vaddr = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
 244 #if WATCH_PWRITE
 245                         DRM_INFO("pwrite slow i %d o %d l %d "
 246                                  "pfn %ld vaddr %p\n",
 247                                  i, o, l, pfn, vaddr);
 248 #endif
 249                         if (vaddr == NULL) {
 250                                 ret = -EFAULT;
 251                                 goto fail;
 252                         }
 253                         unwritten = __copy_from_user(vaddr + o, user_data, l);
 254 #if WATCH_PWRITE
 255                         DRM_INFO("unwritten %ld\n", unwritten);
 256 #endif
 257                         iounmap(vaddr);
 258                         if (unwritten) {
 259                                 ret = -EFAULT;
 260                                 goto fail;
 261                         }
 262                 }
 263
 264                 remain -= l;
 265                 user_data += l;
 266                 offset += l;
 267         }
 268 #if WATCH_PWRITE && 1
 269         i915_gem_clflush_object(obj);
 270         i915_gem_dump_object(obj, args->offset + args->size, __func__, ~0);
 271         i915_gem_clflush_object(obj);
 272 #endif
 273
 274 fail:
 275         i915_gem_object_unpin(obj);
 276         mutex_unlock(&dev->struct_mutex);
 277
 278         return ret;
 279 }
 280
 281 int
 282 i915_gem_shmem_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
 283                       struct drm_i915_gem_pwrite *args,
 284                       struct drm_file *file_priv)
 285 {
 286         int ret;
 287         loff_t offset;
 288         ssize_t written;
 289
 290         mutex_lock(&dev->struct_mutex);
 291
 292         ret = i915_gem_set_domain(obj, file_priv,
 293                                   I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
 294         if (ret) {
 295                 mutex_unlock(&dev->struct_mutex);
 296                 return ret;
 297         }
 298
 299         offset = args->offset;
 300
 301         written = vfs_write(obj->filp,
 302                             (char __user *)(uintptr_t) args->data_ptr,
 303                             args->size, &offset);
 304         if (written != args->size) {
 305                 mutex_unlock(&dev->struct_mutex);
 306                 if (written < 0)
 307                         return written;
 308                 else
 309                         return -EINVAL;
 310         }
 311
 312         mutex_unlock(&dev->struct_mutex);
 313
 314         return 0;
 315 }
 316
 317 /**
 318  * Writes data to the object referenced by handle.
 319  *
 320  * On error, the contents of the buffer that were to be modified are undefined.
 321  */
 322 int
 323 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 324                       struct drm_file *file_priv)
 325 {
 326         struct drm_i915_gem_pwrite *args = data;
 327         struct drm_gem_object *obj;
 328         struct drm_i915_gem_object *obj_priv;
 329         int ret = 0;
 330
 331         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 332         if (obj == NULL)
 333                 return -EBADF;
 334         obj_priv = obj->driver_private;
 335
 336         /* Bounds check destination.
 337          *
 338          * XXX: This could use review for overflow issues...
 339          */
 340         if (args->offset > obj->size || args->size > obj->size ||
 341             args->offset + args->size > obj->size) {
 342                 drm_gem_object_unreference(obj);
 343                 return -EINVAL;
 344         }
 345
 346         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 347          * it would end up going through the fenced access, and we'll get
 348          * different detiling behavior between reading and writing.
 349          * pread/pwrite currently are reading and writing from the CPU
 350          * perspective, requiring manual detiling by the client.
 351          */
 352         if (obj_priv->tiling_mode == I915_TILING_NONE &&
 353             dev->gtt_total != 0)
 354                 ret = i915_gem_gtt_pwrite(dev, obj, args, file_priv);
 355         else
 356                 ret = i915_gem_shmem_pwrite(dev, obj, args, file_priv);
 357
 358 #if WATCH_PWRITE
 359         if (ret)
 360                 DRM_INFO("pwrite failed %d\n", ret);
 361 #endif
 362
 363         drm_gem_object_unreference(obj);
 364
 365         return ret;
 366 }
 367
 368 /**
 369  * Called when user space prepares to use an object
 370  */
 371 int
 372 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 373                           struct drm_file *file_priv)
 374 {
 375         struct drm_i915_gem_set_domain *args = data;
 376         struct drm_gem_object *obj;
 377         int ret;
 378
 379         if (!(dev->driver->driver_features & DRIVER_GEM))
 380                 return -ENODEV;
 381
 382         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 383         if (obj == NULL)
 384                 return -EBADF;
 385
 386         mutex_lock(&dev->struct_mutex);
 387 #if WATCH_BUF
 388         DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
 389                  obj, obj->size, args->read_domains, args->write_domain);
 390 #endif
 391         ret = i915_gem_set_domain(obj, file_priv,
 392                                   args->read_domains, args->write_domain);
 393         drm_gem_object_unreference(obj);
 394         mutex_unlock(&dev->struct_mutex);
 395         return ret;
 396 }
 397
 398 /**
 399  * Called when user space has done writes to this buffer
 400  */
 401 int
 402 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
 403                       struct drm_file *file_priv)
 404 {
 405         struct drm_i915_gem_sw_finish *args = data;
 406         struct drm_gem_object *obj;
 407         struct drm_i915_gem_object *obj_priv;
 408         int ret = 0;
 409
 410         if (!(dev->driver->driver_features & DRIVER_GEM))
 411                 return -ENODEV;
 412
 413         mutex_lock(&dev->struct_mutex);
 414         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 415         if (obj == NULL) {
 416                 mutex_unlock(&dev->struct_mutex);
 417                 return -EBADF;
 418         }
 419
 420 #if WATCH_BUF
 421         DRM_INFO("%s: sw_finish %d (%p %d)\n",
 422                  __func__, args->handle, obj, obj->size);
 423 #endif
 424         obj_priv = obj->driver_private;
 425
 426         /* Pinned buffers may be scanout, so flush the cache */
 427         if ((obj->write_domain & I915_GEM_DOMAIN_CPU) && obj_priv->pin_count) {
 428                 i915_gem_clflush_object(obj);
 429                 drm_agp_chipset_flush(dev);
 430         }
 431         drm_gem_object_unreference(obj);
 432         mutex_unlock(&dev->struct_mutex);
 433         return ret;
 434 }
 435
 436 /**
 437  * Maps the contents of an object, returning the address it is mapped
 438  * into.
 439  *
 440  * While the mapping holds a reference on the contents of the object, it doesn't
 441  * imply a ref on the object itself.
 442  */
 443 int
 444 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 445                    struct drm_file *file_priv)
 446 {
 447         struct drm_i915_gem_mmap *args = data;
 448         struct drm_gem_object *obj;
 449         loff_t offset;
 450         unsigned long addr;
 451
 452         if (!(dev->driver->driver_features & DRIVER_GEM))
 453                 return -ENODEV;
 454
 455         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 456         if (obj == NULL)
 457                 return -EBADF;
 458
 459         offset = args->offset;
 460
 461         down_write(&current->mm->mmap_sem);
 462         addr = do_mmap(obj->filp, 0, args->size,
 463                        PROT_READ | PROT_WRITE, MAP_SHARED,
 464                        args->offset);
 465         up_write(&current->mm->mmap_sem);
 466         mutex_lock(&dev->struct_mutex);
 467         drm_gem_object_unreference(obj);
 468         mutex_unlock(&dev->struct_mutex);
 469         if (IS_ERR((void *)addr))
 470                 return addr;
 471
 472         args->addr_ptr = (uint64_t) addr;
 473
 474         return 0;
 475 }
 476
 477 static void
 478 i915_gem_object_free_page_list(struct drm_gem_object *obj)
 479 {
 480         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 481         int page_count = obj->size / PAGE_SIZE;
 482         int i;
 483
 484         if (obj_priv->page_list == NULL)
 485                 return;
 486
 487
 488         for (i = 0; i < page_count; i++)
 489                 if (obj_priv->page_list[i] != NULL) {
 490                         if (obj_priv->dirty)
 491                                 set_page_dirty(obj_priv->page_list[i]);
 492                         mark_page_accessed(obj_priv->page_list[i]);
 493                         page_cache_release(obj_priv->page_list[i]);
 494                 }
 495         obj_priv->dirty = 0;
 496
 497         drm_free(obj_priv->page_list,
 498                  page_count * sizeof(struct page *),
 499                  DRM_MEM_DRIVER);
 500         obj_priv->page_list = NULL;
 501 }
 502
 503 static void
 504 i915_gem_object_move_to_active(struct drm_gem_object *obj)
 505 {
 506         struct drm_device *dev = obj->dev;
 507         struct drm_i915_private *dev_priv = dev->dev_private;
 508         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 509
 510         /* Add a reference if we're newly entering the active list. */
 511         if (!obj_priv->active) {
 512                 drm_gem_object_reference(obj);
 513                 obj_priv->active = 1;
 514         }
 515         /* Move from whatever list we were on to the tail of execution. */
 516         list_move_tail(&obj_priv->list,
 517                        &dev_priv->mm.active_list);
 518 }
 519
 520
 521 static void
 522 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
 523 {
 524         struct drm_device *dev = obj->dev;
 525         struct drm_i915_private *dev_priv = dev->dev_private;
 526         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 527
 528         i915_verify_inactive(dev, __FILE__, __LINE__);
 529         if (obj_priv->pin_count != 0)
 530                 list_del_init(&obj_priv->list);
 531         else
 532                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
 533
 534         if (obj_priv->active) {
 535                 obj_priv->active = 0;
 536                 drm_gem_object_unreference(obj);
 537         }
 538         i915_verify_inactive(dev, __FILE__, __LINE__);
 539 }
 540
 541 /**
 542  * Creates a new sequence number, emitting a write of it to the status page
 543  * plus an interrupt, which will trigger i915_user_interrupt_handler.
 544  *
 545  * Must be called with struct_lock held.
 546  *
 547  * Returned sequence numbers are nonzero on success.
 548  */
 549 static uint32_t
 550 i915_add_request(struct drm_device *dev, uint32_t flush_domains)
 551 {
 552         struct drm_i915_private *dev_priv = dev->dev_private;
 553         struct drm_i915_gem_request *request;
 554         uint32_t seqno;
 555         int was_empty;
 556         RING_LOCALS;
 557
 558         request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
 559         if (request == NULL)
 560                 return 0;
 561
 562         /* Grab the seqno we're going to make this request be, and bump the
 563          * next (skipping 0 so it can be the reserved no-seqno value).
 564          */
 565         seqno = dev_priv->mm.next_gem_seqno;
 566         dev_priv->mm.next_gem_seqno++;
 567         if (dev_priv->mm.next_gem_seqno == 0)
 568                 dev_priv->mm.next_gem_seqno++;
 569
 570         BEGIN_LP_RING(4);
 571         OUT_RING(MI_STORE_DWORD_INDEX);
 572         OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 573         OUT_RING(seqno);
 574
 575         OUT_RING(MI_USER_INTERRUPT);
 576         ADVANCE_LP_RING();
 577
 578         DRM_DEBUG("%d\n", seqno);
 579
 580         request->seqno = seqno;
 581         request->emitted_jiffies = jiffies;
 582         request->flush_domains = flush_domains;
 583         was_empty = list_empty(&dev_priv->mm.request_list);
 584         list_add_tail(&request->list, &dev_priv->mm.request_list);
 585
 586         if (was_empty)
 587                 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
 588         return seqno;
 589 }
 590
 591 /**
 592  * Command execution barrier
 593  *
 594  * Ensures that all commands in the ring are finished
 595  * before signalling the CPU
 596  */
 597 uint32_t
 598 i915_retire_commands(struct drm_device *dev)
 599 {
 600         struct drm_i915_private *dev_priv = dev->dev_private;
 601         uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 602         uint32_t flush_domains = 0;
 603         RING_LOCALS;
 604
 605         /* The sampler always gets flushed on i965 (sigh) */
 606         if (IS_I965G(dev))
 607                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
 608         BEGIN_LP_RING(2);
 609         OUT_RING(cmd);
 610         OUT_RING(0); /* noop */
 611         ADVANCE_LP_RING();
 612         return flush_domains;
 613 }
 614
 615 /**
 616  * Moves buffers associated only with the given active seqno from the active
 617  * to inactive list, potentially freeing them.
 618  */
 619 static void
 620 i915_gem_retire_request(struct drm_device *dev,
 621                         struct drm_i915_gem_request *request)
 622 {
 623         struct drm_i915_private *dev_priv = dev->dev_private;
 624
 625         if (request->flush_domains != 0) {
 626                 struct drm_i915_gem_object *obj_priv, *next;
 627
 628                 /* First clear any buffers that were only waiting for a flush
 629                  * matching the one just retired.
 630                  */
 631
 632                 list_for_each_entry_safe(obj_priv, next,
 633                                          &dev_priv->mm.flushing_list, list) {
 634                         struct drm_gem_object *obj = obj_priv->obj;
 635
 636                         if (obj->write_domain & request->flush_domains) {
 637                                 obj->write_domain = 0;
 638                                 i915_gem_object_move_to_inactive(obj);
 639                         }
 640                 }
 641
 642         }
 643
 644         /* Move any buffers on the active list that are no longer referenced
 645          * by the ringbuffer to the flushing/inactive lists as appropriate.
 646          */
 647         while (!list_empty(&dev_priv->mm.active_list)) {
 648                 struct drm_gem_object *obj;
 649                 struct drm_i915_gem_object *obj_priv;
 650
 651                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
 652                                             struct drm_i915_gem_object,
 653                                             list);
 654                 obj = obj_priv->obj;
 655
 656                 /* If the seqno being retired doesn't match the oldest in the
 657                  * list, then the oldest in the list must still be newer than
 658                  * this seqno.
 659                  */
 660                 if (obj_priv->last_rendering_seqno != request->seqno)
 661                         return;
 662 #if WATCH_LRU
 663                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
 664                          __func__, request->seqno, obj);
 665 #endif
 666
 667                 /* If this request flushes the write domain,
 668                  * clear the write domain from the object now
 669                  */
 670                 if (request->flush_domains & obj->write_domain)
 671                     obj->write_domain = 0;
 672
 673                 if (obj->write_domain != 0) {
 674                         list_move_tail(&obj_priv->list,
 675                                        &dev_priv->mm.flushing_list);
 676                 } else {
 677                         i915_gem_object_move_to_inactive(obj);
 678                 }
 679         }
 680 }
 681
 682 /**
 683  * Returns true if seq1 is later than seq2.
 684  */
 685 static int
 686 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
 687 {
 688         return (int32_t)(seq1 - seq2) >= 0;
 689 }
 690
 691 uint32_t
 692 i915_get_gem_seqno(struct drm_device *dev)
 693 {
 694         struct drm_i915_private *dev_priv = dev->dev_private;
 695
 696         return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
 697 }
 698
 699 /**
 700  * This function clears the request list as sequence numbers are passed.
 701  */
 702 void
 703 i915_gem_retire_requests(struct drm_device *dev)
 704 {
 705         struct drm_i915_private *dev_priv = dev->dev_private;
 706         uint32_t seqno;
 707
 708         seqno = i915_get_gem_seqno(dev);
 709
 710         while (!list_empty(&dev_priv->mm.request_list)) {
 711                 struct drm_i915_gem_request *request;
 712                 uint32_t retiring_seqno;
 713
 714                 request = list_first_entry(&dev_priv->mm.request_list,
 715                                            struct drm_i915_gem_request,
 716                                            list);
 717                 retiring_seqno = request->seqno;
 718
 719                 if (i915_seqno_passed(seqno, retiring_seqno) ||
 720                     dev_priv->mm.wedged) {
 721                         i915_gem_retire_request(dev, request);
 722
 723                         list_del(&request->list);
 724                         drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
 725                 } else
 726                         break;
 727         }
 728 }
 729
 730 void
 731 i915_gem_retire_work_handler(struct work_struct *work)
 732 {
 733         struct drm_i915_private *dev_priv;
 734         struct drm_device *dev;
 735
 736         dev_priv = container_of(work, struct drm_i915_private,
 737                                 mm.retire_work.work);
 738         dev = dev_priv->dev;
 739
 740         mutex_lock(&dev->struct_mutex);
 741         i915_gem_retire_requests(dev);
 742         if (!list_empty(&dev_priv->mm.request_list))
 743                 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
 744         mutex_unlock(&dev->struct_mutex);
 745 }
 746
 747 /**
 748  * Waits for a sequence number to be signaled, and cleans up the
 749  * request and object lists appropriately for that event.
 750  */
 751 int
 752 i915_wait_request(struct drm_device *dev, uint32_t seqno)
 753 {
 754         struct drm_i915_private *dev_priv = dev->dev_private;
 755         int ret = 0;
 756
 757         BUG_ON(seqno == 0);
 758
 759         if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
 760                 dev_priv->mm.waiting_gem_seqno = seqno;
 761                 i915_user_irq_on(dev);
 762                 ret = wait_event_interruptible(dev_priv->irq_queue,
 763                                                i915_seqno_passed(i915_get_gem_seqno(dev),
 764                                                                  seqno) ||
 765                                                dev_priv->mm.wedged);
 766                 i915_user_irq_off(dev);
 767                 dev_priv->mm.waiting_gem_seqno = 0;
 768         }
 769         if (dev_priv->mm.wedged)
 770                 ret = -EIO;
 771
 772         if (ret && ret != -ERESTARTSYS)
 773                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
 774                           __func__, ret, seqno, i915_get_gem_seqno(dev));
 775
 776         /* Directly dispatch request retiring.  While we have the work queue
 777          * to handle this, the waiter on a request often wants an associated
 778          * buffer to have made it to the inactive list, and we would need
 779          * a separate wait queue to handle that.
 780          */
 781         if (ret == 0)
 782                 i915_gem_retire_requests(dev);
 783
 784         return ret;
 785 }
 786
 787 static void
 788 i915_gem_flush(struct drm_device *dev,
 789                uint32_t invalidate_domains,
 790                uint32_t flush_domains)
 791 {
 792         struct drm_i915_private *dev_priv = dev->dev_private;
 793         uint32_t cmd;
 794         RING_LOCALS;
 795
 796 #if WATCH_EXEC
 797         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
 798                   invalidate_domains, flush_domains);
 799 #endif
 800
 801         if (flush_domains & I915_GEM_DOMAIN_CPU)
 802                 drm_agp_chipset_flush(dev);
 803
 804         if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU |
 805                                                      I915_GEM_DOMAIN_GTT)) {
 806                 /*
 807                  * read/write caches:
 808                  *
 809                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 810                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 811                  * also flushed at 2d versus 3d pipeline switches.
 812                  *
 813                  * read-only caches:
 814                  *
 815                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 816                  * MI_READ_FLUSH is set, and is always flushed on 965.
 817                  *
 818                  * I915_GEM_DOMAIN_COMMAND may not exist?
 819                  *
 820                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 821                  * invalidated when MI_EXE_FLUSH is set.
 822                  *
 823                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 824                  * invalidated with every MI_FLUSH.
 825                  *
 826                  * TLBs:
 827                  *
 828                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 829                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 830                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 831                  * are flushed at any MI_FLUSH.
 832                  */
 833
 834                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 835                 if ((invalidate_domains|flush_domains) &
 836                     I915_GEM_DOMAIN_RENDER)
 837                         cmd &= ~MI_NO_WRITE_FLUSH;
 838                 if (!IS_I965G(dev)) {
 839                         /*
 840                          * On the 965, the sampler cache always gets flushed
 841                          * and this bit is reserved.
 842                          */
 843                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 844                                 cmd |= MI_READ_FLUSH;
 845                 }
 846                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 847                         cmd |= MI_EXE_FLUSH;
 848
 849 #if WATCH_EXEC
 850                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
 851 #endif
 852                 BEGIN_LP_RING(2);
 853                 OUT_RING(cmd);
 854                 OUT_RING(0); /* noop */
 855                 ADVANCE_LP_RING();
 856         }
 857 }
 858
 859 /**
 860  * Ensures that all rendering to the object has completed and the object is
 861  * safe to unbind from the GTT or access from the CPU.
 862  */
 863 static int
 864 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
 865 {
 866         struct drm_device *dev = obj->dev;
 867         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 868         int ret;
 869         uint32_t write_domain;
 870
 871         /* If there are writes queued to the buffer, flush and
 872          * create a new seqno to wait for.
 873          */
 874         write_domain = obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT);
 875         if (write_domain) {
 876 #if WATCH_BUF
 877                 DRM_INFO("%s: flushing object %p from write domain %08x\n",
 878                           __func__, obj, write_domain);
 879 #endif
 880                 i915_gem_flush(dev, 0, write_domain);
 881
 882                 i915_gem_object_move_to_active(obj);
 883                 obj_priv->last_rendering_seqno = i915_add_request(dev,
 884                                                                   write_domain);
 885                 BUG_ON(obj_priv->last_rendering_seqno == 0);
 886 #if WATCH_LRU
 887                 DRM_INFO("%s: flush moves to exec list %p\n", __func__, obj);
 888 #endif
 889         }
 890
 891         /* If there is rendering queued on the buffer being evicted, wait for
 892          * it.
 893          */
 894         if (obj_priv->active) {
 895 #if WATCH_BUF
 896                 DRM_INFO("%s: object %p wait for seqno %08x\n",
 897                           __func__, obj, obj_priv->last_rendering_seqno);
 898 #endif
 899                 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
 900                 if (ret != 0)
 901                         return ret;
 902         }
 903
 904         return 0;
 905 }
 906
 907 /**
 908  * Unbinds an object from the GTT aperture.
 909  */
 910 static int
 911 i915_gem_object_unbind(struct drm_gem_object *obj)
 912 {
 913         struct drm_device *dev = obj->dev;
 914         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 915         int ret = 0;
 916
 917 #if WATCH_BUF
 918         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
 919         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
 920 #endif
 921         if (obj_priv->gtt_space == NULL)
 922                 return 0;
 923
 924         if (obj_priv->pin_count != 0) {
 925                 DRM_ERROR("Attempting to unbind pinned buffer\n");
 926                 return -EINVAL;
 927         }
 928
 929         /* Wait for any rendering to complete
 930          */
 931         ret = i915_gem_object_wait_rendering(obj);
 932         if (ret) {
 933                 DRM_ERROR("wait_rendering failed: %d\n", ret);
 934                 return ret;
 935         }
 936
 937         /* Move the object to the CPU domain to ensure that
 938          * any possible CPU writes while it's not in the GTT
 939          * are flushed when we go to remap it. This will
 940          * also ensure that all pending GPU writes are finished
 941          * before we unbind.
 942          */
 943         ret = i915_gem_object_set_domain(obj, I915_GEM_DOMAIN_CPU,
 944                                          I915_GEM_DOMAIN_CPU);
 945         if (ret) {
 946                 DRM_ERROR("set_domain failed: %d\n", ret);
 947                 return ret;
 948         }
 949
 950         if (obj_priv->agp_mem != NULL) {
 951                 drm_unbind_agp(obj_priv->agp_mem);
 952                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
 953                 obj_priv->agp_mem = NULL;
 954         }
 955
 956         BUG_ON(obj_priv->active);
 957
 958         i915_gem_object_free_page_list(obj);
 959
 960         if (obj_priv->gtt_space) {
 961                 atomic_dec(&dev->gtt_count);
 962                 atomic_sub(obj->size, &dev->gtt_memory);
 963
 964                 drm_mm_put_block(obj_priv->gtt_space);
 965                 obj_priv->gtt_space = NULL;
 966         }
 967
 968         /* Remove ourselves from the LRU list if present. */
 969         if (!list_empty(&obj_priv->list))
 970                 list_del_init(&obj_priv->list);
 971
 972         return 0;
 973 }
 974
 975 static int
 976 i915_gem_evict_something(struct drm_device *dev)
 977 {
 978         struct drm_i915_private *dev_priv = dev->dev_private;
 979         struct drm_gem_object *obj;
 980         struct drm_i915_gem_object *obj_priv;
 981         int ret = 0;
 982
 983         for (;;) {
 984                 /* If there's an inactive buffer available now, grab it
 985                  * and be done.
 986                  */
 987                 if (!list_empty(&dev_priv->mm.inactive_list)) {
 988                         obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
 989                                                     struct drm_i915_gem_object,
 990                                                     list);
 991                         obj = obj_priv->obj;
 992                         BUG_ON(obj_priv->pin_count != 0);
 993 #if WATCH_LRU
 994                         DRM_INFO("%s: evicting %p\n", __func__, obj);
 995 #endif
 996                         BUG_ON(obj_priv->active);
 997
 998                         /* Wait on the rendering and unbind the buffer. */
 999                         ret = i915_gem_object_unbind(obj);
1000                         break;
1001                 }
1002
1003                 /* If we didn't get anything, but the ring is still processing
1004                  * things, wait for one of those things to finish and hopefully
1005                  * leave us a buffer to evict.
1006                  */
1007                 if (!list_empty(&dev_priv->mm.request_list)) {
1008                         struct drm_i915_gem_request *request;
1009
1010                         request = list_first_entry(&dev_priv->mm.request_list,
1011                                                    struct drm_i915_gem_request,
1012                                                    list);
1013
1014                         ret = i915_wait_request(dev, request->seqno);
1015                         if (ret)
1016                                 break;
1017
1018                         /* if waiting caused an object to become inactive,
1019                          * then loop around and wait for it. Otherwise, we
1020                          * assume that waiting freed and unbound something,
1021                          * so there should now be some space in the GTT
1022                          */
1023                         if (!list_empty(&dev_priv->mm.inactive_list))
1024                                 continue;
1025                         break;
1026                 }
1027
1028                 /* If we didn't have anything on the request list but there
1029                  * are buffers awaiting a flush, emit one and try again.
1030                  * When we wait on it, those buffers waiting for that flush
1031                  * will get moved to inactive.
1032                  */
1033                 if (!list_empty(&dev_priv->mm.flushing_list)) {
1034                         obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1035                                                     struct drm_i915_gem_object,
1036                                                     list);
1037                         obj = obj_priv->obj;
1038
1039                         i915_gem_flush(dev,
1040                                        obj->write_domain,
1041                                        obj->write_domain);
1042                         i915_add_request(dev, obj->write_domain);
1043
1044                         obj = NULL;
1045                         continue;
1046                 }
1047
1048                 DRM_ERROR("inactive empty %d request empty %d "
1049                           "flushing empty %d\n",
1050                           list_empty(&dev_priv->mm.inactive_list),
1051                           list_empty(&dev_priv->mm.request_list),
1052                           list_empty(&dev_priv->mm.flushing_list));
1053                 /* If we didn't do any of the above, there's nothing to be done
1054                  * and we just can't fit it in.
1055                  */
1056                 return -ENOMEM;
1057         }
1058         return ret;
1059 }
1060
1061 static int
1062 i915_gem_object_get_page_list(struct drm_gem_object *obj)
1063 {
1064         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1065         int page_count, i;
1066         struct address_space *mapping;
1067         struct inode *inode;
1068         struct page *page;
1069         int ret;
1070
1071         if (obj_priv->page_list)
1072                 return 0;
1073
1074         /* Get the list of pages out of our struct file.  They'll be pinned
1075          * at this point until we release them.
1076          */
1077         page_count = obj->size / PAGE_SIZE;
1078         BUG_ON(obj_priv->page_list != NULL);
1079         obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *),
1080                                          DRM_MEM_DRIVER);
1081         if (obj_priv->page_list == NULL) {
1082                 DRM_ERROR("Faled to allocate page list\n");
1083                 return -ENOMEM;
1084         }
1085
1086         inode = obj->filp->f_path.dentry->d_inode;
1087         mapping = inode->i_mapping;
1088         for (i = 0; i < page_count; i++) {
1089                 page = read_mapping_page(mapping, i, NULL);
1090                 if (IS_ERR(page)) {
1091                         ret = PTR_ERR(page);
1092                         DRM_ERROR("read_mapping_page failed: %d\n", ret);
1093                         i915_gem_object_free_page_list(obj);
1094                         return ret;
1095                 }
1096                 obj_priv->page_list[i] = page;
1097         }
1098         return 0;
1099 }
1100
1101 /**
1102  * Finds free space in the GTT aperture and binds the object there.
1103  */
1104 static int
1105 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
1106 {
1107         struct drm_device *dev = obj->dev;
1108         struct drm_i915_private *dev_priv = dev->dev_private;
1109         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1110         struct drm_mm_node *free_space;
1111         int page_count, ret;
1112
1113         if (alignment == 0)
1114                 alignment = PAGE_SIZE;
1115         if (alignment & (PAGE_SIZE - 1)) {
1116                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1117                 return -EINVAL;
1118         }
1119
1120  search_free:
1121         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1122                                         obj->size, alignment, 0);
1123         if (free_space != NULL) {
1124                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
1125                                                        alignment);
1126                 if (obj_priv->gtt_space != NULL) {
1127                         obj_priv->gtt_space->private = obj;
1128                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
1129                 }
1130         }
1131         if (obj_priv->gtt_space == NULL) {
1132                 /* If the gtt is empty and we're still having trouble
1133                  * fitting our object in, we're out of memory.
1134                  */
1135 #if WATCH_LRU
1136                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
1137 #endif
1138                 if (list_empty(&dev_priv->mm.inactive_list) &&
1139                     list_empty(&dev_priv->mm.flushing_list) &&
1140                     list_empty(&dev_priv->mm.active_list)) {
1141                         DRM_ERROR("GTT full, but LRU list empty\n");
1142                         return -ENOMEM;
1143                 }
1144
1145                 ret = i915_gem_evict_something(dev);
1146                 if (ret != 0) {
1147                         DRM_ERROR("Failed to evict a buffer %d\n", ret);
1148                         return ret;
1149                 }
1150                 goto search_free;
1151         }
1152
1153 #if WATCH_BUF
1154         DRM_INFO("Binding object of size %d at 0x%08x\n",
1155                  obj->size, obj_priv->gtt_offset);
1156 #endif
1157         ret = i915_gem_object_get_page_list(obj);
1158         if (ret) {
1159                 drm_mm_put_block(obj_priv->gtt_space);
1160                 obj_priv->gtt_space = NULL;
1161                 return ret;
1162         }
1163
1164         page_count = obj->size / PAGE_SIZE;
1165         /* Create an AGP memory structure pointing at our pages, and bind it
1166          * into the GTT.
1167          */
1168         obj_priv->agp_mem = drm_agp_bind_pages(dev,
1169                                                obj_priv->page_list,
1170                                                page_count,
1171                                                obj_priv->gtt_offset);
1172         if (obj_priv->agp_mem == NULL) {
1173                 i915_gem_object_free_page_list(obj);
1174                 drm_mm_put_block(obj_priv->gtt_space);
1175                 obj_priv->gtt_space = NULL;
1176                 return -ENOMEM;
1177         }
1178         atomic_inc(&dev->gtt_count);
1179         atomic_add(obj->size, &dev->gtt_memory);
1180
1181         /* Assert that the object is not currently in any GPU domain. As it
1182          * wasn't in the GTT, there shouldn't be any way it could have been in
1183          * a GPU cache
1184          */
1185         BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1186         BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1187
1188         return 0;
1189 }
1190
1191 void
1192 i915_gem_clflush_object(struct drm_gem_object *obj)
1193 {
1194         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
1195
1196         /* If we don't have a page list set up, then we're not pinned
1197          * to GPU, and we can ignore the cache flush because it'll happen
1198          * again at bind time.
1199          */
1200         if (obj_priv->page_list == NULL)
1201                 return;
1202
1203         drm_ttm_cache_flush(obj_priv->page_list, obj->size / PAGE_SIZE);
1204 }
1205
1206 /*
1207  * Set the next domain for the specified object. This
1208  * may not actually perform the necessary flushing/invaliding though,
1209  * as that may want to be batched with other set_domain operations
1210  *
1211  * This is (we hope) the only really tricky part of gem. The goal
1212  * is fairly simple -- track which caches hold bits of the object
1213  * and make sure they remain coherent. A few concrete examples may
1214  * help to explain how it works. For shorthand, we use the notation
1215  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1216  * a pair of read and write domain masks.
1217  *
1218  * Case 1: the batch buffer
1219  *
1220  *      1. Allocated
1221  *      2. Written by CPU
1222  *      3. Mapped to GTT
1223  *      4. Read by GPU
1224  *      5. Unmapped from GTT
1225  *      6. Freed
1226  *
1227  *      Let's take these a step at a time
1228  *
1229  *      1. Allocated
1230  *              Pages allocated from the kernel may still have
1231  *              cache contents, so we set them to (CPU, CPU) always.
1232  *      2. Written by CPU (using pwrite)
1233  *              The pwrite function calls set_domain (CPU, CPU) and
1234  *              this function does nothing (as nothing changes)
1235  *      3. Mapped by GTT
1236  *              This function asserts that the object is not
1237  *              currently in any GPU-based read or write domains
1238  *      4. Read by GPU
1239  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
1240  *              As write_domain is zero, this function adds in the
1241  *              current read domains (CPU+COMMAND, 0).
1242  *              flush_domains is set to CPU.
1243  *              invalidate_domains is set to COMMAND
1244  *              clflush is run to get data out of the CPU caches
1245  *              then i915_dev_set_domain calls i915_gem_flush to
1246  *              emit an MI_FLUSH and drm_agp_chipset_flush
1247  *      5. Unmapped from GTT
1248  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
1249  *              flush_domains and invalidate_domains end up both zero
1250  *              so no flushing/invalidating happens
1251  *      6. Freed
1252  *              yay, done
1253  *
1254  * Case 2: The shared render buffer
1255  *
1256  *      1. Allocated
1257  *      2. Mapped to GTT
1258  *      3. Read/written by GPU
1259  *      4. set_domain to (CPU,CPU)
1260  *      5. Read/written by CPU
1261  *      6. Read/written by GPU
1262  *
1263  *      1. Allocated
1264  *              Same as last example, (CPU, CPU)
1265  *      2. Mapped to GTT
1266  *              Nothing changes (assertions find that it is not in the GPU)
1267  *      3. Read/written by GPU
1268  *              execbuffer calls set_domain (RENDER, RENDER)
1269  *              flush_domains gets CPU
1270  *              invalidate_domains gets GPU
1271  *              clflush (obj)
1272  *              MI_FLUSH and drm_agp_chipset_flush
1273  *      4. set_domain (CPU, CPU)
1274  *              flush_domains gets GPU
1275  *              invalidate_domains gets CPU
1276  *              wait_rendering (obj) to make sure all drawing is complete.
1277  *              This will include an MI_FLUSH to get the data from GPU
1278  *              to memory
1279  *              clflush (obj) to invalidate the CPU cache
1280  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
1281  *      5. Read/written by CPU
1282  *              cache lines are loaded and dirtied
1283  *      6. Read written by GPU
1284  *              Same as last GPU access
1285  *
1286  * Case 3: The constant buffer
1287  *
1288  *      1. Allocated
1289  *      2. Written by CPU
1290  *      3. Read by GPU
1291  *      4. Updated (written) by CPU again
1292  *      5. Read by GPU
1293  *
1294  *      1. Allocated
1295  *              (CPU, CPU)
1296  *      2. Written by CPU
1297  *              (CPU, CPU)
1298  *      3. Read by GPU
1299  *              (CPU+RENDER, 0)
1300  *              flush_domains = CPU
1301  *              invalidate_domains = RENDER
1302  *              clflush (obj)
1303  *              MI_FLUSH
1304  *              drm_agp_chipset_flush
1305  *      4. Updated (written) by CPU again
1306  *              (CPU, CPU)
1307  *              flush_domains = 0 (no previous write domain)
1308  *              invalidate_domains = 0 (no new read domains)
1309  *      5. Read by GPU
1310  *              (CPU+RENDER, 0)
1311  *              flush_domains = CPU
1312  *              invalidate_domains = RENDER
1313  *              clflush (obj)
1314  *              MI_FLUSH
1315  *              drm_agp_chipset_flush
1316  */
1317 int
1318 i915_gem_object_set_domain(struct drm_gem_object *obj,
1319                             uint32_t read_domains,
1320                             uint32_t write_domain)
1321 {
1322         struct drm_device               *dev = obj->dev;
1323         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
1324         uint32_t                        invalidate_domains = 0;
1325         uint32_t                        flush_domains = 0;
1326         int                             ret;
1327
1328 #if WATCH_BUF
1329         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
1330                  __func__, obj,
1331                  obj->read_domains, read_domains,
1332                  obj->write_domain, write_domain);
1333 #endif
1334         /*
1335          * If the object isn't moving to a new write domain,
1336          * let the object stay in multiple read domains
1337          */
1338         if (write_domain == 0)
1339                 read_domains |= obj->read_domains;
1340         else
1341                 obj_priv->dirty = 1;
1342
1343         /*
1344          * Flush the current write domain if
1345          * the new read domains don't match. Invalidate
1346          * any read domains which differ from the old
1347          * write domain
1348          */
1349         if (obj->write_domain && obj->write_domain != read_domains) {
1350                 flush_domains |= obj->write_domain;
1351                 invalidate_domains |= read_domains & ~obj->write_domain;
1352         }
1353         /*
1354          * Invalidate any read caches which may have
1355          * stale data. That is, any new read domains.
1356          */
1357         invalidate_domains |= read_domains & ~obj->read_domains;
1358         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
1359 #if WATCH_BUF
1360                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
1361                          __func__, flush_domains, invalidate_domains);
1362 #endif
1363                 /*
1364                  * If we're invaliding the CPU cache and flushing a GPU cache,
1365                  * then pause for rendering so that the GPU caches will be
1366                  * flushed before the cpu cache is invalidated
1367                  */
1368                 if ((invalidate_domains & I915_GEM_DOMAIN_CPU) &&
1369                     (flush_domains & ~(I915_GEM_DOMAIN_CPU |
1370                                        I915_GEM_DOMAIN_GTT))) {
1371                         ret = i915_gem_object_wait_rendering(obj);
1372                         if (ret)
1373                                 return ret;
1374                 }
1375                 i915_gem_clflush_object(obj);
1376         }
1377
1378         if ((write_domain | flush_domains) != 0)
1379                 obj->write_domain = write_domain;
1380
1381         /* If we're invalidating the CPU domain, clear the per-page CPU
1382          * domain list as well.
1383          */
1384         if (obj_priv->page_cpu_valid != NULL &&
1385             (obj->read_domains & I915_GEM_DOMAIN_CPU) &&
1386             ((read_domains & I915_GEM_DOMAIN_CPU) == 0)) {
1387                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
1388         }
1389         obj->read_domains = read_domains;
1390
1391         dev->invalidate_domains |= invalidate_domains;
1392         dev->flush_domains |= flush_domains;
1393 #if WATCH_BUF
1394         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
1395                  __func__,
1396                  obj->read_domains, obj->write_domain,
1397                  dev->invalidate_domains, dev->flush_domains);
1398 #endif
1399         return 0;
1400 }
1401
1402 /**
1403  * Set the read/write domain on a range of the object.
1404  *
1405  * Currently only implemented for CPU reads, otherwise drops to normal
1406  * i915_gem_object_set_domain().
1407  */
1408 static int
1409 i915_gem_object_set_domain_range(struct drm_gem_object *obj,
1410                                  uint64_t offset,
1411                                  uint64_t size,
1412                                  uint32_t read_domains,
1413                                  uint32_t write_domain)
1414 {
1415         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1416         int ret, i;
1417
1418         if (obj->read_domains & I915_GEM_DOMAIN_CPU)
1419                 return 0;
1420
1421         if (read_domains != I915_GEM_DOMAIN_CPU ||
1422             write_domain != 0)
1423                 return i915_gem_object_set_domain(obj,
1424                                                   read_domains, write_domain);
1425
1426         /* Wait on any GPU rendering to the object to be flushed. */
1427         if (obj->write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) {
1428                 ret = i915_gem_object_wait_rendering(obj);
1429                 if (ret)
1430                         return ret;
1431         }
1432
1433         if (obj_priv->page_cpu_valid == NULL) {
1434                 obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
1435                                                       DRM_MEM_DRIVER);
1436         }
1437
1438         /* Flush the cache on any pages that are still invalid from the CPU's
1439          * perspective.
1440          */
1441         for (i = offset / PAGE_SIZE; i < (offset + size - 1) / PAGE_SIZE; i++) {
1442                 if (obj_priv->page_cpu_valid[i])
1443                         continue;
1444
1445                 drm_ttm_cache_flush(obj_priv->page_list + i, 1);
1446
1447                 obj_priv->page_cpu_valid[i] = 1;
1448         }
1449
1450         return 0;
1451 }
1452
1453 /**
1454  * Once all of the objects have been set in the proper domain,
1455  * perform the necessary flush and invalidate operations.
1456  *
1457  * Returns the write domains flushed, for use in flush tracking.
1458  */
1459 static uint32_t
1460 i915_gem_dev_set_domain(struct drm_device *dev)
1461 {
1462         uint32_t flush_domains = dev->flush_domains;
1463
1464         /*
1465          * Now that all the buffers are synced to the proper domains,
1466          * flush and invalidate the collected domains
1467          */
1468         if (dev->invalidate_domains | dev->flush_domains) {
1469 #if WATCH_EXEC
1470                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
1471                           __func__,
1472                          dev->invalidate_domains,
1473                          dev->flush_domains);
1474 #endif
1475                 i915_gem_flush(dev,
1476                                dev->invalidate_domains,
1477                                dev->flush_domains);
1478                 dev->invalidate_domains = 0;
1479                 dev->flush_domains = 0;
1480         }
1481
1482         return flush_domains;
1483 }
1484
1485 /**
1486  * Pin an object to the GTT and evaluate the relocations landing in it.
1487  */
1488 static int
1489 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
1490                                  struct drm_file *file_priv,
1491                                  struct drm_i915_gem_exec_object *entry)
1492 {
1493         struct drm_device *dev = obj->dev;
1494         struct drm_i915_gem_relocation_entry reloc;
1495         struct drm_i915_gem_relocation_entry __user *relocs;
1496         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1497         int i, ret;
1498         uint32_t last_reloc_offset = -1;
1499         void *reloc_page = NULL;
1500
1501         /* Choose the GTT offset for our buffer and put it there. */
1502         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
1503         if (ret)
1504                 return ret;
1505
1506         entry->offset = obj_priv->gtt_offset;
1507
1508         relocs = (struct drm_i915_gem_relocation_entry __user *)
1509                  (uintptr_t) entry->relocs_ptr;
1510         /* Apply the relocations, using the GTT aperture to avoid cache
1511          * flushing requirements.
1512          */
1513         for (i = 0; i < entry->relocation_count; i++) {
1514                 struct drm_gem_object *target_obj;
1515                 struct drm_i915_gem_object *target_obj_priv;
1516                 uint32_t reloc_val, reloc_offset, *reloc_entry;
1517                 int ret;
1518
1519                 ret = copy_from_user(&reloc, relocs + i, sizeof(reloc));
1520                 if (ret != 0) {
1521                         i915_gem_object_unpin(obj);
1522                         return ret;
1523                 }
1524
1525                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
1526                                                    reloc.target_handle);
1527                 if (target_obj == NULL) {
1528                         i915_gem_object_unpin(obj);
1529                         return -EBADF;
1530                 }
1531                 target_obj_priv = target_obj->driver_private;
1532
1533                 /* The target buffer should have appeared before us in the
1534                  * exec_object list, so it should have a GTT space bound by now.
1535                  */
1536                 if (target_obj_priv->gtt_space == NULL) {
1537                         DRM_ERROR("No GTT space found for object %d\n",
1538                                   reloc.target_handle);
1539                         drm_gem_object_unreference(target_obj);
1540                         i915_gem_object_unpin(obj);
1541                         return -EINVAL;
1542                 }
1543
1544                 if (reloc.offset > obj->size - 4) {
1545                         DRM_ERROR("Relocation beyond object bounds: "
1546                                   "obj %p target %d offset %d size %d.\n",
1547                                   obj, reloc.target_handle,
1548                                   (int) reloc.offset, (int) obj->size);
1549                         drm_gem_object_unreference(target_obj);
1550                         i915_gem_object_unpin(obj);
1551                         return -EINVAL;
1552                 }
1553                 if (reloc.offset & 3) {
1554                         DRM_ERROR("Relocation not 4-byte aligned: "
1555                                   "obj %p target %d offset %d.\n",
1556                                   obj, reloc.target_handle,
1557                                   (int) reloc.offset);
1558                         drm_gem_object_unreference(target_obj);
1559                         i915_gem_object_unpin(obj);
1560                         return -EINVAL;
1561                 }
1562
1563                 if (reloc.write_domain && target_obj->pending_write_domain &&
1564                     reloc.write_domain != target_obj->pending_write_domain) {
1565                         DRM_ERROR("Write domain conflict: "
1566                                   "obj %p target %d offset %d "
1567                                   "new %08x old %08x\n",
1568                                   obj, reloc.target_handle,
1569                                   (int) reloc.offset,
1570                                   reloc.write_domain,
1571                                   target_obj->pending_write_domain);
1572                         drm_gem_object_unreference(target_obj);
1573                         i915_gem_object_unpin(obj);
1574                         return -EINVAL;
1575                 }
1576
1577 #if WATCH_RELOC
1578                 DRM_INFO("%s: obj %p offset %08x target %d "
1579                          "read %08x write %08x gtt %08x "
1580                          "presumed %08x delta %08x\n",
1581                          __func__,
1582                          obj,
1583                          (int) reloc.offset,
1584                          (int) reloc.target_handle,
1585                          (int) reloc.read_domains,
1586                          (int) reloc.write_domain,
1587                          (int) target_obj_priv->gtt_offset,
1588                          (int) reloc.presumed_offset,
1589                          reloc.delta);
1590 #endif
1591
1592                 target_obj->pending_read_domains |= reloc.read_domains;
1593                 target_obj->pending_write_domain |= reloc.write_domain;
1594
1595                 /* If the relocation already has the right value in it, no
1596                  * more work needs to be done.
1597                  */
1598                 if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
1599                         drm_gem_object_unreference(target_obj);
1600                         continue;
1601                 }
1602
1603                 /* Now that we're going to actually write some data in,
1604                  * make sure that any rendering using this buffer's contents
1605                  * is completed.
1606                  */
1607                 i915_gem_object_wait_rendering(obj);
1608
1609                 /* As we're writing through the gtt, flush
1610                  * any CPU writes before we write the relocations
1611                  */
1612                 if (obj->write_domain & I915_GEM_DOMAIN_CPU) {
1613                         i915_gem_clflush_object(obj);
1614                         drm_agp_chipset_flush(dev);
1615                         obj->write_domain = 0;
1616                 }
1617
1618                 /* Map the page containing the relocation we're going to
1619                  * perform.
1620                  */
1621                 reloc_offset = obj_priv->gtt_offset + reloc.offset;
1622                 if (reloc_page == NULL ||
1623                     (last_reloc_offset & ~(PAGE_SIZE - 1)) !=
1624                     (reloc_offset & ~(PAGE_SIZE - 1))) {
1625                         if (reloc_page != NULL)
1626                                 iounmap(reloc_page);
1627
1628                         reloc_page = ioremap(dev->agp->base +
1629                                              (reloc_offset & ~(PAGE_SIZE - 1)),
1630                                              PAGE_SIZE);
1631                         last_reloc_offset = reloc_offset;
1632                         if (reloc_page == NULL) {
1633                                 drm_gem_object_unreference(target_obj);
1634                                 i915_gem_object_unpin(obj);
1635                                 return -ENOMEM;
1636                         }
1637                 }
1638
1639                 reloc_entry = (uint32_t *)((char *)reloc_page +
1640                                            (reloc_offset & (PAGE_SIZE - 1)));
1641                 reloc_val = target_obj_priv->gtt_offset + reloc.delta;
1642
1643 #if WATCH_BUF
1644                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
1645                           obj, (unsigned int) reloc.offset,
1646                           readl(reloc_entry), reloc_val);
1647 #endif
1648                 writel(reloc_val, reloc_entry);
1649
1650                 /* Write the updated presumed offset for this entry back out
1651                  * to the user.
1652                  */
1653                 reloc.presumed_offset = target_obj_priv->gtt_offset;
1654                 ret = copy_to_user(relocs + i, &reloc, sizeof(reloc));
1655                 if (ret != 0) {
1656                         drm_gem_object_unreference(target_obj);
1657                         i915_gem_object_unpin(obj);
1658                         return ret;
1659                 }
1660
1661                 drm_gem_object_unreference(target_obj);
1662         }
1663
1664         if (reloc_page != NULL)
1665                 iounmap(reloc_page);
1666
1667 #if WATCH_BUF
1668         if (0)
1669                 i915_gem_dump_object(obj, 128, __func__, ~0);
1670 #endif
1671         return 0;
1672 }
1673
1674 /** Dispatch a batchbuffer to the ring
1675  */
1676 static int
1677 i915_dispatch_gem_execbuffer(struct drm_device *dev,
1678                               struct drm_i915_gem_execbuffer *exec,
1679                               uint64_t exec_offset)
1680 {
1681         struct drm_i915_private *dev_priv = dev->dev_private;
1682         struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *)
1683                                              (uintptr_t) exec->cliprects_ptr;
1684         int nbox = exec->num_cliprects;
1685         int i = 0, count;
1686         uint32_t        exec_start, exec_len;
1687         RING_LOCALS;
1688
1689         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
1690         exec_len = (uint32_t) exec->batch_len;
1691
1692         if ((exec_start | exec_len) & 0x7) {
1693                 DRM_ERROR("alignment\n");
1694                 return -EINVAL;
1695         }
1696
1697         if (!exec_start)
1698                 return -EINVAL;
1699
1700         count = nbox ? nbox : 1;
1701
1702         for (i = 0; i < count; i++) {
1703                 if (i < nbox) {
1704                         int ret = i915_emit_box(dev, boxes, i,
1705                                                 exec->DR1, exec->DR4);
1706                         if (ret)
1707                                 return ret;
1708                 }
1709
1710                 if (IS_I830(dev) || IS_845G(dev)) {
1711                         BEGIN_LP_RING(4);
1712                         OUT_RING(MI_BATCH_BUFFER);
1713                         OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1714                         OUT_RING(exec_start + exec_len - 4);
1715                         OUT_RING(0);
1716                         ADVANCE_LP_RING();
1717                 } else {
1718                         BEGIN_LP_RING(2);
1719                         if (IS_I965G(dev)) {
1720                                 OUT_RING(MI_BATCH_BUFFER_START |
1721                                          (2 << 6) |
1722                                          MI_BATCH_NON_SECURE_I965);
1723                                 OUT_RING(exec_start);
1724                         } else {
1725                                 OUT_RING(MI_BATCH_BUFFER_START |
1726                                          (2 << 6));
1727                                 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1728                         }
1729                         ADVANCE_LP_RING();
1730                 }
1731         }
1732
1733         /* XXX breadcrumb */
1734         return 0;
1735 }
1736
1737 /* Throttle our rendering by waiting until the ring has completed our requests
1738  * emitted over 20 msec ago.
1739  *
1740  * This should get us reasonable parallelism between CPU and GPU but also
1741  * relatively low latency when blocking on a particular request to finish.
1742  */
1743 static int
1744 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
1745 {
1746         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1747         int ret = 0;
1748         uint32_t seqno;
1749
1750         mutex_lock(&dev->struct_mutex);
1751         seqno = i915_file_priv->mm.last_gem_throttle_seqno;
1752         i915_file_priv->mm.last_gem_throttle_seqno =
1753                 i915_file_priv->mm.last_gem_seqno;
1754         if (seqno)
1755                 ret = i915_wait_request(dev, seqno);
1756         mutex_unlock(&dev->struct_mutex);
1757         return ret;
1758 }
1759
1760 int
1761 i915_gem_execbuffer(struct drm_device *dev, void *data,
1762                     struct drm_file *file_priv)
1763 {
1764         struct drm_i915_private *dev_priv = dev->dev_private;
1765         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1766         struct drm_i915_gem_execbuffer *args = data;
1767         struct drm_i915_gem_exec_object *exec_list = NULL;
1768         struct drm_gem_object **object_list = NULL;
1769         struct drm_gem_object *batch_obj;
1770         int ret, i, pinned = 0;
1771         uint64_t exec_offset;
1772         uint32_t seqno, flush_domains;
1773
1774 #if WATCH_EXEC
1775         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1776                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1777 #endif
1778
1779         /* Copy in the exec list from userland */
1780         exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
1781                                DRM_MEM_DRIVER);
1782         object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
1783                                  DRM_MEM_DRIVER);
1784         if (exec_list == NULL || object_list == NULL) {
1785                 DRM_ERROR("Failed to allocate exec or object list "
1786                           "for %d buffers\n",
1787                           args->buffer_count);
1788                 ret = -ENOMEM;
1789                 goto pre_mutex_err;
1790         }
1791         ret = copy_from_user(exec_list,
1792                              (struct drm_i915_relocation_entry __user *)
1793                              (uintptr_t) args->buffers_ptr,
1794                              sizeof(*exec_list) * args->buffer_count);
1795         if (ret != 0) {
1796                 DRM_ERROR("copy %d exec entries failed %d\n",
1797                           args->buffer_count, ret);
1798                 goto pre_mutex_err;
1799         }
1800
1801         mutex_lock(&dev->struct_mutex);
1802
1803         i915_verify_inactive(dev, __FILE__, __LINE__);
1804
1805         if (dev_priv->mm.wedged) {
1806                 DRM_ERROR("Execbuf while wedged\n");
1807                 mutex_unlock(&dev->struct_mutex);
1808                 return -EIO;
1809         }
1810
1811         if (dev_priv->mm.suspended) {
1812                 DRM_ERROR("Execbuf while VT-switched.\n");
1813                 mutex_unlock(&dev->struct_mutex);
1814                 return -EBUSY;
1815         }
1816
1817         /* Zero the gloabl flush/invalidate flags. These
1818          * will be modified as each object is bound to the
1819          * gtt
1820          */
1821         dev->invalidate_domains = 0;
1822         dev->flush_domains = 0;
1823
1824         /* Look up object handles and perform the relocations */
1825         for (i = 0; i < args->buffer_count; i++) {
1826                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
1827                                                        exec_list[i].handle);
1828                 if (object_list[i] == NULL) {
1829                         DRM_ERROR("Invalid object handle %d at index %d\n",
1830                                    exec_list[i].handle, i);
1831                         ret = -EBADF;
1832                         goto err;
1833                 }
1834
1835                 object_list[i]->pending_read_domains = 0;
1836                 object_list[i]->pending_write_domain = 0;
1837                 ret = i915_gem_object_pin_and_relocate(object_list[i],
1838                                                        file_priv,
1839                                                        &exec_list[i]);
1840                 if (ret) {
1841                         DRM_ERROR("object bind and relocate failed %d\n", ret);
1842                         goto err;
1843                 }
1844                 pinned = i + 1;
1845         }
1846
1847         /* Set the pending read domains for the batch buffer to COMMAND */
1848         batch_obj = object_list[args->buffer_count-1];
1849         batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
1850         batch_obj->pending_write_domain = 0;
1851
1852         i915_verify_inactive(dev, __FILE__, __LINE__);
1853
1854         for (i = 0; i < args->buffer_count; i++) {
1855                 struct drm_gem_object *obj = object_list[i];
1856                 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1857
1858                 if (obj_priv->gtt_space == NULL) {
1859                         /* We evicted the buffer in the process of validating
1860                          * our set of buffers in.  We could try to recover by
1861                          * kicking them everything out and trying again from
1862                          * the start.
1863                          */
1864                         ret = -ENOMEM;
1865                         goto err;
1866                 }
1867
1868                 /* make sure all previous memory operations have passed */
1869                 ret = i915_gem_object_set_domain(obj,
1870                                                  obj->pending_read_domains,
1871                                                  obj->pending_write_domain);
1872                 if (ret)
1873                         goto err;
1874         }
1875
1876         i915_verify_inactive(dev, __FILE__, __LINE__);
1877
1878         /* Flush/invalidate caches and chipset buffer */
1879         flush_domains = i915_gem_dev_set_domain(dev);
1880
1881         i915_verify_inactive(dev, __FILE__, __LINE__);
1882
1883 #if WATCH_COHERENCY
1884         for (i = 0; i < args->buffer_count; i++) {
1885                 i915_gem_object_check_coherency(object_list[i],
1886                                                 exec_list[i].handle);
1887         }
1888 #endif
1889
1890         exec_offset = exec_list[args->buffer_count - 1].offset;
1891
1892 #if WATCH_EXEC
1893         i915_gem_dump_object(object_list[args->buffer_count - 1],
1894                               args->batch_len,
1895                               __func__,
1896                               ~0);
1897 #endif
1898
1899         /* Exec the batchbuffer */
1900         ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset);
1901         if (ret) {
1902                 DRM_ERROR("dispatch failed %d\n", ret);
1903                 goto err;
1904         }
1905
1906         /*
1907          * Ensure that the commands in the batch buffer are
1908          * finished before the interrupt fires
1909          */
1910         flush_domains |= i915_retire_commands(dev);
1911
1912         i915_verify_inactive(dev, __FILE__, __LINE__);
1913
1914         /*
1915          * Get a seqno representing the execution of the current buffer,
1916          * which we can wait on.  We would like to mitigate these interrupts,
1917          * likely by only creating seqnos occasionally (so that we have
1918          * *some* interrupts representing completion of buffers that we can
1919          * wait on when trying to clear up gtt space).
1920          */
1921         seqno = i915_add_request(dev, flush_domains);
1922         BUG_ON(seqno == 0);
1923         i915_file_priv->mm.last_gem_seqno = seqno;
1924         for (i = 0; i < args->buffer_count; i++) {
1925                 struct drm_gem_object *obj = object_list[i];
1926                 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1927
1928                 i915_gem_object_move_to_active(obj);
1929                 obj_priv->last_rendering_seqno = seqno;
1930 #if WATCH_LRU
1931                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
1932 #endif
1933         }
1934 #if WATCH_LRU
1935         i915_dump_lru(dev, __func__);
1936 #endif
1937
1938         i915_verify_inactive(dev, __FILE__, __LINE__);
1939
1940         /* Copy the new buffer offsets back to the user's exec list. */
1941         ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1942                            (uintptr_t) args->buffers_ptr,
1943                            exec_list,
1944                            sizeof(*exec_list) * args->buffer_count);
1945         if (ret)
1946                 DRM_ERROR("failed to copy %d exec entries "
1947                           "back to user (%d)\n",
1948                            args->buffer_count, ret);
1949 err:
1950         if (object_list != NULL) {
1951                 for (i = 0; i < pinned; i++)
1952                         i915_gem_object_unpin(object_list[i]);
1953
1954                 for (i = 0; i < args->buffer_count; i++)
1955                         drm_gem_object_unreference(object_list[i]);
1956         }
1957         mutex_unlock(&dev->struct_mutex);
1958
1959 pre_mutex_err:
1960         drm_free(object_list, sizeof(*object_list) * args->buffer_count,
1961                  DRM_MEM_DRIVER);
1962         drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
1963                  DRM_MEM_DRIVER);
1964
1965         return ret;
1966 }
1967
1968 int
1969 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
1970 {
1971         struct drm_device *dev = obj->dev;
1972         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1973         int ret;
1974
1975         i915_verify_inactive(dev, __FILE__, __LINE__);
1976         if (obj_priv->gtt_space == NULL) {
1977                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
1978                 if (ret != 0) {
1979                         DRM_ERROR("Failure to bind: %d", ret);
1980                         return ret;
1981                 }
1982         }
1983         obj_priv->pin_count++;
1984
1985         /* If the object is not active and not pending a flush,
1986          * remove it from the inactive list
1987          */
1988         if (obj_priv->pin_count == 1) {
1989                 atomic_inc(&dev->pin_count);
1990                 atomic_add(obj->size, &dev->pin_memory);
1991                 if (!obj_priv->active &&
1992                     (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
1993                                            I915_GEM_DOMAIN_GTT)) == 0 &&
1994                     !list_empty(&obj_priv->list))
1995                         list_del_init(&obj_priv->list);
1996         }
1997         i915_verify_inactive(dev, __FILE__, __LINE__);
1998
1999         return 0;
2000 }
2001
2002 void
2003 i915_gem_object_unpin(struct drm_gem_object *obj)
2004 {
2005         struct drm_device *dev = obj->dev;
2006         struct drm_i915_private *dev_priv = dev->dev_private;
2007         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2008
2009         i915_verify_inactive(dev, __FILE__, __LINE__);
2010         obj_priv->pin_count--;
2011         BUG_ON(obj_priv->pin_count < 0);
2012         BUG_ON(obj_priv->gtt_space == NULL);
2013
2014         /* If the object is no longer pinned, and is
2015          * neither active nor being flushed, then stick it on
2016          * the inactive list
2017          */
2018         if (obj_priv->pin_count == 0) {
2019                 if (!obj_priv->active &&
2020                     (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2021                                            I915_GEM_DOMAIN_GTT)) == 0)
2022                         list_move_tail(&obj_priv->list,
2023                                        &dev_priv->mm.inactive_list);
2024                 atomic_dec(&dev->pin_count);
2025                 atomic_sub(obj->size, &dev->pin_memory);
2026         }
2027         i915_verify_inactive(dev, __FILE__, __LINE__);
2028 }
2029
2030 int
2031 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2032                    struct drm_file *file_priv)
2033 {
2034         struct drm_i915_gem_pin *args = data;
2035         struct drm_gem_object *obj;
2036         struct drm_i915_gem_object *obj_priv;
2037         int ret;
2038
2039         mutex_lock(&dev->struct_mutex);
2040
2041         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2042         if (obj == NULL) {
2043                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
2044                           args->handle);
2045                 mutex_unlock(&dev->struct_mutex);
2046                 return -EBADF;
2047         }
2048         obj_priv = obj->driver_private;
2049
2050         ret = i915_gem_object_pin(obj, args->alignment);
2051         if (ret != 0) {
2052                 drm_gem_object_unreference(obj);
2053                 mutex_unlock(&dev->struct_mutex);
2054                 return ret;
2055         }
2056
2057         /* XXX - flush the CPU caches for pinned objects
2058          * as the X server doesn't manage domains yet
2059          */
2060         if (obj->write_domain & I915_GEM_DOMAIN_CPU) {
2061                 i915_gem_clflush_object(obj);
2062                 drm_agp_chipset_flush(dev);
2063                 obj->write_domain = 0;
2064         }
2065         args->offset = obj_priv->gtt_offset;
2066         drm_gem_object_unreference(obj);
2067         mutex_unlock(&dev->struct_mutex);
2068
2069         return 0;
2070 }
2071
2072 int
2073 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2074                      struct drm_file *file_priv)
2075 {
2076         struct drm_i915_gem_pin *args = data;
2077         struct drm_gem_object *obj;
2078
2079         mutex_lock(&dev->struct_mutex);
2080
2081         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2082         if (obj == NULL) {
2083                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2084                           args->handle);
2085                 mutex_unlock(&dev->struct_mutex);
2086                 return -EBADF;
2087         }
2088
2089         i915_gem_object_unpin(obj);
2090
2091         drm_gem_object_unreference(obj);
2092         mutex_unlock(&dev->struct_mutex);
2093         return 0;
2094 }
2095
2096 int
2097 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2098                     struct drm_file *file_priv)
2099 {
2100         struct drm_i915_gem_busy *args = data;
2101         struct drm_gem_object *obj;
2102         struct drm_i915_gem_object *obj_priv;
2103
2104         mutex_lock(&dev->struct_mutex);
2105         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2106         if (obj == NULL) {
2107                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2108                           args->handle);
2109                 mutex_unlock(&dev->struct_mutex);
2110                 return -EBADF;
2111         }
2112
2113         obj_priv = obj->driver_private;
2114         args->busy = obj_priv->active;
2115
2116         drm_gem_object_unreference(obj);
2117         mutex_unlock(&dev->struct_mutex);
2118         return 0;
2119 }
2120
2121 int
2122 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2123                         struct drm_file *file_priv)
2124 {
2125     return i915_gem_ring_throttle(dev, file_priv);
2126 }
2127
2128 int i915_gem_init_object(struct drm_gem_object *obj)
2129 {
2130         struct drm_i915_gem_object *obj_priv;
2131
2132         obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
2133         if (obj_priv == NULL)
2134                 return -ENOMEM;
2135
2136         /*
2137          * We've just allocated pages from the kernel,
2138          * so they've just been written by the CPU with
2139          * zeros. They'll need to be clflushed before we
2140          * use them with the GPU.
2141          */
2142         obj->write_domain = I915_GEM_DOMAIN_CPU;
2143         obj->read_domains = I915_GEM_DOMAIN_CPU;
2144
2145         obj->driver_private = obj_priv;
2146         obj_priv->obj = obj;
2147         INIT_LIST_HEAD(&obj_priv->list);
2148         return 0;
2149 }
2150
2151 void i915_gem_free_object(struct drm_gem_object *obj)
2152 {
2153         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2154
2155         while (obj_priv->pin_count > 0)
2156                 i915_gem_object_unpin(obj);
2157
2158         i915_gem_object_unbind(obj);
2159
2160         drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER);
2161         drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
2162 }
2163
2164 int
2165 i915_gem_set_domain(struct drm_gem_object *obj,
2166                     struct drm_file *file_priv,
2167                     uint32_t read_domains,
2168                     uint32_t write_domain)
2169 {
2170         struct drm_device *dev = obj->dev;
2171         int ret;
2172         uint32_t flush_domains;
2173
2174         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
2175
2176         ret = i915_gem_object_set_domain(obj, read_domains, write_domain);
2177         if (ret)
2178                 return ret;
2179         flush_domains = i915_gem_dev_set_domain(obj->dev);
2180
2181         if (flush_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT))
2182                 (void) i915_add_request(dev, flush_domains);
2183
2184         return 0;
2185 }
2186
2187 /** Unbinds all objects that are on the given buffer list. */
2188 static int
2189 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
2190 {
2191         struct drm_gem_object *obj;
2192         struct drm_i915_gem_object *obj_priv;
2193         int ret;
2194
2195         while (!list_empty(head)) {
2196                 obj_priv = list_first_entry(head,
2197                                             struct drm_i915_gem_object,
2198                                             list);
2199                 obj = obj_priv->obj;
2200
2201                 if (obj_priv->pin_count != 0) {
2202                         DRM_ERROR("Pinned object in unbind list\n");
2203                         mutex_unlock(&dev->struct_mutex);
2204                         return -EINVAL;
2205                 }
2206
2207                 ret = i915_gem_object_unbind(obj);
2208                 if (ret != 0) {
2209                         DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
2210                                   ret);
2211                         mutex_unlock(&dev->struct_mutex);
2212                         return ret;
2213                 }
2214         }
2215
2216
2217         return 0;
2218 }
2219
2220 static int
2221 i915_gem_idle(struct drm_device *dev)
2222 {
2223         struct drm_i915_private *dev_priv = dev->dev_private;
2224         uint32_t seqno, cur_seqno, last_seqno;
2225         int stuck;
2226
2227         if (dev_priv->mm.suspended)
2228                 return 0;
2229
2230         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
2231          * We need to replace this with a semaphore, or something.
2232          */
2233         dev_priv->mm.suspended = 1;
2234
2235         i915_kernel_lost_context(dev);
2236
2237         /* Flush the GPU along with all non-CPU write domains
2238          */
2239         i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT),
2240                        ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
2241         seqno = i915_add_request(dev, ~(I915_GEM_DOMAIN_CPU |
2242                                         I915_GEM_DOMAIN_GTT));
2243
2244         if (seqno == 0) {
2245                 mutex_unlock(&dev->struct_mutex);
2246                 return -ENOMEM;
2247         }
2248
2249         dev_priv->mm.waiting_gem_seqno = seqno;
2250         last_seqno = 0;
2251         stuck = 0;
2252         for (;;) {
2253                 cur_seqno = i915_get_gem_seqno(dev);
2254                 if (i915_seqno_passed(cur_seqno, seqno))
2255                         break;
2256                 if (last_seqno == cur_seqno) {
2257                         if (stuck++ > 100) {
2258                                 DRM_ERROR("hardware wedged\n");
2259                                 dev_priv->mm.wedged = 1;
2260                                 DRM_WAKEUP(&dev_priv->irq_queue);
2261                                 break;
2262                         }
2263                 }
2264                 msleep(10);
2265                 last_seqno = cur_seqno;
2266         }
2267         dev_priv->mm.waiting_gem_seqno = 0;
2268
2269         i915_gem_retire_requests(dev);
2270
2271         /* Active and flushing should now be empty as we've
2272          * waited for a sequence higher than any pending execbuffer
2273          */
2274         BUG_ON(!list_empty(&dev_priv->mm.active_list));
2275         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2276
2277         /* Request should now be empty as we've also waited
2278          * for the last request in the list
2279          */
2280         BUG_ON(!list_empty(&dev_priv->mm.request_list));
2281
2282         /* Move all buffers out of the GTT. */
2283         i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
2284
2285         BUG_ON(!list_empty(&dev_priv->mm.active_list));
2286         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2287         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
2288         BUG_ON(!list_empty(&dev_priv->mm.request_list));
2289         return 0;
2290 }
2291
2292 static int
2293 i915_gem_init_hws(struct drm_device *dev)
2294 {
2295         struct drm_i915_private *dev_priv = dev->dev_private;
2296         struct drm_gem_object *obj;
2297         struct drm_i915_gem_object *obj_priv;
2298         int ret;
2299
2300         /* If we need a physical address for the status page, it's already
2301          * initialized at driver load time.
2302          */
2303         if (!I915_NEED_GFX_HWS(dev))
2304                 return 0;
2305
2306         obj = drm_gem_object_alloc(dev, 4096);
2307         if (obj == NULL) {
2308                 DRM_ERROR("Failed to allocate status page\n");
2309                 return -ENOMEM;
2310         }
2311         obj_priv = obj->driver_private;
2312
2313         ret = i915_gem_object_pin(obj, 4096);
2314         if (ret != 0) {
2315                 drm_gem_object_unreference(obj);
2316                 return ret;
2317         }
2318
2319         dev_priv->status_gfx_addr = obj_priv->gtt_offset;
2320         dev_priv->hws_map.offset = dev->agp->base + obj_priv->gtt_offset;
2321         dev_priv->hws_map.size = 4096;
2322         dev_priv->hws_map.type = 0;
2323         dev_priv->hws_map.flags = 0;
2324         dev_priv->hws_map.mtrr = 0;
2325
2326         drm_core_ioremap(&dev_priv->hws_map, dev);
2327         if (dev_priv->hws_map.handle == NULL) {
2328                 DRM_ERROR("Failed to map status page.\n");
2329                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
2330                 drm_gem_object_unreference(obj);
2331                 return -EINVAL;
2332         }
2333         dev_priv->hws_obj = obj;
2334         dev_priv->hw_status_page = dev_priv->hws_map.handle;
2335         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
2336         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
2337         DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
2338
2339         return 0;
2340 }
2341
2342 int
2343 i915_gem_init_ringbuffer(struct drm_device *dev)
2344 {
2345         struct drm_i915_private *dev_priv = dev->dev_private;
2346         struct drm_gem_object *obj;
2347         struct drm_i915_gem_object *obj_priv;
2348         int ret;
2349
2350         ret = i915_gem_init_hws(dev);
2351         if (ret != 0)
2352                 return ret;
2353
2354         obj = drm_gem_object_alloc(dev, 128 * 1024);
2355         if (obj == NULL) {
2356                 DRM_ERROR("Failed to allocate ringbuffer\n");
2357                 return -ENOMEM;
2358         }
2359         obj_priv = obj->driver_private;
2360
2361         ret = i915_gem_object_pin(obj, 4096);
2362         if (ret != 0) {
2363                 drm_gem_object_unreference(obj);
2364                 return ret;
2365         }
2366
2367         /* Set up the kernel mapping for the ring. */
2368         dev_priv->ring.Size = obj->size;
2369         dev_priv->ring.tail_mask = obj->size - 1;
2370
2371         dev_priv->ring.map.offset = dev->agp->base + obj_priv->gtt_offset;
2372         dev_priv->ring.map.size = obj->size;
2373         dev_priv->ring.map.type = 0;
2374         dev_priv->ring.map.flags = 0;
2375         dev_priv->ring.map.mtrr = 0;
2376
2377         drm_core_ioremap(&dev_priv->ring.map, dev);
2378         if (dev_priv->ring.map.handle == NULL) {
2379                 DRM_ERROR("Failed to map ringbuffer.\n");
2380                 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2381                 drm_gem_object_unreference(obj);
2382                 return -EINVAL;
2383         }
2384         dev_priv->ring.ring_obj = obj;
2385         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
2386
2387         /* Stop the ring if it's running. */
2388         I915_WRITE(PRB0_CTL, 0);
2389         I915_WRITE(PRB0_HEAD, 0);
2390         I915_WRITE(PRB0_TAIL, 0);
2391         I915_WRITE(PRB0_START, 0);
2392
2393         /* Initialize the ring. */
2394         I915_WRITE(PRB0_START, obj_priv->gtt_offset);
2395         I915_WRITE(PRB0_CTL,
2396                    ((obj->size - 4096) & RING_NR_PAGES) |
2397                    RING_NO_REPORT |
2398                    RING_VALID);
2399
2400         /* Update our cache of the ring state */
2401         i915_kernel_lost_context(dev);
2402
2403         return 0;
2404 }
2405
2406 void
2407 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
2408 {
2409         struct drm_i915_private *dev_priv = dev->dev_private;
2410
2411         if (dev_priv->ring.ring_obj == NULL)
2412                 return;
2413
2414         drm_core_ioremapfree(&dev_priv->ring.map, dev);
2415
2416         i915_gem_object_unpin(dev_priv->ring.ring_obj);
2417         drm_gem_object_unreference(dev_priv->ring.ring_obj);
2418         dev_priv->ring.ring_obj = NULL;
2419         memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2420
2421         if (dev_priv->hws_obj != NULL) {
2422                 i915_gem_object_unpin(dev_priv->hws_obj);
2423                 drm_gem_object_unreference(dev_priv->hws_obj);
2424                 dev_priv->hws_obj = NULL;
2425                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
2426
2427                 /* Write high address into HWS_PGA when disabling. */
2428                 I915_WRITE(HWS_PGA, 0x1ffff000);
2429         }
2430 }
2431
2432 int
2433 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2434                        struct drm_file *file_priv)
2435 {
2436         struct drm_i915_private *dev_priv = dev->dev_private;
2437         int ret;
2438
2439         if (drm_core_check_feature(dev, DRIVER_MODESET))
2440                 return 0;
2441
2442         if (dev_priv->mm.wedged) {
2443                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
2444                 dev_priv->mm.wedged = 0;
2445         }
2446
2447         ret = i915_gem_init_ringbuffer(dev);
2448         if (ret != 0)
2449                 return ret;
2450
2451         mutex_lock(&dev->struct_mutex);
2452         BUG_ON(!list_empty(&dev_priv->mm.active_list));
2453         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2454         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
2455         BUG_ON(!list_empty(&dev_priv->mm.request_list));
2456         dev_priv->mm.suspended = 0;
2457         mutex_unlock(&dev->struct_mutex);
2458         return 0;
2459 }
2460
2461 int
2462 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2463                        struct drm_file *file_priv)
2464 {
2465         int ret;
2466
2467         if (drm_core_check_feature(dev, DRIVER_MODESET))
2468                 return 0;
2469
2470         mutex_lock(&dev->struct_mutex);
2471         ret = i915_gem_idle(dev);
2472         if (ret == 0)
2473                 i915_gem_cleanup_ringbuffer(dev);
2474         mutex_unlock(&dev->struct_mutex);
2475
2476         return 0;
2477 }
2478
2479 void
2480 i915_gem_lastclose(struct drm_device *dev)
2481 {
2482         int ret;
2483         struct drm_i915_private *dev_priv = dev->dev_private;
2484
2485         mutex_lock(&dev->struct_mutex);
2486
2487         if (dev_priv->ring.ring_obj != NULL) {
2488                 ret = i915_gem_idle(dev);
2489                 if (ret)
2490                         DRM_ERROR("failed to idle hardware: %d\n", ret);
2491
2492                 i915_gem_cleanup_ringbuffer(dev);
2493         }
2494
2495         mutex_unlock(&dev->struct_mutex);
2496 }
2497
2498 void i915_gem_load(struct drm_device *dev)
2499 {
2500         struct drm_i915_private *dev_priv = dev->dev_private;
2501
2502         INIT_LIST_HEAD(&dev_priv->mm.active_list);
2503         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
2504         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
2505         INIT_LIST_HEAD(&dev_priv->mm.request_list);
2506         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
2507                           i915_gem_retire_work_handler);
2508         dev_priv->mm.next_gem_seqno = 1;
2509
2510         i915_gem_detect_bit_6_swizzle(dev);
2511 }