NV50: basic fbcon + misc fixes
[platform/upstream/libdrm.git] / linux-core / i915_fence.c
1 /**************************************************************************
2  *
3  * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
4  * All Rights Reserved.
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14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
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22  * The above copyright notice and this permission notice (including the
23  * next paragraph) shall be included in all copies or substantial portions
24  * of the Software.
25  *
26  *
27  **************************************************************************/
28 /*
29  * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
30  */
31
32 #include "drmP.h"
33 #include "drm.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36
37 /*
38  * Initiate a sync flush if it's not already pending.
39  */
40
41 static inline void i915_initiate_rwflush(struct drm_i915_private *dev_priv,
42                                          struct drm_fence_class_manager *fc)
43 {
44         if ((fc->pending_flush & DRM_I915_FENCE_TYPE_RW) &&
45             !dev_priv->flush_pending) {
46                 dev_priv->flush_sequence = (uint32_t) READ_BREADCRUMB(dev_priv);
47                 dev_priv->flush_flags = fc->pending_flush;
48                 dev_priv->saved_flush_status = READ_HWSP(dev_priv, 0);
49                 I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
50                 dev_priv->flush_pending = 1;
51                 fc->pending_flush &= ~DRM_I915_FENCE_TYPE_RW;
52         }
53 }
54
55 static inline void i915_report_rwflush(struct drm_device *dev,
56                                        struct drm_i915_private *dev_priv)
57 {
58         if (unlikely(dev_priv->flush_pending)) {
59
60                 uint32_t flush_flags;
61                 uint32_t i_status;
62                 uint32_t flush_sequence;
63
64                 i_status = READ_HWSP(dev_priv, 0);
65                 if ((i_status & (1 << 12)) !=
66                     (dev_priv->saved_flush_status & (1 << 12))) {
67                         flush_flags = dev_priv->flush_flags;
68                         flush_sequence = dev_priv->flush_sequence;
69                         dev_priv->flush_pending = 0;
70                         drm_fence_handler(dev, 0, flush_sequence,
71                                           flush_flags, 0);
72                 }
73         }
74 }
75
76 static void i915_fence_flush(struct drm_device *dev,
77                              uint32_t fence_class)
78 {
79         struct drm_i915_private *dev_priv = 
80                 (struct drm_i915_private *) dev->dev_private;
81         struct drm_fence_manager *fm = &dev->fm;
82         struct drm_fence_class_manager *fc = &fm->fence_class[0];
83         unsigned long irq_flags;
84
85         if (unlikely(!dev_priv))
86                 return;
87
88         write_lock_irqsave(&fm->lock, irq_flags);
89         i915_initiate_rwflush(dev_priv, fc);
90         write_unlock_irqrestore(&fm->lock, irq_flags);
91 }
92
93
94 static void i915_fence_poll(struct drm_device *dev, uint32_t fence_class,
95                             uint32_t waiting_types)
96 {
97         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
98         struct drm_fence_manager *fm = &dev->fm;
99         struct drm_fence_class_manager *fc = &fm->fence_class[0];
100         uint32_t sequence;
101
102         if (unlikely(!dev_priv))
103                 return;
104
105         /*
106          * First, report any executed sync flush:
107          */
108
109         i915_report_rwflush(dev, dev_priv);
110
111         /*
112          * Report A new breadcrumb, and adjust IRQs.
113          */
114
115         if (waiting_types & DRM_FENCE_TYPE_EXE) {
116
117                 sequence = READ_BREADCRUMB(dev_priv);
118                 drm_fence_handler(dev, 0, sequence,
119                                   DRM_FENCE_TYPE_EXE, 0);
120
121                 if (dev_priv->fence_irq_on &&
122                     !(fc->waiting_types & DRM_FENCE_TYPE_EXE)) {
123                         i915_user_irq_off(dev);
124                         dev_priv->fence_irq_on = 0;
125                 } else if (!dev_priv->fence_irq_on &&
126                            (fc->waiting_types & DRM_FENCE_TYPE_EXE)) {
127                         i915_user_irq_on(dev);
128                         dev_priv->fence_irq_on = 1;
129                 }
130         }
131
132         /*
133          * There may be new RW flushes pending. Start them.
134          */
135         
136         i915_initiate_rwflush(dev_priv, fc); 
137
138         /*
139          * And possibly, but unlikely, they finish immediately.
140          */
141
142         i915_report_rwflush(dev, dev_priv);
143
144 }
145
146 static int i915_fence_emit_sequence(struct drm_device *dev, uint32_t class,
147                              uint32_t flags, uint32_t *sequence,
148                              uint32_t *native_type)
149 {
150         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
151         if (unlikely(!dev_priv))
152                 return -EINVAL;
153
154         i915_emit_irq(dev);
155         *sequence = (uint32_t) dev_priv->counter;
156         *native_type = DRM_FENCE_TYPE_EXE;
157         if (flags & DRM_I915_FENCE_FLAG_FLUSHED)
158                 *native_type |= DRM_I915_FENCE_TYPE_RW;
159
160         return 0;
161 }
162
163 void i915_fence_handler(struct drm_device *dev)
164 {
165         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
166         struct drm_fence_manager *fm = &dev->fm;
167         struct drm_fence_class_manager *fc = &fm->fence_class[0];
168
169         write_lock(&fm->lock);
170         if (likely(dev_priv->fence_irq_on))
171                 i915_fence_poll(dev, 0, fc->waiting_types);
172         write_unlock(&fm->lock);
173 }
174
175 /*
176  * We need a separate wait function since we need to poll for
177  * sync flushes.
178  */
179
180 static int i915_fence_wait(struct drm_fence_object *fence,
181                            int lazy, int interruptible, uint32_t mask)
182 {
183         struct drm_device *dev = fence->dev;
184         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
185         struct drm_fence_manager *fm = &dev->fm;
186         struct drm_fence_class_manager *fc = &fm->fence_class[0];
187         int ret;
188         unsigned long  _end = jiffies + 3 * DRM_HZ;
189
190         drm_fence_object_flush(fence, mask);
191         if (likely(interruptible))
192                 ret = wait_event_interruptible_timeout
193                         (fc->fence_queue, drm_fence_object_signaled(fence, DRM_FENCE_TYPE_EXE), 
194                          3 * DRM_HZ);
195         else 
196                 ret = wait_event_timeout
197                         (fc->fence_queue, drm_fence_object_signaled(fence, DRM_FENCE_TYPE_EXE), 
198                          3 * DRM_HZ);
199
200         if (unlikely(ret == -ERESTARTSYS))
201                 return -EAGAIN;
202
203         if (unlikely(ret == 0))
204                 return -EBUSY;
205
206         if (likely(mask == DRM_FENCE_TYPE_EXE || 
207                    drm_fence_object_signaled(fence, mask))) 
208                 return 0;
209
210         /*
211          * Remove this code snippet when fixed. HWSTAM doesn't let
212          * flush info through...
213          */
214
215         if (unlikely(dev_priv && !dev_priv->irq_enabled)) {
216                 unsigned long irq_flags;
217
218                 DRM_ERROR("X server disabled IRQs before releasing frame buffer.\n");
219                 msleep(100);
220                 dev_priv->flush_pending = 0;
221                 write_lock_irqsave(&fm->lock, irq_flags);
222                 drm_fence_handler(dev, fence->fence_class, 
223                                   fence->sequence, fence->type, 0);
224                 write_unlock_irqrestore(&fm->lock, irq_flags);
225         }
226
227         /*
228          * Poll for sync flush completion.
229          */
230
231         return drm_fence_wait_polling(fence, lazy, interruptible, mask, _end);
232 }
233
234 static uint32_t i915_fence_needed_flush(struct drm_fence_object *fence)
235 {
236         uint32_t flush_flags = fence->waiting_types & 
237                 ~(DRM_FENCE_TYPE_EXE | fence->signaled_types);
238
239         if (likely(flush_flags == 0 || 
240                    ((flush_flags & ~fence->native_types) == 0) || 
241                    (fence->signaled_types != DRM_FENCE_TYPE_EXE)))
242                 return 0;
243         else {
244                 struct drm_device *dev = fence->dev;
245                 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
246                 struct drm_fence_driver *driver = dev->driver->fence_driver;
247                 
248                 if (unlikely(!dev_priv))
249                         return 0;
250
251                 if (dev_priv->flush_pending) {
252                         uint32_t diff = (dev_priv->flush_sequence - fence->sequence) & 
253                                 driver->sequence_mask;
254
255                         if (diff < driver->wrap_diff)
256                                 return 0;
257                 }
258         }
259         return flush_flags;
260 }
261
262 struct drm_fence_driver i915_fence_driver = {
263         .num_classes = 1,
264         .wrap_diff = (1U << (BREADCRUMB_BITS - 1)),
265         .flush_diff = (1U << (BREADCRUMB_BITS - 2)),
266         .sequence_mask = BREADCRUMB_MASK,
267         .has_irq = NULL,
268         .emit = i915_fence_emit_sequence,
269         .flush = i915_fence_flush,
270         .poll = i915_fence_poll,
271         .needed_flush = i915_fence_needed_flush,
272         .wait = i915_fence_wait,
273 };