linux-core/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drm.h"
  33 #include "intel_drv.h"
  34 #include "i915_drv.h"
  35
  36 #include "drm_pciids.h"
  37
  38 static struct pci_device_id pciidlist[] = {
  39         i915_PCI_IDS
  40 };
  41
  42 #ifdef I915_HAVE_FENCE
  43 static struct drm_fence_driver i915_fence_driver = {
  44         .num_classes = 1,
  45         .wrap_diff = (1U << (BREADCRUMB_BITS - 1)),
  46         .flush_diff = (1U << (BREADCRUMB_BITS - 2)),
  47         .sequence_mask = BREADCRUMB_MASK,
  48         .lazy_capable = 1,
  49         .emit = i915_fence_emit_sequence,
  50         .poke_flush = i915_poke_flush,
  51         .has_irq = i915_fence_has_irq,
  52 };
  53 #endif
  54 #ifdef I915_HAVE_BUFFER
  55
  56 static uint32_t i915_mem_prios[] = {DRM_BO_MEM_VRAM, DRM_BO_MEM_PRIV0, DRM_BO_MEM_TT, DRM_BO_MEM_LOCAL};
  57 static uint32_t i915_busy_prios[] = {DRM_BO_MEM_TT, DRM_BO_MEM_PRIV0, DRM_BO_MEM_VRAM, DRM_BO_MEM_LOCAL};
  58
  59 static struct drm_bo_driver i915_bo_driver = {
  60         .mem_type_prio = i915_mem_prios,
  61         .mem_busy_prio = i915_busy_prios,
  62         .num_mem_type_prio = sizeof(i915_mem_prios)/sizeof(uint32_t),
  63         .num_mem_busy_prio = sizeof(i915_busy_prios)/sizeof(uint32_t),
  64         .create_ttm_backend_entry = i915_create_ttm_backend_entry,
  65         .fence_type = i915_fence_types,
  66         .invalidate_caches = i915_invalidate_caches,
  67         .init_mem_type = i915_init_mem_type,
  68         .evict_mask = i915_evict_mask,
  69         .move = i915_move,
  70         .ttm_cache_flush = i915_flush_ttm,
  71 };
  72 #endif
  73
  74 enum pipe {
  75     PIPE_A = 0,
  76     PIPE_B,
  77 };
  78
  79 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
  80 {
  81         struct drm_i915_private *dev_priv = dev->dev_private;
  82
  83         if (pipe == PIPE_A)
  84                 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
  85         else
  86                 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
  87 }
  88
  89 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
  90 {
  91         struct drm_i915_private *dev_priv = dev->dev_private;
  92         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
  93         u32 *array;
  94         int i;
  95
  96         if (!i915_pipe_enabled(dev, pipe))
  97                 return;
  98
  99         if (pipe == PIPE_A)
 100                 array = dev_priv->save_palette_a;
 101         else
 102                 array = dev_priv->save_palette_b;
 103
 104         for(i = 0; i < 256; i++)
 105                 array[i] = I915_READ(reg + (i << 2));
 106 }
 107
 108 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
 109 {
 110         struct drm_i915_private *dev_priv = dev->dev_private;
 111         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
 112         u32 *array;
 113         int i;
 114
 115         if (!i915_pipe_enabled(dev, pipe))
 116                 return;
 117
 118         if (pipe == PIPE_A)
 119                 array = dev_priv->save_palette_a;
 120         else
 121                 array = dev_priv->save_palette_b;
 122
 123         for(i = 0; i < 256; i++)
 124                 I915_WRITE(reg + (i << 2), array[i]);
 125 }
 126
 127 static u8 i915_read_indexed(u16 index_port, u16 data_port, u8 reg)
 128 {
 129         outb(reg, index_port);
 130         return inb(data_port);
 131 }
 132
 133 static u8 i915_read_ar(u16 st01, u8 reg, u16 palette_enable)
 134 {
 135         inb(st01);
 136         outb(palette_enable | reg, VGA_AR_INDEX);
 137         return inb(VGA_AR_DATA_READ);
 138 }
 139
 140 static void i915_write_ar(u8 st01, u8 reg, u8 val, u16 palette_enable)
 141 {
 142         inb(st01);
 143         outb(palette_enable | reg, VGA_AR_INDEX);
 144         outb(val, VGA_AR_DATA_WRITE);
 145 }
 146
 147 static void i915_write_indexed(u16 index_port, u16 data_port, u8 reg, u8 val)
 148 {
 149         outb(reg, index_port);
 150         outb(val, data_port);
 151 }
 152
 153 static void i915_save_vga(struct drm_device *dev)
 154 {
 155         struct drm_i915_private *dev_priv = dev->dev_private;
 156         int i;
 157         u16 cr_index, cr_data, st01;
 158
 159         /* VGA color palette registers */
 160         dev_priv->saveDACMASK = inb(VGA_DACMASK);
 161         /* DACCRX automatically increments during read */
 162         outb(0, VGA_DACRX);
 163         /* Read 3 bytes of color data from each index */
 164         for (i = 0; i < 256 * 3; i++)
 165                 dev_priv->saveDACDATA[i] = inb(VGA_DACDATA);
 166
 167         /* MSR bits */
 168         dev_priv->saveMSR = inb(VGA_MSR_READ);
 169         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 170                 cr_index = VGA_CR_INDEX_CGA;
 171                 cr_data = VGA_CR_DATA_CGA;
 172                 st01 = VGA_ST01_CGA;
 173         } else {
 174                 cr_index = VGA_CR_INDEX_MDA;
 175                 cr_data = VGA_CR_DATA_MDA;
 176                 st01 = VGA_ST01_MDA;
 177         }
 178
 179         /* CRT controller regs */
 180         i915_write_indexed(cr_index, cr_data, 0x11,
 181                            i915_read_indexed(cr_index, cr_data, 0x11) &
 182                            (~0x80));
 183         for (i = 0; i < 0x24; i++)
 184                 dev_priv->saveCR[i] =
 185                         i915_read_indexed(cr_index, cr_data, i);
 186         /* Make sure we don't turn off CR group 0 writes */
 187         dev_priv->saveCR[0x11] &= ~0x80;
 188
 189         /* Attribute controller registers */
 190         inb(st01);
 191         dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
 192         for (i = 0; i < 20; i++)
 193                 dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
 194         inb(st01);
 195         outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
 196
 197         /* Graphics controller registers */
 198         for (i = 0; i < 9; i++)
 199                 dev_priv->saveGR[i] =
 200                         i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, i);
 201
 202         dev_priv->saveGR[0x10] =
 203                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10);
 204         dev_priv->saveGR[0x11] =
 205                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11);
 206         dev_priv->saveGR[0x18] =
 207                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18);
 208
 209         /* Sequencer registers */
 210         for (i = 0; i < 8; i++)
 211                 dev_priv->saveSR[i] =
 212                         i915_read_indexed(VGA_SR_INDEX, VGA_SR_DATA, i);
 213 }
 214
 215 static void i915_restore_vga(struct drm_device *dev)
 216 {
 217         struct drm_i915_private *dev_priv = dev->dev_private;
 218         int i;
 219         u16 cr_index, cr_data, st01;
 220
 221         /* MSR bits */
 222         outb(dev_priv->saveMSR, VGA_MSR_WRITE);
 223         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 224                 cr_index = VGA_CR_INDEX_CGA;
 225                 cr_data = VGA_CR_DATA_CGA;
 226                 st01 = VGA_ST01_CGA;
 227         } else {
 228                 cr_index = VGA_CR_INDEX_MDA;
 229                 cr_data = VGA_CR_DATA_MDA;
 230                 st01 = VGA_ST01_MDA;
 231         }
 232
 233         /* Sequencer registers, don't write SR07 */
 234         for (i = 0; i < 7; i++)
 235                 i915_write_indexed(VGA_SR_INDEX, VGA_SR_DATA, i,
 236                                    dev_priv->saveSR[i]);
 237
 238         /* CRT controller regs */
 239         /* Enable CR group 0 writes */
 240         i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
 241         for (i = 0; i < 0x24; i++)
 242                 i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);
 243
 244         /* Graphics controller regs */
 245         for (i = 0; i < 9; i++)
 246                 i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, i,
 247                                    dev_priv->saveGR[i]);
 248
 249         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10,
 250                            dev_priv->saveGR[0x10]);
 251         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11,
 252                            dev_priv->saveGR[0x11]);
 253         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18,
 254                            dev_priv->saveGR[0x18]);
 255
 256         /* Attribute controller registers */
 257         for (i = 0; i < 20; i++)
 258                 i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
 259         inb(st01); /* switch back to index mode */
 260         outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX);
 261
 262         /* VGA color palette registers */
 263         outb(dev_priv->saveDACMASK, VGA_DACMASK);
 264         /* DACCRX automatically increments during read */
 265         outb(0, VGA_DACWX);
 266         /* Read 3 bytes of color data from each index */
 267         for (i = 0; i < 256 * 3; i++)
 268                 outb(dev_priv->saveDACDATA[i], VGA_DACDATA);
 269
 270 }
 271
 272 static int i915_suspend(struct drm_device *dev)
 273 {
 274         struct drm_i915_private *dev_priv = dev->dev_private;
 275         int i;
 276
 277         if (!dev || !dev_priv) {
 278                 printk(KERN_ERR "dev: %p, dev_priv: %p\n", dev, dev_priv);
 279                 printk(KERN_ERR "DRM not initialized, aborting suspend.\n");
 280                 return -ENODEV;
 281         }
 282
 283         pci_save_state(dev->pdev);
 284         pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
 285
 286         /* Pipe & plane A info */
 287         dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
 288         dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
 289         dev_priv->saveFPA0 = I915_READ(FPA0);
 290         dev_priv->saveFPA1 = I915_READ(FPA1);
 291         dev_priv->saveDPLL_A = I915_READ(DPLL_A);
 292         if (IS_I965G(dev))
 293                 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
 294         dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
 295         dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
 296         dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
 297         dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
 298         dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
 299         dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
 300         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
 301
 302         dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
 303         dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
 304         dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
 305         dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
 306         dev_priv->saveDSPABASE = I915_READ(DSPABASE);
 307         if (IS_I965G(dev)) {
 308                 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
 309                 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
 310         }
 311         i915_save_palette(dev, PIPE_A);
 312
 313         /* Pipe & plane B info */
 314         dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
 315         dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
 316         dev_priv->saveFPB0 = I915_READ(FPB0);
 317         dev_priv->saveFPB1 = I915_READ(FPB1);
 318         dev_priv->saveDPLL_B = I915_READ(DPLL_B);
 319         if (IS_I965G(dev))
 320                 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
 321         dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
 322         dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
 323         dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
 324         dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
 325         dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
 326         dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
 327         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
 328
 329         dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
 330         dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
 331         dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
 332         dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
 333         dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
 334         if (IS_I965GM(dev)) {
 335                 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
 336                 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
 337         }
 338         i915_save_palette(dev, PIPE_B);
 339
 340         /* CRT state */
 341         dev_priv->saveADPA = I915_READ(ADPA);
 342
 343         /* LVDS state */
 344         dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
 345         dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
 346         dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
 347         if (IS_I965G(dev))
 348                 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
 349         if (IS_MOBILE(dev) && !IS_I830(dev))
 350                 dev_priv->saveLVDS = I915_READ(LVDS);
 351         if (!IS_I830(dev) && !IS_845G(dev))
 352                 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
 353         dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON);
 354         dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF);
 355         dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);
 356
 357         /* FIXME: save TV & SDVO state */
 358
 359         /* FBC state */
 360         dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
 361         dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
 362         dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
 363         dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
 364
 365         /* VGA state */
 366         dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
 367         dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
 368         dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
 369         dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
 370
 371         /* Scratch space */
 372         for (i = 0; i < 16; i++) {
 373                 dev_priv->saveSWF0[i] = I915_READ(SWF0 + (i << 2));
 374                 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
 375         }
 376         for (i = 0; i < 3; i++)
 377                 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
 378
 379         i915_save_vga(dev);
 380
 381         /* Shut down the device */
 382         pci_disable_device(dev->pdev);
 383         pci_set_power_state(dev->pdev, PCI_D3hot);
 384
 385         return 0;
 386 }
 387
 388 static int i915_resume(struct drm_device *dev)
 389 {
 390         struct drm_i915_private *dev_priv = dev->dev_private;
 391         int i;
 392
 393         pci_set_power_state(dev->pdev, PCI_D0);
 394         pci_restore_state(dev->pdev);
 395         if (pci_enable_device(dev->pdev))
 396                 return -1;
 397
 398         pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
 399
 400         /* Pipe & plane A info */
 401         /* Prime the clock */
 402         if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
 403                 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
 404                            ~DPLL_VCO_ENABLE);
 405                 udelay(150);
 406         }
 407         I915_WRITE(FPA0, dev_priv->saveFPA0);
 408         I915_WRITE(FPA1, dev_priv->saveFPA1);
 409         /* Actually enable it */
 410         I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
 411         udelay(150);
 412         if (IS_I965G(dev))
 413                 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
 414         udelay(150);
 415
 416         /* Restore mode */
 417         I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
 418         I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
 419         I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
 420         I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
 421         I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
 422         I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
 423         I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
 424
 425         /* Restore plane info */
 426         I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
 427         I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
 428         I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
 429         I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
 430         I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
 431         if (IS_I965G(dev)) {
 432                 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
 433                 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
 434         }
 435         I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
 436         i915_restore_palette(dev, PIPE_A);
 437         /* Enable the plane */
 438         I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
 439         I915_WRITE(DSPABASE, I915_READ(DSPABASE));
 440
 441         /* Pipe & plane B info */
 442         if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
 443                 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
 444                            ~DPLL_VCO_ENABLE);
 445                 udelay(150);
 446         }
 447         I915_WRITE(FPB0, dev_priv->saveFPB0);
 448         I915_WRITE(FPB1, dev_priv->saveFPB1);
 449         /* Actually enable it */
 450         I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
 451         udelay(150);
 452         if (IS_I965G(dev))
 453                 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
 454         udelay(150);
 455
 456         /* Restore mode */
 457         I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
 458         I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
 459         I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
 460         I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
 461         I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
 462         I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
 463         I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
 464
 465         /* Restore plane info */
 466         I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
 467         I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
 468         I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
 469         I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
 470         I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
 471         if (IS_I965G(dev)) {
 472                 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
 473                 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
 474         }
 475         I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
 476         i915_restore_palette(dev, PIPE_A);
 477         /* Enable the plane */
 478         I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
 479         I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
 480
 481         /* CRT state */
 482         I915_WRITE(ADPA, dev_priv->saveADPA);
 483
 484         /* LVDS state */
 485         if (IS_I965G(dev))
 486                 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
 487         if (IS_MOBILE(dev) && !IS_I830(dev))
 488                 I915_WRITE(LVDS, dev_priv->saveLVDS);
 489         if (!IS_I830(dev) && !IS_845G(dev))
 490                 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
 491
 492         I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
 493         I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
 494         I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON);
 495         I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF);
 496         I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
 497         I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
 498
 499         /* FIXME: restore TV & SDVO state */
 500
 501         /* FBC info */
 502         I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
 503         I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
 504         I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
 505         I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
 506
 507         /* VGA state */
 508         I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
 509         I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
 510         I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
 511         I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
 512         udelay(150);
 513
 514         for (i = 0; i < 16; i++) {
 515                 I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF0[i]);
 516                 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
 517         }
 518         for (i = 0; i < 3; i++)
 519                 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
 520
 521         i915_restore_vga(dev);
 522
 523         return 0;
 524 }
 525
 526 static int probe(struct pci_dev *pdev, const struct pci_device_id *ent);
 527 static struct drm_driver driver = {
 528         /* don't use mtrr's here, the Xserver or user space app should
 529          * deal with them for intel hardware.
 530          */
 531         .driver_features =
 532             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR | */
 533             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL |
 534             DRIVER_IRQ_VBL2,
 535         .load = i915_driver_load,
 536         .unload = i915_driver_unload,
 537         .lastclose = i915_driver_lastclose,
 538         .preclose = i915_driver_preclose,
 539         .suspend = i915_suspend,
 540         .resume = i915_resume,
 541         .device_is_agp = i915_driver_device_is_agp,
 542         .vblank_wait = i915_driver_vblank_wait,
 543         .vblank_wait2 = i915_driver_vblank_wait2,
 544         .irq_preinstall = i915_driver_irq_preinstall,
 545         .irq_postinstall = i915_driver_irq_postinstall,
 546         .irq_uninstall = i915_driver_irq_uninstall,
 547         .irq_handler = i915_driver_irq_handler,
 548         .reclaim_buffers = drm_core_reclaim_buffers,
 549         .get_map_ofs = drm_core_get_map_ofs,
 550         .get_reg_ofs = drm_core_get_reg_ofs,
 551         .fb_probe = intelfb_probe,
 552         .fb_remove = intelfb_remove,
 553         .ioctls = i915_ioctls,
 554         .fops = {
 555                 .owner = THIS_MODULE,
 556                 .open = drm_open,
 557                 .release = drm_release,
 558                 .ioctl = drm_ioctl,
 559                 .mmap = drm_mmap,
 560                 .poll = drm_poll,
 561                 .fasync = drm_fasync,
 562 #if defined(CONFIG_COMPAT) && LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
 563                 .compat_ioctl = i915_compat_ioctl,
 564 #endif
 565                 },
 566         .pci_driver = {
 567                 .name = DRIVER_NAME,
 568                 .id_table = pciidlist,
 569                 .probe = probe,
 570                 .remove = __devexit_p(drm_cleanup_pci),
 571                 },
 572 #ifdef I915_HAVE_FENCE
 573         .fence_driver = &i915_fence_driver,
 574 #endif
 575 #ifdef I915_HAVE_BUFFER
 576         .bo_driver = &i915_bo_driver,
 577 #endif
 578         .name = DRIVER_NAME,
 579         .desc = DRIVER_DESC,
 580         .date = DRIVER_DATE,
 581         .major = DRIVER_MAJOR,
 582         .minor = DRIVER_MINOR,
 583         .patchlevel = DRIVER_PATCHLEVEL,
 584 };
 585
 586 static int probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 587 {
 588         return drm_get_dev(pdev, ent, &driver);
 589 }
 590
 591 static int __init i915_init(void)
 592 {
 593         driver.num_ioctls = i915_max_ioctl;
 594         return drm_init(&driver, pciidlist);
 595 }
 596
 597 static void __exit i915_exit(void)
 598 {
 599         drm_exit(&driver);
 600 }
 601
 602 module_init(i915_init);
 603 module_exit(i915_exit);
 604
 605 MODULE_AUTHOR(DRIVER_AUTHOR);
 606 MODULE_DESCRIPTION(DRIVER_DESC);
 607 MODULE_LICENSE("GPL and additional rights");