linux-core/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drm.h"
  33 #include "i915_drv.h"
  34
  35 #include "drm_pciids.h"
  36
  37 static struct pci_device_id pciidlist[] = {
  38         i915_PCI_IDS
  39 };
  40
  41 #ifdef I915_HAVE_FENCE
  42 static struct drm_fence_driver i915_fence_driver = {
  43         .num_classes = 1,
  44         .wrap_diff = (1U << (BREADCRUMB_BITS - 1)),
  45         .flush_diff = (1U << (BREADCRUMB_BITS - 2)),
  46         .sequence_mask = BREADCRUMB_MASK,
  47         .lazy_capable = 1,
  48         .emit = i915_fence_emit_sequence,
  49         .poke_flush = i915_poke_flush,
  50         .has_irq = i915_fence_has_irq,
  51 };
  52 #endif
  53 #ifdef I915_HAVE_BUFFER
  54
  55 static uint32_t i915_mem_prios[] = {DRM_BO_MEM_PRIV0, DRM_BO_MEM_TT, DRM_BO_MEM_LOCAL};
  56 static uint32_t i915_busy_prios[] = {DRM_BO_MEM_TT, DRM_BO_MEM_PRIV0, DRM_BO_MEM_LOCAL};
  57
  58 static struct drm_bo_driver i915_bo_driver = {
  59         .mem_type_prio = i915_mem_prios,
  60         .mem_busy_prio = i915_busy_prios,
  61         .num_mem_type_prio = sizeof(i915_mem_prios)/sizeof(uint32_t),
  62         .num_mem_busy_prio = sizeof(i915_busy_prios)/sizeof(uint32_t),
  63         .create_ttm_backend_entry = i915_create_ttm_backend_entry,
  64         .fence_type = i915_fence_types,
  65         .invalidate_caches = i915_invalidate_caches,
  66         .init_mem_type = i915_init_mem_type,
  67         .evict_mask = i915_evict_mask,
  68         .move = i915_move,
  69         .ttm_cache_flush = i915_flush_ttm,
  70 };
  71 #endif
  72
  73 enum pipe {
  74     PIPE_A = 0,
  75     PIPE_B,
  76 };
  77
  78 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
  79 {
  80         struct drm_i915_private *dev_priv = dev->dev_private;
  81
  82         if (pipe == PIPE_A)
  83                 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
  84         else
  85                 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
  86 }
  87
  88 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
  89 {
  90         struct drm_i915_private *dev_priv = dev->dev_private;
  91         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
  92         u32 *array;
  93         int i;
  94
  95         if (!i915_pipe_enabled(dev, pipe))
  96                 return;
  97
  98         if (pipe == PIPE_A)
  99                 array = dev_priv->save_palette_a;
 100         else
 101                 array = dev_priv->save_palette_b;
 102
 103         for(i = 0; i < 256; i++)
 104                 array[i] = I915_READ(reg + (i << 2));
 105 }
 106
 107 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
 108 {
 109         struct drm_i915_private *dev_priv = dev->dev_private;
 110         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
 111         u32 *array;
 112         int i;
 113
 114         if (!i915_pipe_enabled(dev, pipe))
 115                 return;
 116
 117         if (pipe == PIPE_A)
 118                 array = dev_priv->save_palette_a;
 119         else
 120                 array = dev_priv->save_palette_b;
 121
 122         for(i = 0; i < 256; i++)
 123                 I915_WRITE(reg + (i << 2), array[i]);
 124 }
 125
 126 static u8 i915_read_indexed(u16 index_port, u16 data_port, u8 reg)
 127 {
 128         outb(reg, index_port);
 129         return inb(data_port);
 130 }
 131
 132 static u8 i915_read_ar(u16 st01, u8 reg, u16 palette_enable)
 133 {
 134         inb(st01);
 135         outb(palette_enable | reg, VGA_AR_INDEX);
 136         return inb(VGA_AR_DATA_READ);
 137 }
 138
 139 static void i915_write_ar(u8 st01, u8 reg, u8 val, u16 palette_enable)
 140 {
 141         inb(st01);
 142         outb(palette_enable | reg, VGA_AR_INDEX);
 143         outb(val, VGA_AR_DATA_WRITE);
 144 }
 145
 146 static void i915_write_indexed(u16 index_port, u16 data_port, u8 reg, u8 val)
 147 {
 148         outb(reg, index_port);
 149         outb(val, data_port);
 150 }
 151
 152 static void i915_save_vga(struct drm_device *dev)
 153 {
 154         struct drm_i915_private *dev_priv = dev->dev_private;
 155         int i;
 156         u16 cr_index, cr_data, st01;
 157
 158         /* VGA color palette registers */
 159         dev_priv->saveDACMASK = inb(VGA_DACMASK);
 160         /* DACCRX automatically increments during read */
 161         outb(0, VGA_DACRX);
 162         /* Read 3 bytes of color data from each index */
 163         for (i = 0; i < 256 * 3; i++)
 164                 dev_priv->saveDACDATA[i] = inb(VGA_DACDATA);
 165
 166         /* MSR bits */
 167         dev_priv->saveMSR = inb(VGA_MSR_READ);
 168         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 169                 cr_index = VGA_CR_INDEX_CGA;
 170                 cr_data = VGA_CR_DATA_CGA;
 171                 st01 = VGA_ST01_CGA;
 172         } else {
 173                 cr_index = VGA_CR_INDEX_MDA;
 174                 cr_data = VGA_CR_DATA_MDA;
 175                 st01 = VGA_ST01_MDA;
 176         }
 177
 178         /* CRT controller regs */
 179         i915_write_indexed(cr_index, cr_data, 0x11,
 180                            i915_read_indexed(cr_index, cr_data, 0x11) &
 181                            (~0x80));
 182         for (i = 0; i < 0x24; i++)
 183                 dev_priv->saveCR[i] =
 184                         i915_read_indexed(cr_index, cr_data, i);
 185         /* Make sure we don't turn off CR group 0 writes */
 186         dev_priv->saveCR[0x11] &= ~0x80;
 187
 188         /* Attribute controller registers */
 189         inb(st01);
 190         dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
 191         for (i = 0; i < 20; i++)
 192                 dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
 193         inb(st01);
 194         outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
 195
 196         /* Graphics controller registers */
 197         for (i = 0; i < 9; i++)
 198                 dev_priv->saveGR[i] =
 199                         i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, i);
 200
 201         dev_priv->saveGR[0x10] =
 202                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10);
 203         dev_priv->saveGR[0x11] =
 204                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11);
 205         dev_priv->saveGR[0x18] =
 206                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18);
 207
 208         /* Sequencer registers */
 209         for (i = 0; i < 8; i++)
 210                 dev_priv->saveSR[i] =
 211                         i915_read_indexed(VGA_SR_INDEX, VGA_SR_DATA, i);
 212 }
 213
 214 static void i915_restore_vga(struct drm_device *dev)
 215 {
 216         struct drm_i915_private *dev_priv = dev->dev_private;
 217         int i;
 218         u16 cr_index, cr_data, st01;
 219
 220         /* MSR bits */
 221         outb(dev_priv->saveMSR, VGA_MSR_WRITE);
 222         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 223                 cr_index = VGA_CR_INDEX_CGA;
 224                 cr_data = VGA_CR_DATA_CGA;
 225                 st01 = VGA_ST01_CGA;
 226         } else {
 227                 cr_index = VGA_CR_INDEX_MDA;
 228                 cr_data = VGA_CR_DATA_MDA;
 229                 st01 = VGA_ST01_MDA;
 230         }
 231
 232         /* Sequencer registers, don't write SR07 */
 233         for (i = 0; i < 7; i++)
 234                 i915_write_indexed(VGA_SR_INDEX, VGA_SR_DATA, i,
 235                                    dev_priv->saveSR[i]);
 236
 237         /* CRT controller regs */
 238         /* Enable CR group 0 writes */
 239         i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
 240         for (i = 0; i < 0x24; i++)
 241                 i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);
 242
 243         /* Graphics controller regs */
 244         for (i = 0; i < 9; i++)
 245                 i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, i,
 246                                    dev_priv->saveGR[i]);
 247
 248         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10,
 249                            dev_priv->saveGR[0x10]);
 250         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11,
 251                            dev_priv->saveGR[0x11]);
 252         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18,
 253                            dev_priv->saveGR[0x18]);
 254
 255         /* Attribute controller registers */
 256         for (i = 0; i < 20; i++)
 257                 i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
 258         inb(st01); /* switch back to index mode */
 259         outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX);
 260
 261         /* VGA color palette registers */
 262         outb(dev_priv->saveDACMASK, VGA_DACMASK);
 263         /* DACCRX automatically increments during read */
 264         outb(0, VGA_DACWX);
 265         /* Read 3 bytes of color data from each index */
 266         for (i = 0; i < 256 * 3; i++)
 267                 outb(dev_priv->saveDACDATA[i], VGA_DACDATA);
 268
 269 }
 270
 271 static int i915_suspend(struct drm_device *dev)
 272 {
 273         struct drm_i915_private *dev_priv = dev->dev_private;
 274         int i;
 275
 276         if (!dev || !dev_priv) {
 277                 printk(KERN_ERR "dev: %p, dev_priv: %p\n", dev, dev_priv);
 278                 printk(KERN_ERR "DRM not initialized, aborting suspend.\n");
 279                 return -ENODEV;
 280         }
 281
 282         pci_save_state(dev->pdev);
 283         pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
 284
 285         /* Pipe & plane A info */
 286         dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
 287         dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
 288         dev_priv->saveFPA0 = I915_READ(FPA0);
 289         dev_priv->saveFPA1 = I915_READ(FPA1);
 290         dev_priv->saveDPLL_A = I915_READ(DPLL_A);
 291         if (IS_I965G(dev))
 292                 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
 293         dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
 294         dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
 295         dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
 296         dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
 297         dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
 298         dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
 299         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
 300
 301         dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
 302         dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
 303         dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
 304         dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
 305         dev_priv->saveDSPABASE = I915_READ(DSPABASE);
 306         if (IS_I965G(dev)) {
 307                 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
 308                 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
 309         }
 310         i915_save_palette(dev, PIPE_A);
 311
 312         /* Pipe & plane B info */
 313         dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
 314         dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
 315         dev_priv->saveFPB0 = I915_READ(FPB0);
 316         dev_priv->saveFPB1 = I915_READ(FPB1);
 317         dev_priv->saveDPLL_B = I915_READ(DPLL_B);
 318         if (IS_I965G(dev))
 319                 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
 320         dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
 321         dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
 322         dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
 323         dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
 324         dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
 325         dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
 326         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
 327
 328         dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
 329         dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
 330         dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
 331         dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
 332         dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
 333         if (IS_I965GM(dev)) {
 334                 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
 335                 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
 336         }
 337         i915_save_palette(dev, PIPE_B);
 338
 339         /* CRT state */
 340         dev_priv->saveADPA = I915_READ(ADPA);
 341
 342         /* LVDS state */
 343         dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
 344         dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
 345         dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
 346         if (IS_I965G(dev))
 347                 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
 348         if (IS_MOBILE(dev) && !IS_I830(dev))
 349                 dev_priv->saveLVDS = I915_READ(LVDS);
 350         if (!IS_I830(dev) && !IS_845G(dev))
 351                 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
 352         dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON);
 353         dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF);
 354         dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);
 355
 356         /* FIXME: save TV & SDVO state */
 357
 358         /* FBC state */
 359         dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
 360         dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
 361         dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
 362         dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
 363
 364         /* VGA state */
 365         dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
 366         dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
 367         dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
 368         dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
 369
 370         /* Scratch space */
 371         for (i = 0; i < 16; i++) {
 372                 dev_priv->saveSWF0[i] = I915_READ(SWF0 + (i << 2));
 373                 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
 374         }
 375         for (i = 0; i < 3; i++)
 376                 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
 377
 378         i915_save_vga(dev);
 379
 380         /* Shut down the device */
 381         pci_disable_device(dev->pdev);
 382         pci_set_power_state(dev->pdev, PCI_D3hot);
 383
 384         return 0;
 385 }
 386
 387 static int i915_resume(struct drm_device *dev)
 388 {
 389         struct drm_i915_private *dev_priv = dev->dev_private;
 390         int i;
 391
 392         pci_set_power_state(dev->pdev, PCI_D0);
 393         pci_restore_state(dev->pdev);
 394         if (pci_enable_device(dev->pdev))
 395                 return -1;
 396
 397         pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
 398
 399         /* Pipe & plane A info */
 400         /* Prime the clock */
 401         if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
 402                 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
 403                            ~DPLL_VCO_ENABLE);
 404                 udelay(150);
 405         }
 406         I915_WRITE(FPA0, dev_priv->saveFPA0);
 407         I915_WRITE(FPA1, dev_priv->saveFPA1);
 408         /* Actually enable it */
 409         I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
 410         udelay(150);
 411         if (IS_I965G(dev))
 412                 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
 413         udelay(150);
 414
 415         /* Restore mode */
 416         I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
 417         I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
 418         I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
 419         I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
 420         I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
 421         I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
 422         I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
 423
 424         /* Restore plane info */
 425         I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
 426         I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
 427         I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
 428         I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
 429         I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
 430         if (IS_I965G(dev)) {
 431                 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
 432                 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
 433         }
 434         I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
 435         i915_restore_palette(dev, PIPE_A);
 436         /* Enable the plane */
 437         I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
 438         I915_WRITE(DSPABASE, I915_READ(DSPABASE));
 439
 440         /* Pipe & plane B info */
 441         if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
 442                 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
 443                            ~DPLL_VCO_ENABLE);
 444                 udelay(150);
 445         }
 446         I915_WRITE(FPB0, dev_priv->saveFPB0);
 447         I915_WRITE(FPB1, dev_priv->saveFPB1);
 448         /* Actually enable it */
 449         I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
 450         udelay(150);
 451         if (IS_I965G(dev))
 452                 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
 453         udelay(150);
 454
 455         /* Restore mode */
 456         I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
 457         I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
 458         I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
 459         I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
 460         I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
 461         I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
 462         I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
 463
 464         /* Restore plane info */
 465         I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
 466         I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
 467         I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
 468         I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
 469         I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
 470         if (IS_I965G(dev)) {
 471                 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
 472                 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
 473         }
 474         I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
 475         i915_restore_palette(dev, PIPE_A);
 476         /* Enable the plane */
 477         I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
 478         I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
 479
 480         /* CRT state */
 481         I915_WRITE(ADPA, dev_priv->saveADPA);
 482
 483         /* LVDS state */
 484         if (IS_I965G(dev))
 485                 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
 486         if (IS_MOBILE(dev) && !IS_I830(dev))
 487                 I915_WRITE(LVDS, dev_priv->saveLVDS);
 488         if (!IS_I830(dev) && !IS_845G(dev))
 489                 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
 490
 491         I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
 492         I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
 493         I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON);
 494         I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF);
 495         I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
 496         I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
 497
 498         /* FIXME: restore TV & SDVO state */
 499
 500         /* FBC info */
 501         I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
 502         I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
 503         I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
 504         I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
 505
 506         /* VGA state */
 507         I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
 508         I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
 509         I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
 510         I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
 511         udelay(150);
 512
 513         for (i = 0; i < 16; i++) {
 514                 I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF0[i]);
 515                 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
 516         }
 517         for (i = 0; i < 3; i++)
 518                 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
 519
 520         i915_restore_vga(dev);
 521
 522         return 0;
 523 }
 524
 525 static int probe(struct pci_dev *pdev, const struct pci_device_id *ent);
 526 static struct drm_driver driver = {
 527         /* don't use mtrr's here, the Xserver or user space app should
 528          * deal with them for intel hardware.
 529          */
 530         .driver_features =
 531             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR | */
 532             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED,
 533         .load = i915_driver_load,
 534         .unload = i915_driver_unload,
 535         .firstopen = i915_driver_firstopen,
 536         .lastclose = i915_driver_lastclose,
 537         .preclose = i915_driver_preclose,
 538         .suspend = i915_suspend,
 539         .resume = i915_resume,
 540         .device_is_agp = i915_driver_device_is_agp,
 541         .get_vblank_counter = i915_get_vblank_counter,
 542         .enable_vblank = i915_enable_vblank,
 543         .disable_vblank = i915_disable_vblank,
 544         .irq_preinstall = i915_driver_irq_preinstall,
 545         .irq_postinstall = i915_driver_irq_postinstall,
 546         .irq_uninstall = i915_driver_irq_uninstall,
 547         .irq_handler = i915_driver_irq_handler,
 548         .reclaim_buffers = drm_core_reclaim_buffers,
 549         .get_map_ofs = drm_core_get_map_ofs,
 550         .get_reg_ofs = drm_core_get_reg_ofs,
 551         .ioctls = i915_ioctls,
 552         .fops = {
 553                 .owner = THIS_MODULE,
 554                 .open = drm_open,
 555                 .release = drm_release,
 556                 .ioctl = drm_ioctl,
 557                 .mmap = drm_mmap,
 558                 .poll = drm_poll,
 559                 .fasync = drm_fasync,
 560 #if defined(CONFIG_COMPAT) && LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
 561                 .compat_ioctl = i915_compat_ioctl,
 562 #endif
 563                 },
 564         .pci_driver = {
 565                 .name = DRIVER_NAME,
 566                 .id_table = pciidlist,
 567                 .probe = probe,
 568                 .remove = __devexit_p(drm_cleanup_pci),
 569                 },
 570 #ifdef I915_HAVE_FENCE
 571         .fence_driver = &i915_fence_driver,
 572 #endif
 573 #ifdef I915_HAVE_BUFFER
 574         .bo_driver = &i915_bo_driver,
 575 #endif
 576         .name = DRIVER_NAME,
 577         .desc = DRIVER_DESC,
 578         .date = DRIVER_DATE,
 579         .major = DRIVER_MAJOR,
 580         .minor = DRIVER_MINOR,
 581         .patchlevel = DRIVER_PATCHLEVEL,
 582 };
 583
 584 static int probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 585 {
 586         return drm_get_dev(pdev, ent, &driver);
 587 }
 588
 589 static int __init i915_init(void)
 590 {
 591         driver.num_ioctls = i915_max_ioctl;
 592         return drm_init(&driver, pciidlist);
 593 }
 594
 595 static void __exit i915_exit(void)
 596 {
 597         drm_exit(&driver);
 598 }
 599
 600 module_init(i915_init);
 601 module_exit(i915_exit);
 602
 603 MODULE_AUTHOR(DRIVER_AUTHOR);
 604 MODULE_DESCRIPTION(DRIVER_DESC);
 605 MODULE_LICENSE("GPL and additional rights");