linux-core/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drm.h"
  33 #include "intel_drv.h"
  34 #include "i915_drv.h"
  35
  36 #include "drm_pciids.h"
  37
  38 static struct pci_device_id pciidlist[] = {
  39         i915_PCI_IDS
  40 };
  41
  42 unsigned int i915_modeset = 0;
  43 module_param_named(modeset, i915_modeset, int, 0400);
  44
  45 unsigned int i915_fbpercrtc = 0;
  46 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  47
  48 unsigned int i915_rightof = 1;
  49 module_param_named(i915_rightof, i915_rightof, int, 0400);
  50
  51 #ifdef I915_HAVE_FENCE
  52 extern struct drm_fence_driver i915_fence_driver;
  53 #endif
  54
  55 #ifdef I915_HAVE_BUFFER
  56
  57 static uint32_t i915_mem_prios[] = {DRM_BO_MEM_VRAM, DRM_BO_MEM_TT, DRM_BO_MEM_LOCAL};
  58 static uint32_t i915_busy_prios[] = {DRM_BO_MEM_TT, DRM_BO_MEM_VRAM, DRM_BO_MEM_LOCAL};
  59
  60 static struct drm_bo_driver i915_bo_driver = {
  61         .mem_type_prio = i915_mem_prios,
  62         .mem_busy_prio = i915_busy_prios,
  63         .num_mem_type_prio = sizeof(i915_mem_prios)/sizeof(uint32_t),
  64         .num_mem_busy_prio = sizeof(i915_busy_prios)/sizeof(uint32_t),
  65         .create_ttm_backend_entry = i915_create_ttm_backend_entry,
  66         .fence_type = i915_fence_type,
  67         .invalidate_caches = i915_invalidate_caches,
  68         .init_mem_type = i915_init_mem_type,
  69         .evict_flags = i915_evict_flags,
  70         .move = i915_move,
  71         .ttm_cache_flush = i915_flush_ttm,
  72         .command_stream_barrier = NULL,
  73 };
  74 #endif
  75
  76 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
  77 {
  78         struct drm_i915_private *dev_priv = dev->dev_private;
  79
  80         if (pipe == PIPE_A)
  81                 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
  82         else
  83                 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
  84 }
  85
  86 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
  87 {
  88         struct drm_i915_private *dev_priv = dev->dev_private;
  89         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
  90         u32 *array;
  91         int i;
  92
  93         if (!i915_pipe_enabled(dev, pipe))
  94                 return;
  95
  96         if (pipe == PIPE_A)
  97                 array = dev_priv->save_palette_a;
  98         else
  99                 array = dev_priv->save_palette_b;
 100
 101         for(i = 0; i < 256; i++)
 102                 array[i] = I915_READ(reg + (i << 2));
 103 }
 104
 105 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
 106 {
 107         struct drm_i915_private *dev_priv = dev->dev_private;
 108         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
 109         u32 *array;
 110         int i;
 111
 112         if (!i915_pipe_enabled(dev, pipe))
 113                 return;
 114
 115         if (pipe == PIPE_A)
 116                 array = dev_priv->save_palette_a;
 117         else
 118                 array = dev_priv->save_palette_b;
 119
 120         for(i = 0; i < 256; i++)
 121                 I915_WRITE(reg + (i << 2), array[i]);
 122 }
 123
 124 static u8 i915_read_indexed(u16 index_port, u16 data_port, u8 reg)
 125 {
 126         outb(reg, index_port);
 127         return inb(data_port);
 128 }
 129
 130 static u8 i915_read_ar(u16 st01, u8 reg, u16 palette_enable)
 131 {
 132         inb(st01);
 133         outb(palette_enable | reg, VGA_AR_INDEX);
 134         return inb(VGA_AR_DATA_READ);
 135 }
 136
 137 static void i915_write_ar(u8 st01, u8 reg, u8 val, u16 palette_enable)
 138 {
 139         inb(st01);
 140         outb(palette_enable | reg, VGA_AR_INDEX);
 141         outb(val, VGA_AR_DATA_WRITE);
 142 }
 143
 144 static void i915_write_indexed(u16 index_port, u16 data_port, u8 reg, u8 val)
 145 {
 146         outb(reg, index_port);
 147         outb(val, data_port);
 148 }
 149
 150 static void i915_save_vga(struct drm_device *dev)
 151 {
 152         struct drm_i915_private *dev_priv = dev->dev_private;
 153         int i;
 154         u16 cr_index, cr_data, st01;
 155
 156         /* VGA color palette registers */
 157         dev_priv->saveDACMASK = inb(VGA_DACMASK);
 158         /* DACCRX automatically increments during read */
 159         outb(0, VGA_DACRX);
 160         /* Read 3 bytes of color data from each index */
 161         for (i = 0; i < 256 * 3; i++)
 162                 dev_priv->saveDACDATA[i] = inb(VGA_DACDATA);
 163
 164         /* MSR bits */
 165         dev_priv->saveMSR = inb(VGA_MSR_READ);
 166         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 167                 cr_index = VGA_CR_INDEX_CGA;
 168                 cr_data = VGA_CR_DATA_CGA;
 169                 st01 = VGA_ST01_CGA;
 170         } else {
 171                 cr_index = VGA_CR_INDEX_MDA;
 172                 cr_data = VGA_CR_DATA_MDA;
 173                 st01 = VGA_ST01_MDA;
 174         }
 175
 176         /* CRT controller regs */
 177         i915_write_indexed(cr_index, cr_data, 0x11,
 178                            i915_read_indexed(cr_index, cr_data, 0x11) &
 179                            (~0x80));
 180         for (i = 0; i <= 0x24; i++)
 181                 dev_priv->saveCR[i] =
 182                         i915_read_indexed(cr_index, cr_data, i);
 183         /* Make sure we don't turn off CR group 0 writes */
 184         dev_priv->saveCR[0x11] &= ~0x80;
 185
 186         /* Attribute controller registers */
 187         inb(st01);
 188         dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
 189         for (i = 0; i <= 0x14; i++)
 190                 dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
 191         inb(st01);
 192         outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
 193         inb(st01);
 194
 195         /* Graphics controller registers */
 196         for (i = 0; i < 9; i++)
 197                 dev_priv->saveGR[i] =
 198                         i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, i);
 199
 200         dev_priv->saveGR[0x10] =
 201                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10);
 202         dev_priv->saveGR[0x11] =
 203                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11);
 204         dev_priv->saveGR[0x18] =
 205                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18);
 206
 207         /* Sequencer registers */
 208         for (i = 0; i < 8; i++)
 209                 dev_priv->saveSR[i] =
 210                         i915_read_indexed(VGA_SR_INDEX, VGA_SR_DATA, i);
 211 }
 212
 213 static void i915_restore_vga(struct drm_device *dev)
 214 {
 215         struct drm_i915_private *dev_priv = dev->dev_private;
 216         int i;
 217         u16 cr_index, cr_data, st01;
 218
 219         /* MSR bits */
 220         outb(dev_priv->saveMSR, VGA_MSR_WRITE);
 221         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 222                 cr_index = VGA_CR_INDEX_CGA;
 223                 cr_data = VGA_CR_DATA_CGA;
 224                 st01 = VGA_ST01_CGA;
 225         } else {
 226                 cr_index = VGA_CR_INDEX_MDA;
 227                 cr_data = VGA_CR_DATA_MDA;
 228                 st01 = VGA_ST01_MDA;
 229         }
 230
 231         /* Sequencer registers, don't write SR07 */
 232         for (i = 0; i < 7; i++)
 233                 i915_write_indexed(VGA_SR_INDEX, VGA_SR_DATA, i,
 234                                    dev_priv->saveSR[i]);
 235
 236         /* CRT controller regs */
 237         /* Enable CR group 0 writes */
 238         i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
 239         for (i = 0; i <= 0x24; i++)
 240                 i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);
 241
 242         /* Graphics controller regs */
 243         for (i = 0; i < 9; i++)
 244                 i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, i,
 245                                    dev_priv->saveGR[i]);
 246
 247         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10,
 248                            dev_priv->saveGR[0x10]);
 249         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11,
 250                            dev_priv->saveGR[0x11]);
 251         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18,
 252                            dev_priv->saveGR[0x18]);
 253
 254         /* Attribute controller registers */
 255         inb(st01); /* switch back to index mode */
 256         for (i = 0; i <= 0x14; i++)
 257                 i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
 258         inb(st01); /* switch back to index mode */
 259         outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX);
 260         inb(st01);
 261
 262         /* VGA color palette registers */
 263         outb(dev_priv->saveDACMASK, VGA_DACMASK);
 264         /* DACCRX automatically increments during read */
 265         outb(0, VGA_DACWX);
 266         /* Read 3 bytes of color data from each index */
 267         for (i = 0; i < 256 * 3; i++)
 268                 outb(dev_priv->saveDACDATA[i], VGA_DACDATA);
 269
 270 }
 271
 272 static int i915_suspend(struct drm_device *dev, pm_message_t state)
 273 {
 274         struct drm_i915_private *dev_priv = dev->dev_private;
 275         int i;
 276
 277         if (!dev || !dev_priv) {
 278                 printk(KERN_ERR "dev: %p, dev_priv: %p\n", dev, dev_priv);
 279                 printk(KERN_ERR "DRM not initialized, aborting suspend.\n");
 280                 return -ENODEV;
 281         }
 282
 283         if (state.event == PM_EVENT_PRETHAW)
 284                 return 0;
 285
 286         pci_save_state(dev->pdev);
 287         pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
 288
 289         /* Display arbitration control */
 290         dev_priv->saveDSPARB = I915_READ(DSPARB);
 291
 292         /* Pipe & plane A info */
 293         dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
 294         dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
 295         dev_priv->saveFPA0 = I915_READ(FPA0);
 296         dev_priv->saveFPA1 = I915_READ(FPA1);
 297         dev_priv->saveDPLL_A = I915_READ(DPLL_A);
 298         if (IS_I965G(dev))
 299                 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
 300         dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
 301         dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
 302         dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
 303         dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
 304         dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
 305         dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
 306         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
 307
 308         dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
 309         dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
 310         dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
 311         dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
 312         dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
 313         if (IS_I965G(dev)) {
 314                 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
 315                 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
 316         }
 317         i915_save_palette(dev, PIPE_A);
 318         dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
 319
 320         /* Pipe & plane B info */
 321         dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
 322         dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
 323         dev_priv->saveFPB0 = I915_READ(FPB0);
 324         dev_priv->saveFPB1 = I915_READ(FPB1);
 325         dev_priv->saveDPLL_B = I915_READ(DPLL_B);
 326         if (IS_I965G(dev))
 327                 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
 328         dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
 329         dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
 330         dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
 331         dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
 332         dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
 333         dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
 334         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
 335
 336         dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
 337         dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
 338         dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
 339         dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
 340         dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
 341         if (IS_I965GM(dev) || IS_IGD_GM(dev)) {
 342                 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
 343                 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
 344         }
 345         i915_save_palette(dev, PIPE_B);
 346         dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
 347
 348         /* CRT state */
 349         dev_priv->saveADPA = I915_READ(ADPA);
 350
 351         /* LVDS state */
 352         dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
 353         dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
 354         dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
 355         if (IS_I965G(dev))
 356                 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
 357         if (IS_MOBILE(dev) && !IS_I830(dev))
 358                 dev_priv->saveLVDS = I915_READ(LVDS);
 359         if (!IS_I830(dev) && !IS_845G(dev))
 360                 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
 361         dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
 362         dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
 363         dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
 364
 365         /* FIXME: save TV & SDVO state */
 366
 367         /* FBC state */
 368         dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
 369         dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
 370         dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
 371         dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
 372
 373         /* Interrupt state */
 374         dev_priv->saveIIR = I915_READ(IIR);
 375         dev_priv->saveIER = I915_READ(IER);
 376         dev_priv->saveIMR = I915_READ(IMR);
 377
 378         /* VGA state */
 379         dev_priv->saveVGA0 = I915_READ(VGA0);
 380         dev_priv->saveVGA1 = I915_READ(VGA1);
 381         dev_priv->saveVGA_PD = I915_READ(VGA_PD);
 382         dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
 383
 384         /* Clock gating state */
 385         dev_priv->saveD_STATE = I915_READ(D_STATE);
 386         dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS);
 387
 388         /* Cache mode state */
 389         dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 390
 391         /* Memory Arbitration state */
 392         dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
 393
 394         /* Scratch space */
 395         for (i = 0; i < 16; i++) {
 396                 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
 397                 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
 398         }
 399         for (i = 0; i < 3; i++)
 400                 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
 401
 402         i915_save_vga(dev);
 403
 404         if (state.event == PM_EVENT_SUSPEND) {
 405                 /* Shut down the device */
 406                 pci_disable_device(dev->pdev);
 407                 pci_set_power_state(dev->pdev, PCI_D3hot);
 408         }
 409
 410         return 0;
 411 }
 412
 413 static int i915_resume(struct drm_device *dev)
 414 {
 415         struct drm_i915_private *dev_priv = dev->dev_private;
 416         int i;
 417
 418         pci_set_power_state(dev->pdev, PCI_D0);
 419         pci_restore_state(dev->pdev);
 420         if (pci_enable_device(dev->pdev))
 421                 return -1;
 422
 423         DRM_INFO("resuming i915\n");
 424
 425         pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
 426
 427         I915_WRITE(DSPARB, dev_priv->saveDSPARB);
 428
 429         /* Pipe & plane A info */
 430         /* Prime the clock */
 431         if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
 432                 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
 433                            ~DPLL_VCO_ENABLE);
 434                 udelay(150);
 435         }
 436         I915_WRITE(FPA0, dev_priv->saveFPA0);
 437         I915_WRITE(FPA1, dev_priv->saveFPA1);
 438         /* Actually enable it */
 439         I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
 440         udelay(150);
 441         if (IS_I965G(dev))
 442                 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
 443         udelay(150);
 444
 445         /* Restore mode */
 446         I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
 447         I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
 448         I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
 449         I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
 450         I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
 451         I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
 452         I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
 453
 454         /* Restore plane info */
 455         I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
 456         I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
 457         I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
 458         I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
 459         I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
 460         if (IS_I965G(dev)) {
 461                 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
 462                 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
 463         }
 464
 465         I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
 466
 467         i915_restore_palette(dev, PIPE_A);
 468         /* Enable the plane */
 469         I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
 470         I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
 471
 472         /* Pipe & plane B info */
 473         if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
 474                 DRM_INFO("restoring DPLL_B: 0x%08x\n", dev_priv->saveDPLL_B);
 475                 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
 476                            ~DPLL_VCO_ENABLE);
 477                 udelay(150);
 478         }
 479         I915_WRITE(FPB0, dev_priv->saveFPB0);
 480         I915_WRITE(FPB1, dev_priv->saveFPB1);
 481         /* Actually enable it */
 482         I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
 483         DRM_INFO("restoring DPLL_B: 0x%08x\n", dev_priv->saveDPLL_B);
 484         udelay(150);
 485         if (IS_I965G(dev))
 486                 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
 487         udelay(150);
 488
 489         /* Restore mode */
 490         I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
 491         I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
 492         I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
 493         I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
 494         I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
 495         I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
 496         I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
 497
 498         /* Restore plane info */
 499         I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
 500         I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
 501         I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
 502         I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
 503         I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
 504         if (IS_I965G(dev)) {
 505                 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
 506                 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
 507         }
 508
 509         I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
 510
 511         i915_restore_palette(dev, PIPE_B);
 512         /* Enable the plane */
 513         I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
 514         I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
 515
 516         /* CRT state */
 517         I915_WRITE(ADPA, dev_priv->saveADPA);
 518
 519         /* LVDS state */
 520         if (IS_I965G(dev))
 521                 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
 522         if (IS_MOBILE(dev) && !IS_I830(dev))
 523                 I915_WRITE(LVDS, dev_priv->saveLVDS);
 524         if (!IS_I830(dev) && !IS_845G(dev))
 525                 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
 526
 527         I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
 528         I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
 529         I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
 530         I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
 531         I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
 532         I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
 533
 534         /* FIXME: restore TV & SDVO state */
 535
 536         /* FBC info */
 537         I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
 538         I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
 539         I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
 540         I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
 541
 542         /* VGA state */
 543         I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
 544         I915_WRITE(VGA0, dev_priv->saveVGA0);
 545         I915_WRITE(VGA1, dev_priv->saveVGA1);
 546         I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
 547         udelay(150);
 548
 549         /* Clock gating state */
 550         I915_WRITE (D_STATE, dev_priv->saveD_STATE);
 551         I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS);
 552
 553         /* Cache mode state */
 554         I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
 555
 556         /* Memory arbitration state */
 557         I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
 558
 559         for (i = 0; i < 16; i++) {
 560                 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
 561                 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
 562         }
 563         for (i = 0; i < 3; i++)
 564                 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
 565
 566         i915_restore_vga(dev);
 567
 568         return 0;
 569 }
 570
 571 static int probe(struct pci_dev *pdev, const struct pci_device_id *ent);
 572 static struct drm_driver driver = {
 573         /* don't use mtrr's here, the Xserver or user space app should
 574          * deal with them for intel hardware.
 575          */
 576         .driver_features =
 577             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR | */
 578             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED,
 579         .load = i915_driver_load,
 580         .unload = i915_driver_unload,
 581         .firstopen = i915_driver_firstopen,
 582         .lastclose = i915_driver_lastclose,
 583         .preclose = i915_driver_preclose,
 584         .suspend = i915_suspend,
 585         .resume = i915_resume,
 586         .device_is_agp = i915_driver_device_is_agp,
 587         .get_vblank_counter = i915_get_vblank_counter,
 588         .enable_vblank = i915_enable_vblank,
 589         .disable_vblank = i915_disable_vblank,
 590         .irq_preinstall = i915_driver_irq_preinstall,
 591         .irq_postinstall = i915_driver_irq_postinstall,
 592         .irq_uninstall = i915_driver_irq_uninstall,
 593         .irq_handler = i915_driver_irq_handler,
 594         .reclaim_buffers = drm_core_reclaim_buffers,
 595         .get_map_ofs = drm_core_get_map_ofs,
 596         .get_reg_ofs = drm_core_get_reg_ofs,
 597         .master_create = i915_master_create,
 598         .master_destroy = i915_master_destroy,
 599         .ioctls = i915_ioctls,
 600         .fops = {
 601                 .owner = THIS_MODULE,
 602                 .open = drm_open,
 603                 .release = drm_release,
 604                 .ioctl = drm_ioctl,
 605                 .mmap = drm_mmap,
 606                 .poll = drm_poll,
 607                 .fasync = drm_fasync,
 608 #if defined(CONFIG_COMPAT) && LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
 609                 .compat_ioctl = i915_compat_ioctl,
 610 #endif
 611                 },
 612         .pci_driver = {
 613                 .name = DRIVER_NAME,
 614                 .id_table = pciidlist,
 615                 .probe = probe,
 616                 .remove = __devexit_p(drm_cleanup_pci),
 617                 },
 618 #ifdef I915_HAVE_FENCE
 619         .fence_driver = &i915_fence_driver,
 620 #endif
 621 #ifdef I915_HAVE_BUFFER
 622         .bo_driver = &i915_bo_driver,
 623 #endif
 624         .name = DRIVER_NAME,
 625         .desc = DRIVER_DESC,
 626         .date = DRIVER_DATE,
 627         .major = DRIVER_MAJOR,
 628         .minor = DRIVER_MINOR,
 629         .patchlevel = DRIVER_PATCHLEVEL,
 630 };
 631
 632 static int probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 633 {
 634         return drm_get_dev(pdev, ent, &driver);
 635 }
 636
 637 static int __init i915_init(void)
 638 {
 639         driver.num_ioctls = i915_max_ioctl;
 640         if (i915_modeset == 1)
 641                 driver.driver_features |= DRIVER_MODESET;
 642
 643         return drm_init(&driver, pciidlist);
 644 }
 645
 646 static void __exit i915_exit(void)
 647 {
 648         drm_exit(&driver);
 649 }
 650
 651 module_init(i915_init);
 652 module_exit(i915_exit);
 653
 654 MODULE_AUTHOR(DRIVER_AUTHOR);
 655 MODULE_DESCRIPTION(DRIVER_DESC);
 656 MODULE_LICENSE("GPL and additional rights");