linux-core/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drm.h"
  33 #include "i915_drv.h"
  34
  35 #include "drm_pciids.h"
  36
  37 static struct pci_device_id pciidlist[] = {
  38         i915_PCI_IDS
  39 };
  40
  41 #ifdef I915_HAVE_FENCE
  42 static struct drm_fence_driver i915_fence_driver = {
  43         .num_classes = 1,
  44         .wrap_diff = (1U << (BREADCRUMB_BITS - 1)),
  45         .flush_diff = (1U << (BREADCRUMB_BITS - 2)),
  46         .sequence_mask = BREADCRUMB_MASK,
  47         .lazy_capable = 1,
  48         .emit = i915_fence_emit_sequence,
  49         .poke_flush = i915_poke_flush,
  50         .has_irq = i915_fence_has_irq,
  51 };
  52 #endif
  53 #ifdef I915_HAVE_BUFFER
  54
  55 static uint32_t i915_mem_prios[] = {DRM_BO_MEM_PRIV0, DRM_BO_MEM_TT, DRM_BO_MEM_LOCAL};
  56 static uint32_t i915_busy_prios[] = {DRM_BO_MEM_TT, DRM_BO_MEM_PRIV0, DRM_BO_MEM_LOCAL};
  57
  58 static struct drm_bo_driver i915_bo_driver = {
  59         .mem_type_prio = i915_mem_prios,
  60         .mem_busy_prio = i915_busy_prios,
  61         .num_mem_type_prio = sizeof(i915_mem_prios)/sizeof(uint32_t),
  62         .num_mem_busy_prio = sizeof(i915_busy_prios)/sizeof(uint32_t),
  63         .create_ttm_backend_entry = i915_create_ttm_backend_entry,
  64         .fence_type = i915_fence_types,
  65         .invalidate_caches = i915_invalidate_caches,
  66         .init_mem_type = i915_init_mem_type,
  67         .evict_mask = i915_evict_mask,
  68         .move = i915_move,
  69 };
  70 #endif
  71
  72 enum pipe {
  73     PIPE_A = 0,
  74     PIPE_B,
  75 };
  76
  77 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
  78 {
  79         struct drm_i915_private *dev_priv = dev->dev_private;
  80
  81         if (pipe == PIPE_A)
  82                 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
  83         else
  84                 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
  85 }
  86
  87 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
  88 {
  89         struct drm_i915_private *dev_priv = dev->dev_private;
  90         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
  91         u32 *array;
  92         int i;
  93
  94         if (!i915_pipe_enabled(dev, pipe))
  95                 return;
  96
  97         if (pipe == PIPE_A)
  98                 array = dev_priv->save_palette_a;
  99         else
 100                 array = dev_priv->save_palette_b;
 101
 102         for(i = 0; i < 256; i++)
 103                 array[i] = I915_READ(reg + (i << 2));
 104 }
 105
 106 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
 107 {
 108         struct drm_i915_private *dev_priv = dev->dev_private;
 109         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
 110         u32 *array;
 111         int i;
 112
 113         if (!i915_pipe_enabled(dev, pipe))
 114                 return;
 115
 116         if (pipe == PIPE_A)
 117                 array = dev_priv->save_palette_a;
 118         else
 119                 array = dev_priv->save_palette_b;
 120
 121         for(i = 0; i < 256; i++)
 122                 I915_WRITE(reg + (i << 2), array[i]);
 123 }
 124
 125 static u8 i915_read_indexed(u16 index_port, u16 data_port, u8 reg)
 126 {
 127         outb(reg, index_port);
 128         return inb(data_port);
 129 }
 130
 131 static u8 i915_read_ar(u16 st01, u8 reg, u16 palette_enable)
 132 {
 133         inb(st01);
 134         outb(palette_enable | reg, VGA_AR_INDEX);
 135         return inb(VGA_AR_DATA_READ);
 136 }
 137
 138 static void i915_write_ar(u8 st01, u8 reg, u8 val, u16 palette_enable)
 139 {
 140         inb(st01);
 141         outb(palette_enable | reg, VGA_AR_INDEX);
 142         outb(val, VGA_AR_DATA_WRITE);
 143 }
 144
 145 static void i915_write_indexed(u16 index_port, u16 data_port, u8 reg, u8 val)
 146 {
 147         outb(reg, index_port);
 148         outb(val, data_port);
 149 }
 150
 151 static void i915_save_vga(struct drm_device *dev)
 152 {
 153         struct drm_i915_private *dev_priv = dev->dev_private;
 154         int i;
 155         u16 cr_index, cr_data, st01;
 156
 157         /* VGA color palette registers */
 158         dev_priv->saveDACMASK = inb(VGA_DACMASK);
 159         /* DACCRX automatically increments during read */
 160         outb(0, VGA_DACRX);
 161         /* Read 3 bytes of color data from each index */
 162         for (i = 0; i < 256 * 3; i++)
 163                 dev_priv->saveDACDATA[i] = inb(VGA_DACDATA);
 164
 165         /* MSR bits */
 166         dev_priv->saveMSR = inb(VGA_MSR_READ);
 167         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 168                 cr_index = VGA_CR_INDEX_CGA;
 169                 cr_data = VGA_CR_DATA_CGA;
 170                 st01 = VGA_ST01_CGA;
 171         } else {
 172                 cr_index = VGA_CR_INDEX_MDA;
 173                 cr_data = VGA_CR_DATA_MDA;
 174                 st01 = VGA_ST01_MDA;
 175         }
 176
 177         /* CRT controller regs */
 178         i915_write_indexed(cr_index, cr_data, 0x11,
 179                            i915_read_indexed(cr_index, cr_data, 0x11) &
 180                            (~0x80));
 181         for (i = 0; i < 0x24; i++)
 182                 dev_priv->saveCR[i] =
 183                         i915_read_indexed(cr_index, cr_data, i);
 184         /* Make sure we don't turn off CR group 0 writes */
 185         dev_priv->saveCR[0x11] &= ~0x80;
 186
 187         /* Attribute controller registers */
 188         inb(st01);
 189         dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
 190         for (i = 0; i < 20; i++)
 191                 dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
 192         inb(st01);
 193         outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
 194
 195         /* Graphics controller registers */
 196         for (i = 0; i < 9; i++)
 197                 dev_priv->saveGR[i] =
 198                         i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, i);
 199
 200         dev_priv->saveGR[0x10] =
 201                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10);
 202         dev_priv->saveGR[0x11] =
 203                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11);
 204         dev_priv->saveGR[0x18] =
 205                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18);
 206
 207         /* Sequencer registers */
 208         for (i = 0; i < 8; i++)
 209                 dev_priv->saveSR[i] =
 210                         i915_read_indexed(VGA_SR_INDEX, VGA_SR_DATA, i);
 211 }
 212
 213 static void i915_restore_vga(struct drm_device *dev)
 214 {
 215         struct drm_i915_private *dev_priv = dev->dev_private;
 216         int i;
 217         u16 cr_index, cr_data, st01;
 218
 219         /* MSR bits */
 220         outb(dev_priv->saveMSR, VGA_MSR_WRITE);
 221         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 222                 cr_index = VGA_CR_INDEX_CGA;
 223                 cr_data = VGA_CR_DATA_CGA;
 224                 st01 = VGA_ST01_CGA;
 225         } else {
 226                 cr_index = VGA_CR_INDEX_MDA;
 227                 cr_data = VGA_CR_DATA_MDA;
 228                 st01 = VGA_ST01_MDA;
 229         }
 230
 231         /* Sequencer registers, don't write SR07 */
 232         for (i = 0; i < 7; i++)
 233                 i915_write_indexed(VGA_SR_INDEX, VGA_SR_DATA, i,
 234                                    dev_priv->saveSR[i]);
 235
 236         /* CRT controller regs */
 237         /* Enable CR group 0 writes */
 238         i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
 239         for (i = 0; i < 0x24; i++)
 240                 i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);
 241
 242         /* Graphics controller regs */
 243         for (i = 0; i < 9; i++)
 244                 i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, i,
 245                                    dev_priv->saveGR[i]);
 246
 247         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10,
 248                            dev_priv->saveGR[0x10]);
 249         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11,
 250                            dev_priv->saveGR[0x11]);
 251         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18,
 252                            dev_priv->saveGR[0x18]);
 253
 254         /* Attribute controller registers */
 255         for (i = 0; i < 20; i++)
 256                 i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
 257         inb(st01); /* switch back to index mode */
 258         outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX);
 259
 260         /* VGA color palette registers */
 261         outb(dev_priv->saveDACMASK, VGA_DACMASK);
 262         /* DACCRX automatically increments during read */
 263         outb(0, VGA_DACWX);
 264         /* Read 3 bytes of color data from each index */
 265         for (i = 0; i < 256 * 3; i++)
 266                 outb(dev_priv->saveDACDATA[i], VGA_DACDATA);
 267
 268 }
 269
 270 static int i915_suspend(struct drm_device *dev)
 271 {
 272         struct drm_i915_private *dev_priv = dev->dev_private;
 273         int i;
 274
 275         if (!dev || !dev_priv) {
 276                 printk(KERN_ERR "dev: %p, dev_priv: %p\n", dev, dev_priv);
 277                 printk(KERN_ERR "DRM not initialized, aborting suspend.\n");
 278                 return -ENODEV;
 279         }
 280
 281         pci_save_state(dev->pdev);
 282         pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
 283
 284         /* Pipe & plane A info */
 285         dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
 286         dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
 287         dev_priv->saveFPA0 = I915_READ(FPA0);
 288         dev_priv->saveFPA1 = I915_READ(FPA1);
 289         dev_priv->saveDPLL_A = I915_READ(DPLL_A);
 290         if (IS_I965G(dev))
 291                 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
 292         dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
 293         dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
 294         dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
 295         dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
 296         dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
 297         dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
 298         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
 299
 300         dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
 301         dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
 302         dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
 303         dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
 304         dev_priv->saveDSPABASE = I915_READ(DSPABASE);
 305         if (IS_I965G(dev)) {
 306                 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
 307                 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
 308         }
 309         i915_save_palette(dev, PIPE_A);
 310
 311         /* Pipe & plane B info */
 312         dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
 313         dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
 314         dev_priv->saveFPB0 = I915_READ(FPB0);
 315         dev_priv->saveFPB1 = I915_READ(FPB1);
 316         dev_priv->saveDPLL_B = I915_READ(DPLL_B);
 317         if (IS_I965G(dev))
 318                 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
 319         dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
 320         dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
 321         dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
 322         dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
 323         dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
 324         dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
 325         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
 326
 327         dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
 328         dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
 329         dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
 330         dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
 331         dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
 332         if (IS_I965GM(dev)) {
 333                 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
 334                 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
 335         }
 336         i915_save_palette(dev, PIPE_B);
 337
 338         /* CRT state */
 339         dev_priv->saveADPA = I915_READ(ADPA);
 340
 341         /* LVDS state */
 342         dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
 343         dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
 344         dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
 345         if (IS_I965G(dev))
 346                 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
 347         if (IS_MOBILE(dev) && !IS_I830(dev))
 348                 dev_priv->saveLVDS = I915_READ(LVDS);
 349         if (!IS_I830(dev) && !IS_845G(dev))
 350                 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
 351         dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON);
 352         dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF);
 353         dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);
 354
 355         /* FIXME: save TV & SDVO state */
 356
 357         /* FBC state */
 358         dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
 359         dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
 360         dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
 361         dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
 362
 363         /* VGA state */
 364         dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
 365         dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
 366         dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
 367         dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
 368
 369         /* Scratch space */
 370         for (i = 0; i < 16; i++) {
 371                 dev_priv->saveSWF0[i] = I915_READ(SWF0 + (i << 2));
 372                 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
 373         }
 374         for (i = 0; i < 3; i++)
 375                 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
 376
 377         i915_save_vga(dev);
 378
 379         /* Shut down the device */
 380         pci_disable_device(dev->pdev);
 381         pci_set_power_state(dev->pdev, PCI_D3hot);
 382
 383         return 0;
 384 }
 385
 386 static int i915_resume(struct drm_device *dev)
 387 {
 388         struct drm_i915_private *dev_priv = dev->dev_private;
 389         int i;
 390
 391         pci_set_power_state(dev->pdev, PCI_D0);
 392         pci_restore_state(dev->pdev);
 393         if (pci_enable_device(dev->pdev))
 394                 return -1;
 395
 396         pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
 397
 398         /* Pipe & plane A info */
 399         /* Prime the clock */
 400         if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
 401                 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
 402                            ~DPLL_VCO_ENABLE);
 403                 udelay(150);
 404         }
 405         I915_WRITE(FPA0, dev_priv->saveFPA0);
 406         I915_WRITE(FPA1, dev_priv->saveFPA1);
 407         /* Actually enable it */
 408         I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
 409         udelay(150);
 410         if (IS_I965G(dev))
 411                 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
 412         udelay(150);
 413
 414         /* Restore mode */
 415         I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
 416         I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
 417         I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
 418         I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
 419         I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
 420         I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
 421         I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
 422
 423         /* Restore plane info */
 424         I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
 425         I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
 426         I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
 427         I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
 428         I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
 429         if (IS_I965G(dev)) {
 430                 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
 431                 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
 432         }
 433         I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
 434         i915_restore_palette(dev, PIPE_A);
 435         /* Enable the plane */
 436         I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
 437         I915_WRITE(DSPABASE, I915_READ(DSPABASE));
 438
 439         /* Pipe & plane B info */
 440         if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
 441                 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
 442                            ~DPLL_VCO_ENABLE);
 443                 udelay(150);
 444         }
 445         I915_WRITE(FPB0, dev_priv->saveFPB0);
 446         I915_WRITE(FPB1, dev_priv->saveFPB1);
 447         /* Actually enable it */
 448         I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
 449         udelay(150);
 450         if (IS_I965G(dev))
 451                 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
 452         udelay(150);
 453
 454         /* Restore mode */
 455         I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
 456         I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
 457         I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
 458         I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
 459         I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
 460         I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
 461         I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
 462
 463         /* Restore plane info */
 464         I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
 465         I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
 466         I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
 467         I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
 468         I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
 469         if (IS_I965G(dev)) {
 470                 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
 471                 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
 472         }
 473         I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
 474         i915_restore_palette(dev, PIPE_A);
 475         /* Enable the plane */
 476         I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
 477         I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
 478
 479         /* CRT state */
 480         I915_WRITE(ADPA, dev_priv->saveADPA);
 481
 482         /* LVDS state */
 483         if (IS_I965G(dev))
 484                 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
 485         if (IS_MOBILE(dev) && !IS_I830(dev))
 486                 I915_WRITE(LVDS, dev_priv->saveLVDS);
 487         if (!IS_I830(dev) && !IS_845G(dev))
 488                 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
 489
 490         I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
 491         I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
 492         I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON);
 493         I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF);
 494         I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
 495         I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
 496
 497         /* FIXME: restore TV & SDVO state */
 498
 499         /* FBC info */
 500         I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
 501         I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
 502         I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
 503         I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
 504
 505         /* VGA state */
 506         I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
 507         I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
 508         I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
 509         I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
 510         udelay(150);
 511
 512         for (i = 0; i < 16; i++) {
 513                 I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF0[i]);
 514                 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
 515         }
 516         for (i = 0; i < 3; i++)
 517                 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
 518
 519         i915_restore_vga(dev);
 520
 521         return 0;
 522 }
 523
 524 static int probe(struct pci_dev *pdev, const struct pci_device_id *ent);
 525 static struct drm_driver driver = {
 526         /* don't use mtrr's here, the Xserver or user space app should
 527          * deal with them for intel hardware.
 528          */
 529         .driver_features =
 530             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR | */
 531             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL |
 532             DRIVER_IRQ_VBL2,
 533         .load = i915_driver_load,
 534         .unload = i915_driver_unload,
 535         .firstopen = i915_driver_firstopen,
 536         .lastclose = i915_driver_lastclose,
 537         .preclose = i915_driver_preclose,
 538         .suspend = i915_suspend,
 539         .resume = i915_resume,
 540         .device_is_agp = i915_driver_device_is_agp,
 541         .vblank_wait = i915_driver_vblank_wait,
 542         .vblank_wait2 = i915_driver_vblank_wait2,
 543         .irq_preinstall = i915_driver_irq_preinstall,
 544         .irq_postinstall = i915_driver_irq_postinstall,
 545         .irq_uninstall = i915_driver_irq_uninstall,
 546         .irq_handler = i915_driver_irq_handler,
 547         .reclaim_buffers = drm_core_reclaim_buffers,
 548         .get_map_ofs = drm_core_get_map_ofs,
 549         .get_reg_ofs = drm_core_get_reg_ofs,
 550         .ioctls = i915_ioctls,
 551         .fops = {
 552                 .owner = THIS_MODULE,
 553                 .open = drm_open,
 554                 .release = drm_release,
 555                 .ioctl = drm_ioctl,
 556                 .mmap = drm_mmap,
 557                 .poll = drm_poll,
 558                 .fasync = drm_fasync,
 559 #if defined(CONFIG_COMPAT) && LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
 560                 .compat_ioctl = i915_compat_ioctl,
 561 #endif
 562                 },
 563         .pci_driver = {
 564                 .name = DRIVER_NAME,
 565                 .id_table = pciidlist,
 566                 .probe = probe,
 567                 .remove = __devexit_p(drm_cleanup_pci),
 568                 },
 569 #ifdef I915_HAVE_FENCE
 570         .fence_driver = &i915_fence_driver,
 571 #endif
 572 #ifdef I915_HAVE_BUFFER
 573         .bo_driver = &i915_bo_driver,
 574 #endif
 575         .name = DRIVER_NAME,
 576         .desc = DRIVER_DESC,
 577         .date = DRIVER_DATE,
 578         .major = DRIVER_MAJOR,
 579         .minor = DRIVER_MINOR,
 580         .patchlevel = DRIVER_PATCHLEVEL,
 581 };
 582
 583 static int probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 584 {
 585         return drm_get_dev(pdev, ent, &driver);
 586 }
 587
 588 static int __init i915_init(void)
 589 {
 590         driver.num_ioctls = i915_max_ioctl;
 591         return drm_init(&driver, pciidlist);
 592 }
 593
 594 static void __exit i915_exit(void)
 595 {
 596         drm_exit(&driver);
 597 }
 598
 599 module_init(i915_init);
 600 module_exit(i915_exit);
 601
 602 MODULE_AUTHOR(DRIVER_AUTHOR);
 603 MODULE_DESCRIPTION(DRIVER_DESC);
 604 MODULE_LICENSE("GPL and additional rights");