linux-core/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drm.h"
  33 #include "i915_drv.h"
  34
  35 #include "drm_pciids.h"
  36
  37 static struct pci_device_id pciidlist[] = {
  38         i915_PCI_IDS
  39 };
  40
  41 #ifdef I915_HAVE_FENCE
  42 extern struct drm_fence_driver i915_fence_driver;
  43 #endif
  44
  45 #ifdef I915_HAVE_BUFFER
  46
  47 static uint32_t i915_mem_prios[] = {DRM_BO_MEM_PRIV0, DRM_BO_MEM_TT, DRM_BO_MEM_LOCAL};
  48 static uint32_t i915_busy_prios[] = {DRM_BO_MEM_TT, DRM_BO_MEM_PRIV0, DRM_BO_MEM_LOCAL};
  49
  50 static struct drm_bo_driver i915_bo_driver = {
  51         .mem_type_prio = i915_mem_prios,
  52         .mem_busy_prio = i915_busy_prios,
  53         .num_mem_type_prio = sizeof(i915_mem_prios)/sizeof(uint32_t),
  54         .num_mem_busy_prio = sizeof(i915_busy_prios)/sizeof(uint32_t),
  55         .create_ttm_backend_entry = i915_create_ttm_backend_entry,
  56         .fence_type = i915_fence_type,
  57         .invalidate_caches = i915_invalidate_caches,
  58         .init_mem_type = i915_init_mem_type,
  59         .evict_flags = i915_evict_flags,
  60         .move = i915_move,
  61         .ttm_cache_flush = i915_flush_ttm,
  62         .command_stream_barrier = NULL,
  63 };
  64 #endif
  65
  66 enum pipe {
  67     PIPE_A = 0,
  68     PIPE_B,
  69 };
  70
  71 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
  72 {
  73         struct drm_i915_private *dev_priv = dev->dev_private;
  74
  75         if (pipe == PIPE_A)
  76                 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
  77         else
  78                 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
  79 }
  80
  81 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
  82 {
  83         struct drm_i915_private *dev_priv = dev->dev_private;
  84         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
  85         u32 *array;
  86         int i;
  87
  88         if (!i915_pipe_enabled(dev, pipe))
  89                 return;
  90
  91         if (pipe == PIPE_A)
  92                 array = dev_priv->save_palette_a;
  93         else
  94                 array = dev_priv->save_palette_b;
  95
  96         for(i = 0; i < 256; i++)
  97                 array[i] = I915_READ(reg + (i << 2));
  98 }
  99
 100 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
 101 {
 102         struct drm_i915_private *dev_priv = dev->dev_private;
 103         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
 104         u32 *array;
 105         int i;
 106
 107         if (!i915_pipe_enabled(dev, pipe))
 108                 return;
 109
 110         if (pipe == PIPE_A)
 111                 array = dev_priv->save_palette_a;
 112         else
 113                 array = dev_priv->save_palette_b;
 114
 115         for(i = 0; i < 256; i++)
 116                 I915_WRITE(reg + (i << 2), array[i]);
 117 }
 118
 119 static u8 i915_read_indexed(u16 index_port, u16 data_port, u8 reg)
 120 {
 121         outb(reg, index_port);
 122         return inb(data_port);
 123 }
 124
 125 static u8 i915_read_ar(u16 st01, u8 reg, u16 palette_enable)
 126 {
 127         inb(st01);
 128         outb(palette_enable | reg, VGA_AR_INDEX);
 129         return inb(VGA_AR_DATA_READ);
 130 }
 131
 132 static void i915_write_ar(u8 st01, u8 reg, u8 val, u16 palette_enable)
 133 {
 134         inb(st01);
 135         outb(palette_enable | reg, VGA_AR_INDEX);
 136         outb(val, VGA_AR_DATA_WRITE);
 137 }
 138
 139 static void i915_write_indexed(u16 index_port, u16 data_port, u8 reg, u8 val)
 140 {
 141         outb(reg, index_port);
 142         outb(val, data_port);
 143 }
 144
 145 static void i915_save_vga(struct drm_device *dev)
 146 {
 147         struct drm_i915_private *dev_priv = dev->dev_private;
 148         int i;
 149         u16 cr_index, cr_data, st01;
 150
 151         /* VGA color palette registers */
 152         dev_priv->saveDACMASK = inb(VGA_DACMASK);
 153         /* DACCRX automatically increments during read */
 154         outb(0, VGA_DACRX);
 155         /* Read 3 bytes of color data from each index */
 156         for (i = 0; i < 256 * 3; i++)
 157                 dev_priv->saveDACDATA[i] = inb(VGA_DACDATA);
 158
 159         /* MSR bits */
 160         dev_priv->saveMSR = inb(VGA_MSR_READ);
 161         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 162                 cr_index = VGA_CR_INDEX_CGA;
 163                 cr_data = VGA_CR_DATA_CGA;
 164                 st01 = VGA_ST01_CGA;
 165         } else {
 166                 cr_index = VGA_CR_INDEX_MDA;
 167                 cr_data = VGA_CR_DATA_MDA;
 168                 st01 = VGA_ST01_MDA;
 169         }
 170
 171         /* CRT controller regs */
 172         i915_write_indexed(cr_index, cr_data, 0x11,
 173                            i915_read_indexed(cr_index, cr_data, 0x11) &
 174                            (~0x80));
 175         for (i = 0; i <= 0x24; i++)
 176                 dev_priv->saveCR[i] =
 177                         i915_read_indexed(cr_index, cr_data, i);
 178         /* Make sure we don't turn off CR group 0 writes */
 179         dev_priv->saveCR[0x11] &= ~0x80;
 180
 181         /* Attribute controller registers */
 182         inb(st01);
 183         dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
 184         for (i = 0; i <= 0x14; i++)
 185                 dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
 186         inb(st01);
 187         outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
 188         inb(st01);
 189
 190         /* Graphics controller registers */
 191         for (i = 0; i < 9; i++)
 192                 dev_priv->saveGR[i] =
 193                         i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, i);
 194
 195         dev_priv->saveGR[0x10] =
 196                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10);
 197         dev_priv->saveGR[0x11] =
 198                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11);
 199         dev_priv->saveGR[0x18] =
 200                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18);
 201
 202         /* Sequencer registers */
 203         for (i = 0; i < 8; i++)
 204                 dev_priv->saveSR[i] =
 205                         i915_read_indexed(VGA_SR_INDEX, VGA_SR_DATA, i);
 206 }
 207
 208 static void i915_restore_vga(struct drm_device *dev)
 209 {
 210         struct drm_i915_private *dev_priv = dev->dev_private;
 211         int i;
 212         u16 cr_index, cr_data, st01;
 213
 214         /* MSR bits */
 215         outb(dev_priv->saveMSR, VGA_MSR_WRITE);
 216         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 217                 cr_index = VGA_CR_INDEX_CGA;
 218                 cr_data = VGA_CR_DATA_CGA;
 219                 st01 = VGA_ST01_CGA;
 220         } else {
 221                 cr_index = VGA_CR_INDEX_MDA;
 222                 cr_data = VGA_CR_DATA_MDA;
 223                 st01 = VGA_ST01_MDA;
 224         }
 225
 226         /* Sequencer registers, don't write SR07 */
 227         for (i = 0; i < 7; i++)
 228                 i915_write_indexed(VGA_SR_INDEX, VGA_SR_DATA, i,
 229                                    dev_priv->saveSR[i]);
 230
 231         /* CRT controller regs */
 232         /* Enable CR group 0 writes */
 233         i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
 234         for (i = 0; i <= 0x24; i++)
 235                 i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);
 236
 237         /* Graphics controller regs */
 238         for (i = 0; i < 9; i++)
 239                 i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, i,
 240                                    dev_priv->saveGR[i]);
 241
 242         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10,
 243                            dev_priv->saveGR[0x10]);
 244         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11,
 245                            dev_priv->saveGR[0x11]);
 246         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18,
 247                            dev_priv->saveGR[0x18]);
 248
 249         /* Attribute controller registers */
 250         inb(st01); /* switch back to index mode */
 251         for (i = 0; i <= 0x14; i++)
 252                 i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
 253         inb(st01); /* switch back to index mode */
 254         outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX);
 255         inb(st01);
 256
 257         /* VGA color palette registers */
 258         outb(dev_priv->saveDACMASK, VGA_DACMASK);
 259         /* DACCRX automatically increments during read */
 260         outb(0, VGA_DACWX);
 261         /* Read 3 bytes of color data from each index */
 262         for (i = 0; i < 256 * 3; i++)
 263                 outb(dev_priv->saveDACDATA[i], VGA_DACDATA);
 264
 265 }
 266
 267 static int i915_suspend(struct drm_device *dev, pm_message_t state)
 268 {
 269         struct drm_i915_private *dev_priv = dev->dev_private;
 270         int i;
 271
 272         if (!dev || !dev_priv) {
 273                 printk(KERN_ERR "dev: %p, dev_priv: %p\n", dev, dev_priv);
 274                 printk(KERN_ERR "DRM not initialized, aborting suspend.\n");
 275                 return -ENODEV;
 276         }
 277
 278         if (state.event == PM_EVENT_PRETHAW)
 279                 return 0;
 280
 281         pci_save_state(dev->pdev);
 282         pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
 283
 284         /* Display arbitration control */
 285         dev_priv->saveDSPARB = I915_READ(DSPARB);
 286
 287         /* Pipe & plane A info */
 288         dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
 289         dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
 290         dev_priv->saveFPA0 = I915_READ(FPA0);
 291         dev_priv->saveFPA1 = I915_READ(FPA1);
 292         dev_priv->saveDPLL_A = I915_READ(DPLL_A);
 293         if (IS_I965G(dev))
 294                 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
 295         dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
 296         dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
 297         dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
 298         dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
 299         dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
 300         dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
 301         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
 302
 303         dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
 304         dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
 305         dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
 306         dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
 307         dev_priv->saveDSPABASE = I915_READ(DSPABASE);
 308         if (IS_I965G(dev)) {
 309                 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
 310                 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
 311         }
 312         i915_save_palette(dev, PIPE_A);
 313         dev_priv->savePIPEASTAT = I915_READ(I915REG_PIPEASTAT);
 314
 315         /* Pipe & plane B info */
 316         dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
 317         dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
 318         dev_priv->saveFPB0 = I915_READ(FPB0);
 319         dev_priv->saveFPB1 = I915_READ(FPB1);
 320         dev_priv->saveDPLL_B = I915_READ(DPLL_B);
 321         if (IS_I965G(dev))
 322                 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
 323         dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
 324         dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
 325         dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
 326         dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
 327         dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
 328         dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
 329         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
 330
 331         dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
 332         dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
 333         dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
 334         dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
 335         dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
 336         if (IS_I965GM(dev) || IS_IGD_GM(dev)) {
 337                 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
 338                 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
 339         }
 340         i915_save_palette(dev, PIPE_B);
 341         dev_priv->savePIPEBSTAT = I915_READ(I915REG_PIPEBSTAT);
 342
 343         /* CRT state */
 344         dev_priv->saveADPA = I915_READ(ADPA);
 345
 346         /* LVDS state */
 347         dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
 348         dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
 349         dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
 350         if (IS_I965G(dev))
 351                 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
 352         if (IS_MOBILE(dev) && !IS_I830(dev))
 353                 dev_priv->saveLVDS = I915_READ(LVDS);
 354         if (!IS_I830(dev) && !IS_845G(dev))
 355                 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
 356         dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON);
 357         dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF);
 358         dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);
 359
 360         /* FIXME: save TV & SDVO state */
 361
 362         /* FBC state */
 363         dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
 364         dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
 365         dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
 366         dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
 367
 368         /* Interrupt state */
 369         dev_priv->saveIIR = I915_READ(I915REG_INT_IDENTITY_R);
 370         dev_priv->saveIER = I915_READ(I915REG_INT_ENABLE_R);
 371         dev_priv->saveIMR = I915_READ(I915REG_INT_MASK_R);
 372
 373         /* VGA state */
 374         dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
 375         dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
 376         dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
 377         dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
 378
 379         /* Clock gating state */
 380         dev_priv->saveD_STATE = I915_READ(D_STATE);
 381         dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
 382
 383         /* Cache mode state */
 384         dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 385
 386         /* Memory Arbitration state */
 387         dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
 388
 389         /* Scratch space */
 390         for (i = 0; i < 16; i++) {
 391                 dev_priv->saveSWF0[i] = I915_READ(SWF0 + (i << 2));
 392                 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
 393         }
 394         for (i = 0; i < 3; i++)
 395                 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
 396
 397         i915_save_vga(dev);
 398
 399         if (state.event == PM_EVENT_SUSPEND) {
 400                 /* Shut down the device */
 401                 pci_disable_device(dev->pdev);
 402                 pci_set_power_state(dev->pdev, PCI_D3hot);
 403         }
 404
 405         return 0;
 406 }
 407
 408 static int i915_resume(struct drm_device *dev)
 409 {
 410         struct drm_i915_private *dev_priv = dev->dev_private;
 411         int i;
 412
 413         pci_set_power_state(dev->pdev, PCI_D0);
 414         pci_restore_state(dev->pdev);
 415         if (pci_enable_device(dev->pdev))
 416                 return -1;
 417
 418         pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
 419
 420         I915_WRITE(DSPARB, dev_priv->saveDSPARB);
 421
 422         /* Pipe & plane A info */
 423         /* Prime the clock */
 424         if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
 425                 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
 426                            ~DPLL_VCO_ENABLE);
 427                 udelay(150);
 428         }
 429         I915_WRITE(FPA0, dev_priv->saveFPA0);
 430         I915_WRITE(FPA1, dev_priv->saveFPA1);
 431         /* Actually enable it */
 432         I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
 433         udelay(150);
 434         if (IS_I965G(dev))
 435                 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
 436         udelay(150);
 437
 438         /* Restore mode */
 439         I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
 440         I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
 441         I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
 442         I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
 443         I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
 444         I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
 445         I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
 446
 447         /* Restore plane info */
 448         I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
 449         I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
 450         I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
 451         I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
 452         I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
 453         if (IS_I965G(dev)) {
 454                 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
 455                 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
 456         }
 457
 458         I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
 459
 460         i915_restore_palette(dev, PIPE_A);
 461         /* Enable the plane */
 462         I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
 463         I915_WRITE(DSPABASE, I915_READ(DSPABASE));
 464
 465         /* Pipe & plane B info */
 466         if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
 467                 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
 468                            ~DPLL_VCO_ENABLE);
 469                 udelay(150);
 470         }
 471         I915_WRITE(FPB0, dev_priv->saveFPB0);
 472         I915_WRITE(FPB1, dev_priv->saveFPB1);
 473         /* Actually enable it */
 474         I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
 475         udelay(150);
 476         if (IS_I965G(dev))
 477                 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
 478         udelay(150);
 479
 480         /* Restore mode */
 481         I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
 482         I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
 483         I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
 484         I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
 485         I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
 486         I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
 487         I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
 488
 489         /* Restore plane info */
 490         I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
 491         I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
 492         I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
 493         I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
 494         I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
 495         if (IS_I965G(dev)) {
 496                 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
 497                 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
 498         }
 499
 500         I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
 501
 502         i915_restore_palette(dev, PIPE_B);
 503         /* Enable the plane */
 504         I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
 505         I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
 506
 507         /* CRT state */
 508         I915_WRITE(ADPA, dev_priv->saveADPA);
 509
 510         /* LVDS state */
 511         if (IS_I965G(dev))
 512                 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
 513         if (IS_MOBILE(dev) && !IS_I830(dev))
 514                 I915_WRITE(LVDS, dev_priv->saveLVDS);
 515         if (!IS_I830(dev) && !IS_845G(dev))
 516                 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
 517
 518         I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
 519         I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
 520         I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON);
 521         I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF);
 522         I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
 523         I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
 524
 525         /* FIXME: restore TV & SDVO state */
 526
 527         /* FBC info */
 528         I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
 529         I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
 530         I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
 531         I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
 532
 533         /* VGA state */
 534         I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
 535         I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
 536         I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
 537         I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
 538         udelay(150);
 539
 540         /* Clock gating state */
 541         I915_WRITE (D_STATE, dev_priv->saveD_STATE);
 542         I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
 543
 544         /* Cache mode state */
 545         I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
 546
 547         /* Memory arbitration state */
 548         I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
 549
 550         for (i = 0; i < 16; i++) {
 551                 I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF0[i]);
 552                 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
 553         }
 554         for (i = 0; i < 3; i++)
 555                 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
 556
 557         i915_restore_vga(dev);
 558
 559         return 0;
 560 }
 561
 562 static int probe(struct pci_dev *pdev, const struct pci_device_id *ent);
 563 static void remove(struct pci_dev *pdev);
 564
 565 static struct drm_driver driver = {
 566         /* don't use mtrr's here, the Xserver or user space app should
 567          * deal with them for intel hardware.
 568          */
 569         .driver_features =
 570             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR | */
 571             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 572         .load = i915_driver_load,
 573         .unload = i915_driver_unload,
 574         .firstopen = i915_driver_firstopen,
 575         .open = i915_driver_open,
 576         .lastclose = i915_driver_lastclose,
 577         .preclose = i915_driver_preclose,
 578         .postclose = i915_driver_postclose,
 579         .suspend = i915_suspend,
 580         .resume = i915_resume,
 581         .device_is_agp = i915_driver_device_is_agp,
 582         .get_vblank_counter = i915_get_vblank_counter,
 583         .enable_vblank = i915_enable_vblank,
 584         .disable_vblank = i915_disable_vblank,
 585         .irq_preinstall = i915_driver_irq_preinstall,
 586         .irq_postinstall = i915_driver_irq_postinstall,
 587         .irq_uninstall = i915_driver_irq_uninstall,
 588         .irq_handler = i915_driver_irq_handler,
 589         .reclaim_buffers = drm_core_reclaim_buffers,
 590         .get_map_ofs = drm_core_get_map_ofs,
 591         .get_reg_ofs = drm_core_get_reg_ofs,
 592         .ioctls = i915_ioctls,
 593         .gem_init_object = i915_gem_init_object,
 594         .gem_free_object = i915_gem_free_object,
 595         .fops = {
 596                 .owner = THIS_MODULE,
 597                 .open = drm_open,
 598                 .release = drm_release,
 599                 .ioctl = drm_ioctl,
 600                 .mmap = drm_mmap,
 601                 .poll = drm_poll,
 602                 .fasync = drm_fasync,
 603 #if defined(CONFIG_COMPAT) && LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
 604                 .compat_ioctl = i915_compat_ioctl,
 605 #endif
 606                 },
 607         .pci_driver = {
 608                 .name = DRIVER_NAME,
 609                 .id_table = pciidlist,
 610                 .probe = probe,
 611                 .remove = remove,
 612                 },
 613 #ifdef I915_HAVE_FENCE
 614         .fence_driver = &i915_fence_driver,
 615 #endif
 616 #ifdef I915_HAVE_BUFFER
 617         .bo_driver = &i915_bo_driver,
 618 #endif
 619         .name = DRIVER_NAME,
 620         .desc = DRIVER_DESC,
 621         .date = DRIVER_DATE,
 622         .major = DRIVER_MAJOR,
 623         .minor = DRIVER_MINOR,
 624         .patchlevel = DRIVER_PATCHLEVEL,
 625 };
 626
 627 static int probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 628 {
 629         int ret;
 630
 631         /* On the 945G/GM, the chipset reports the MSI capability on the
 632          * integrated graphics even though the support isn't actually there
 633          * according to the published specs.  It doesn't appear to function
 634          * correctly in testing on 945G.
 635          * This may be a side effect of MSI having been made available for PEG
 636          * and the registers being closely associated.
 637          */
 638         if (pdev->device != 0x2772 && pdev->device != 0x27A2)
 639                 (void )pci_enable_msi(pdev);
 640
 641         ret = drm_get_dev(pdev, ent, &driver);
 642         if (ret && pdev->msi_enabled)
 643                 pci_disable_msi(pdev);
 644         return ret;
 645 }
 646 static void remove(struct pci_dev *pdev)
 647 {
 648         if (pdev->msi_enabled)
 649                 pci_disable_msi(pdev);
 650         drm_cleanup_pci(pdev);
 651 }
 652
 653 static int __init i915_init(void)
 654 {
 655         driver.num_ioctls = i915_max_ioctl;
 656         return drm_init(&driver, pciidlist);
 657 }
 658
 659 static void __exit i915_exit(void)
 660 {
 661         drm_exit(&driver);
 662 }
 663
 664 module_init(i915_init);
 665 module_exit(i915_exit);
 666
 667 MODULE_AUTHOR(DRIVER_AUTHOR);
 668 MODULE_DESCRIPTION(DRIVER_DESC);
 669 MODULE_LICENSE("GPL and additional rights");