linux-core/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drm.h"
  33 #include "intel_drv.h"
  34 #include "i915_drv.h"
  35
  36 #include "drm_pciids.h"
  37
  38 static struct pci_device_id pciidlist[] = {
  39         i915_PCI_IDS
  40 };
  41
  42 unsigned int i915_modeset = 0;
  43 module_param_named(modeset, i915_modeset, int, 0400);
  44
  45 #ifdef I915_HAVE_FENCE
  46 extern struct drm_fence_driver i915_fence_driver;
  47 #endif
  48
  49 #ifdef I915_HAVE_BUFFER
  50
  51 static uint32_t i915_mem_prios[] = {DRM_BO_MEM_VRAM, DRM_BO_MEM_PRIV0, DRM_BO_MEM_TT, DRM_BO_MEM_LOCAL};
  52 static uint32_t i915_busy_prios[] = {DRM_BO_MEM_TT, DRM_BO_MEM_PRIV0, DRM_BO_MEM_VRAM, DRM_BO_MEM_LOCAL};
  53
  54 static struct drm_bo_driver i915_bo_driver = {
  55         .mem_type_prio = i915_mem_prios,
  56         .mem_busy_prio = i915_busy_prios,
  57         .num_mem_type_prio = sizeof(i915_mem_prios)/sizeof(uint32_t),
  58         .num_mem_busy_prio = sizeof(i915_busy_prios)/sizeof(uint32_t),
  59         .create_ttm_backend_entry = i915_create_ttm_backend_entry,
  60         .fence_type = i915_fence_type,
  61         .invalidate_caches = i915_invalidate_caches,
  62         .init_mem_type = i915_init_mem_type,
  63         .evict_flags = i915_evict_flags,
  64         .move = i915_move,
  65         .ttm_cache_flush = i915_flush_ttm,
  66         .command_stream_barrier = NULL,
  67 };
  68 #endif
  69
  70 enum pipe {
  71     PIPE_A = 0,
  72     PIPE_B,
  73 };
  74
  75 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
  76 {
  77         struct drm_i915_private *dev_priv = dev->dev_private;
  78
  79         if (pipe == PIPE_A)
  80                 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
  81         else
  82                 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
  83 }
  84
  85 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
  86 {
  87         struct drm_i915_private *dev_priv = dev->dev_private;
  88         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
  89         u32 *array;
  90         int i;
  91
  92         if (!i915_pipe_enabled(dev, pipe))
  93                 return;
  94
  95         if (pipe == PIPE_A)
  96                 array = dev_priv->save_palette_a;
  97         else
  98                 array = dev_priv->save_palette_b;
  99
 100         for(i = 0; i < 256; i++)
 101                 array[i] = I915_READ(reg + (i << 2));
 102 }
 103
 104 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
 105 {
 106         struct drm_i915_private *dev_priv = dev->dev_private;
 107         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
 108         u32 *array;
 109         int i;
 110
 111         if (!i915_pipe_enabled(dev, pipe))
 112                 return;
 113
 114         if (pipe == PIPE_A)
 115                 array = dev_priv->save_palette_a;
 116         else
 117                 array = dev_priv->save_palette_b;
 118
 119         for(i = 0; i < 256; i++)
 120                 I915_WRITE(reg + (i << 2), array[i]);
 121 }
 122
 123 static u8 i915_read_indexed(u16 index_port, u16 data_port, u8 reg)
 124 {
 125         outb(reg, index_port);
 126         return inb(data_port);
 127 }
 128
 129 static u8 i915_read_ar(u16 st01, u8 reg, u16 palette_enable)
 130 {
 131         inb(st01);
 132         outb(palette_enable | reg, VGA_AR_INDEX);
 133         return inb(VGA_AR_DATA_READ);
 134 }
 135
 136 static void i915_write_ar(u8 st01, u8 reg, u8 val, u16 palette_enable)
 137 {
 138         inb(st01);
 139         outb(palette_enable | reg, VGA_AR_INDEX);
 140         outb(val, VGA_AR_DATA_WRITE);
 141 }
 142
 143 static void i915_write_indexed(u16 index_port, u16 data_port, u8 reg, u8 val)
 144 {
 145         outb(reg, index_port);
 146         outb(val, data_port);
 147 }
 148
 149 static void i915_save_vga(struct drm_device *dev)
 150 {
 151         struct drm_i915_private *dev_priv = dev->dev_private;
 152         int i;
 153         u16 cr_index, cr_data, st01;
 154
 155         /* VGA color palette registers */
 156         dev_priv->saveDACMASK = inb(VGA_DACMASK);
 157         /* DACCRX automatically increments during read */
 158         outb(0, VGA_DACRX);
 159         /* Read 3 bytes of color data from each index */
 160         for (i = 0; i < 256 * 3; i++)
 161                 dev_priv->saveDACDATA[i] = inb(VGA_DACDATA);
 162
 163         /* MSR bits */
 164         dev_priv->saveMSR = inb(VGA_MSR_READ);
 165         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 166                 cr_index = VGA_CR_INDEX_CGA;
 167                 cr_data = VGA_CR_DATA_CGA;
 168                 st01 = VGA_ST01_CGA;
 169         } else {
 170                 cr_index = VGA_CR_INDEX_MDA;
 171                 cr_data = VGA_CR_DATA_MDA;
 172                 st01 = VGA_ST01_MDA;
 173         }
 174
 175         /* CRT controller regs */
 176         i915_write_indexed(cr_index, cr_data, 0x11,
 177                            i915_read_indexed(cr_index, cr_data, 0x11) &
 178                            (~0x80));
 179         for (i = 0; i < 0x24; i++)
 180                 dev_priv->saveCR[i] =
 181                         i915_read_indexed(cr_index, cr_data, i);
 182         /* Make sure we don't turn off CR group 0 writes */
 183         dev_priv->saveCR[0x11] &= ~0x80;
 184
 185         /* Attribute controller registers */
 186         inb(st01);
 187         dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
 188         for (i = 0; i < 20; i++)
 189                 dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
 190         inb(st01);
 191         outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
 192         inb(st01);
 193
 194         /* Graphics controller registers */
 195         for (i = 0; i < 9; i++)
 196                 dev_priv->saveGR[i] =
 197                         i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, i);
 198
 199         dev_priv->saveGR[0x10] =
 200                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10);
 201         dev_priv->saveGR[0x11] =
 202                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11);
 203         dev_priv->saveGR[0x18] =
 204                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18);
 205
 206         /* Sequencer registers */
 207         for (i = 0; i < 8; i++)
 208                 dev_priv->saveSR[i] =
 209                         i915_read_indexed(VGA_SR_INDEX, VGA_SR_DATA, i);
 210 }
 211
 212 static void i915_restore_vga(struct drm_device *dev)
 213 {
 214         struct drm_i915_private *dev_priv = dev->dev_private;
 215         int i;
 216         u16 cr_index, cr_data, st01;
 217
 218         /* MSR bits */
 219         outb(dev_priv->saveMSR, VGA_MSR_WRITE);
 220         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 221                 cr_index = VGA_CR_INDEX_CGA;
 222                 cr_data = VGA_CR_DATA_CGA;
 223                 st01 = VGA_ST01_CGA;
 224         } else {
 225                 cr_index = VGA_CR_INDEX_MDA;
 226                 cr_data = VGA_CR_DATA_MDA;
 227                 st01 = VGA_ST01_MDA;
 228         }
 229
 230         /* Sequencer registers, don't write SR07 */
 231         for (i = 0; i < 7; i++)
 232                 i915_write_indexed(VGA_SR_INDEX, VGA_SR_DATA, i,
 233                                    dev_priv->saveSR[i]);
 234
 235         /* CRT controller regs */
 236         /* Enable CR group 0 writes */
 237         i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
 238         for (i = 0; i < 0x24; i++)
 239                 i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);
 240
 241         /* Graphics controller regs */
 242         for (i = 0; i < 9; i++)
 243                 i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, i,
 244                                    dev_priv->saveGR[i]);
 245
 246         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10,
 247                            dev_priv->saveGR[0x10]);
 248         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11,
 249                            dev_priv->saveGR[0x11]);
 250         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18,
 251                            dev_priv->saveGR[0x18]);
 252
 253         /* Attribute controller registers */
 254         inb(st01); /* switch back to index mode */
 255         for (i = 0; i < 20; i++)
 256                 i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
 257         inb(st01); /* switch back to index mode */
 258         outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX);
 259         inb(st01);
 260
 261         /* VGA color palette registers */
 262         outb(dev_priv->saveDACMASK, VGA_DACMASK);
 263         /* DACCRX automatically increments during read */
 264         outb(0, VGA_DACWX);
 265         /* Read 3 bytes of color data from each index */
 266         for (i = 0; i < 256 * 3; i++)
 267                 outb(dev_priv->saveDACDATA[i], VGA_DACDATA);
 268
 269 }
 270
 271 static int i915_suspend(struct drm_device *dev, pm_message_t state)
 272 {
 273         struct drm_i915_private *dev_priv = dev->dev_private;
 274         int i;
 275
 276         if (!dev || !dev_priv) {
 277                 printk(KERN_ERR "dev: %p, dev_priv: %p\n", dev, dev_priv);
 278                 printk(KERN_ERR "DRM not initialized, aborting suspend.\n");
 279                 return -ENODEV;
 280         }
 281
 282         if (state.event == PM_EVENT_PRETHAW)
 283                 return 0;
 284
 285         pci_save_state(dev->pdev);
 286         pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
 287
 288         /* Pipe & plane A info */
 289         dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
 290         dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
 291         dev_priv->saveFPA0 = I915_READ(FPA0);
 292         dev_priv->saveFPA1 = I915_READ(FPA1);
 293         dev_priv->saveDPLL_A = I915_READ(DPLL_A);
 294         if (IS_I965G(dev))
 295                 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
 296         dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
 297         dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
 298         dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
 299         dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
 300         dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
 301         dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
 302         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
 303
 304         dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
 305         dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
 306         dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
 307         dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
 308         dev_priv->saveDSPABASE = I915_READ(DSPABASE);
 309         if (IS_I965G(dev)) {
 310                 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
 311                 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
 312         }
 313         i915_save_palette(dev, PIPE_A);
 314         dev_priv->savePIPEASTAT = I915_READ(I915REG_PIPEASTAT);
 315
 316         /* Pipe & plane B info */
 317         dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
 318         dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
 319         dev_priv->saveFPB0 = I915_READ(FPB0);
 320         dev_priv->saveFPB1 = I915_READ(FPB1);
 321         dev_priv->saveDPLL_B = I915_READ(DPLL_B);
 322         if (IS_I965G(dev))
 323                 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
 324         dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
 325         dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
 326         dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
 327         dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
 328         dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
 329         dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
 330         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
 331
 332         dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
 333         dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
 334         dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
 335         dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
 336         dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
 337         if (IS_I965GM(dev) || IS_IGD_GM(dev)) {
 338                 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
 339                 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
 340         }
 341         i915_save_palette(dev, PIPE_B);
 342         dev_priv->savePIPEBSTAT = I915_READ(I915REG_PIPEBSTAT);
 343
 344         /* CRT state */
 345         dev_priv->saveADPA = I915_READ(ADPA);
 346
 347         /* LVDS state */
 348         dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
 349         dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
 350         dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
 351         if (IS_I965G(dev))
 352                 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
 353         if (IS_MOBILE(dev) && !IS_I830(dev))
 354                 dev_priv->saveLVDS = I915_READ(LVDS);
 355         if (!IS_I830(dev) && !IS_845G(dev))
 356                 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
 357         dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON);
 358         dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF);
 359         dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);
 360
 361         /* FIXME: save TV & SDVO state */
 362
 363         /* FBC state */
 364         dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
 365         dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
 366         dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
 367         dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
 368
 369         /* Interrupt state */
 370         dev_priv->saveIIR = I915_READ(I915REG_INT_IDENTITY_R);
 371         dev_priv->saveIER = I915_READ(I915REG_INT_ENABLE_R);
 372         dev_priv->saveIMR = I915_READ(I915REG_INT_MASK_R);
 373
 374         /* VGA state */
 375         dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
 376         dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
 377         dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
 378         dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
 379
 380         /* Clock gating state */
 381         dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
 382
 383         /* Cache mode state */
 384         dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 385
 386         /* Memory Arbitration state */
 387         dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
 388
 389         /* Scratch space */
 390         for (i = 0; i < 16; i++) {
 391                 dev_priv->saveSWF0[i] = I915_READ(SWF0 + (i << 2));
 392                 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
 393         }
 394         for (i = 0; i < 3; i++)
 395                 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
 396
 397         i915_save_vga(dev);
 398
 399         if (state.event == PM_EVENT_SUSPEND) {
 400                 /* Shut down the device */
 401                 pci_disable_device(dev->pdev);
 402                 pci_set_power_state(dev->pdev, PCI_D3hot);
 403         }
 404
 405         return 0;
 406 }
 407
 408 static int i915_resume(struct drm_device *dev)
 409 {
 410         struct drm_i915_private *dev_priv = dev->dev_private;
 411         int i;
 412
 413         pci_set_power_state(dev->pdev, PCI_D0);
 414         pci_restore_state(dev->pdev);
 415         if (pci_enable_device(dev->pdev))
 416                 return -1;
 417
 418         pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
 419
 420         /* Pipe & plane A info */
 421         /* Prime the clock */
 422         if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
 423                 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
 424                            ~DPLL_VCO_ENABLE);
 425                 udelay(150);
 426         }
 427         I915_WRITE(FPA0, dev_priv->saveFPA0);
 428         I915_WRITE(FPA1, dev_priv->saveFPA1);
 429         /* Actually enable it */
 430         I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
 431         udelay(150);
 432         if (IS_I965G(dev))
 433                 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
 434         udelay(150);
 435
 436         /* Restore mode */
 437         I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
 438         I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
 439         I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
 440         I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
 441         I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
 442         I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
 443         I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
 444
 445         /* Restore plane info */
 446         I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
 447         I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
 448         I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
 449         I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
 450         I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
 451         if (IS_I965G(dev)) {
 452                 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
 453                 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
 454         }
 455
 456         I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
 457
 458         i915_restore_palette(dev, PIPE_A);
 459         /* Enable the plane */
 460         I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
 461         I915_WRITE(DSPABASE, I915_READ(DSPABASE));
 462
 463         /* Pipe & plane B info */
 464         if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
 465                 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
 466                            ~DPLL_VCO_ENABLE);
 467                 udelay(150);
 468         }
 469         I915_WRITE(FPB0, dev_priv->saveFPB0);
 470         I915_WRITE(FPB1, dev_priv->saveFPB1);
 471         /* Actually enable it */
 472         I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
 473         udelay(150);
 474         if (IS_I965G(dev))
 475                 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
 476         udelay(150);
 477
 478         /* Restore mode */
 479         I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
 480         I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
 481         I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
 482         I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
 483         I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
 484         I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
 485         I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
 486
 487         /* Restore plane info */
 488         I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
 489         I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
 490         I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
 491         I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
 492         I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
 493         if (IS_I965G(dev)) {
 494                 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
 495                 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
 496         }
 497
 498         I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
 499
 500         i915_restore_palette(dev, PIPE_B);
 501         /* Enable the plane */
 502         I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
 503         I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
 504
 505         /* CRT state */
 506         I915_WRITE(ADPA, dev_priv->saveADPA);
 507
 508         /* LVDS state */
 509         if (IS_I965G(dev))
 510                 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
 511         if (IS_MOBILE(dev) && !IS_I830(dev))
 512                 I915_WRITE(LVDS, dev_priv->saveLVDS);
 513         if (!IS_I830(dev) && !IS_845G(dev))
 514                 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
 515
 516         I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
 517         I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
 518         I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON);
 519         I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF);
 520         I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
 521         I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
 522
 523         /* FIXME: restore TV & SDVO state */
 524
 525         /* FBC info */
 526         I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
 527         I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
 528         I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
 529         I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
 530
 531         /* VGA state */
 532         I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
 533         I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
 534         I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
 535         I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
 536         udelay(150);
 537
 538         /* Clock gating state */
 539         I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
 540
 541         /* Cache mode state */
 542         I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
 543
 544         /* Memory arbitration state */
 545         I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
 546
 547         for (i = 0; i < 16; i++) {
 548                 I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF0[i]);
 549                 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
 550         }
 551         for (i = 0; i < 3; i++)
 552                 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
 553
 554         i915_restore_vga(dev);
 555
 556         return 0;
 557 }
 558
 559 static int probe(struct pci_dev *pdev, const struct pci_device_id *ent);
 560 static struct drm_driver driver = {
 561         /* don't use mtrr's here, the Xserver or user space app should
 562          * deal with them for intel hardware.
 563          */
 564         .driver_features =
 565             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR | */
 566             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED,
 567         .load = i915_driver_load,
 568         .unload = i915_driver_unload,
 569         .lastclose = i915_driver_lastclose,
 570         .preclose = i915_driver_preclose,
 571         .suspend = i915_suspend,
 572         .resume = i915_resume,
 573         .device_is_agp = i915_driver_device_is_agp,
 574         .get_vblank_counter = i915_get_vblank_counter,
 575         .enable_vblank = i915_enable_vblank,
 576         .disable_vblank = i915_disable_vblank,
 577         .irq_preinstall = i915_driver_irq_preinstall,
 578         .irq_postinstall = i915_driver_irq_postinstall,
 579         .irq_uninstall = i915_driver_irq_uninstall,
 580         .irq_handler = i915_driver_irq_handler,
 581         .reclaim_buffers = drm_core_reclaim_buffers,
 582         .get_map_ofs = drm_core_get_map_ofs,
 583         .get_reg_ofs = drm_core_get_reg_ofs,
 584         .fb_probe = intelfb_probe,
 585         .fb_remove = intelfb_remove,
 586         .fb_resize = intelfb_resize,
 587         .master_create = i915_master_create,
 588         .master_destroy = i915_master_destroy,
 589         .ioctls = i915_ioctls,
 590         .fops = {
 591                 .owner = THIS_MODULE,
 592                 .open = drm_open,
 593                 .release = drm_release,
 594                 .ioctl = drm_ioctl,
 595                 .mmap = drm_mmap,
 596                 .poll = drm_poll,
 597                 .fasync = drm_fasync,
 598 #if defined(CONFIG_COMPAT) && LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
 599                 .compat_ioctl = i915_compat_ioctl,
 600 #endif
 601                 },
 602         .pci_driver = {
 603                 .name = DRIVER_NAME,
 604                 .id_table = pciidlist,
 605                 .probe = probe,
 606                 .remove = __devexit_p(drm_cleanup_pci),
 607                 },
 608 #ifdef I915_HAVE_FENCE
 609         .fence_driver = &i915_fence_driver,
 610 #endif
 611 #ifdef I915_HAVE_BUFFER
 612         .bo_driver = &i915_bo_driver,
 613 #endif
 614         .name = DRIVER_NAME,
 615         .desc = DRIVER_DESC,
 616         .date = DRIVER_DATE,
 617         .major = DRIVER_MAJOR,
 618         .minor = DRIVER_MINOR,
 619         .patchlevel = DRIVER_PATCHLEVEL,
 620 };
 621
 622 static int probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 623 {
 624         return drm_get_dev(pdev, ent, &driver);
 625 }
 626
 627 static int __init i915_init(void)
 628 {
 629         driver.num_ioctls = i915_max_ioctl;
 630         if (i915_modeset == 1)
 631                 driver.driver_features |= DRIVER_MODESET;
 632
 633         return drm_init(&driver, pciidlist);
 634 }
 635
 636 static void __exit i915_exit(void)
 637 {
 638         drm_exit(&driver);
 639 }
 640
 641 module_init(i915_init);
 642 module_exit(i915_exit);
 643
 644 MODULE_AUTHOR(DRIVER_AUTHOR);
 645 MODULE_DESCRIPTION(DRIVER_DESC);
 646 MODULE_LICENSE("GPL and additional rights");