linux-core/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drm.h"
  33 #include "intel_drv.h"
  34 #include "i915_drv.h"
  35
  36 #include "drm_pciids.h"
  37
  38 static struct pci_device_id pciidlist[] = {
  39         i915_PCI_IDS
  40 };
  41
  42 unsigned int i915_modeset = 0;
  43 module_param_named(modeset, i915_modeset, int, 0400);
  44
  45 unsigned int i915_fbpercrtc = 0;
  46 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  47
  48 unsigned int i915_rightof = 1;
  49 module_param_named(i915_rightof, i915_rightof, int, 0400);
  50
  51 #if defined(I915_HAVE_FENCE) && defined(I915_TTM)
  52 extern struct drm_fence_driver i915_fence_driver;
  53 #endif
  54
  55 #if defined(I915_HAVE_BUFFER) && defined(I915_TTM)
  56
  57 static uint32_t i915_mem_prios[] = {DRM_BO_MEM_VRAM, DRM_BO_MEM_TT, DRM_BO_MEM_LOCAL};
  58 static uint32_t i915_busy_prios[] = {DRM_BO_MEM_TT, DRM_BO_MEM_VRAM, DRM_BO_MEM_LOCAL};
  59
  60 static struct drm_bo_driver i915_bo_driver = {
  61         .mem_type_prio = i915_mem_prios,
  62         .mem_busy_prio = i915_busy_prios,
  63         .num_mem_type_prio = sizeof(i915_mem_prios)/sizeof(uint32_t),
  64         .num_mem_busy_prio = sizeof(i915_busy_prios)/sizeof(uint32_t),
  65         .create_ttm_backend_entry = i915_create_ttm_backend_entry,
  66         .fence_type = i915_fence_type,
  67         .invalidate_caches = i915_invalidate_caches,
  68         .init_mem_type = i915_init_mem_type,
  69         .evict_flags = i915_evict_flags,
  70         .move = i915_move,
  71         .ttm_cache_flush = i915_flush_ttm,
  72         .command_stream_barrier = NULL,
  73 };
  74 #endif /* ttm */
  75
  76 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
  77 {
  78         struct drm_i915_private *dev_priv = dev->dev_private;
  79
  80         if (pipe == PIPE_A)
  81                 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
  82         else
  83                 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
  84 }
  85
  86 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
  87 {
  88         struct drm_i915_private *dev_priv = dev->dev_private;
  89         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
  90         u32 *array;
  91         int i;
  92
  93         if (!i915_pipe_enabled(dev, pipe))
  94                 return;
  95
  96         if (pipe == PIPE_A)
  97                 array = dev_priv->save_palette_a;
  98         else
  99                 array = dev_priv->save_palette_b;
 100
 101         for(i = 0; i < 256; i++)
 102                 array[i] = I915_READ(reg + (i << 2));
 103 }
 104
 105 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
 106 {
 107         struct drm_i915_private *dev_priv = dev->dev_private;
 108         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
 109         u32 *array;
 110         int i;
 111
 112         if (!i915_pipe_enabled(dev, pipe))
 113                 return;
 114
 115         if (pipe == PIPE_A)
 116                 array = dev_priv->save_palette_a;
 117         else
 118                 array = dev_priv->save_palette_b;
 119
 120         for(i = 0; i < 256; i++)
 121                 I915_WRITE(reg + (i << 2), array[i]);
 122 }
 123
 124 static u8 i915_read_indexed(u16 index_port, u16 data_port, u8 reg)
 125 {
 126         outb(reg, index_port);
 127         return inb(data_port);
 128 }
 129
 130 static u8 i915_read_ar(u16 st01, u8 reg, u16 palette_enable)
 131 {
 132         inb(st01);
 133         outb(palette_enable | reg, VGA_AR_INDEX);
 134         return inb(VGA_AR_DATA_READ);
 135 }
 136
 137 static void i915_write_ar(u8 st01, u8 reg, u8 val, u16 palette_enable)
 138 {
 139         inb(st01);
 140         outb(palette_enable | reg, VGA_AR_INDEX);
 141         outb(val, VGA_AR_DATA_WRITE);
 142 }
 143
 144 static void i915_write_indexed(u16 index_port, u16 data_port, u8 reg, u8 val)
 145 {
 146         outb(reg, index_port);
 147         outb(val, data_port);
 148 }
 149
 150 static void i915_save_vga(struct drm_device *dev)
 151 {
 152         struct drm_i915_private *dev_priv = dev->dev_private;
 153         int i;
 154         u16 cr_index, cr_data, st01;
 155
 156         /* VGA color palette registers */
 157         dev_priv->saveDACMASK = inb(VGA_DACMASK);
 158         /* DACCRX automatically increments during read */
 159         outb(0, VGA_DACRX);
 160         /* Read 3 bytes of color data from each index */
 161         for (i = 0; i < 256 * 3; i++)
 162                 dev_priv->saveDACDATA[i] = inb(VGA_DACDATA);
 163
 164         /* MSR bits */
 165         dev_priv->saveMSR = inb(VGA_MSR_READ);
 166         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 167                 cr_index = VGA_CR_INDEX_CGA;
 168                 cr_data = VGA_CR_DATA_CGA;
 169                 st01 = VGA_ST01_CGA;
 170         } else {
 171                 cr_index = VGA_CR_INDEX_MDA;
 172                 cr_data = VGA_CR_DATA_MDA;
 173                 st01 = VGA_ST01_MDA;
 174         }
 175
 176         /* CRT controller regs */
 177         i915_write_indexed(cr_index, cr_data, 0x11,
 178                            i915_read_indexed(cr_index, cr_data, 0x11) &
 179                            (~0x80));
 180         for (i = 0; i <= 0x24; i++)
 181                 dev_priv->saveCR[i] =
 182                         i915_read_indexed(cr_index, cr_data, i);
 183         /* Make sure we don't turn off CR group 0 writes */
 184         dev_priv->saveCR[0x11] &= ~0x80;
 185
 186         /* Attribute controller registers */
 187         inb(st01);
 188         dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
 189         for (i = 0; i <= 0x14; i++)
 190                 dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
 191         inb(st01);
 192         outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
 193         inb(st01);
 194
 195         /* Graphics controller registers */
 196         for (i = 0; i < 9; i++)
 197                 dev_priv->saveGR[i] =
 198                         i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, i);
 199
 200         dev_priv->saveGR[0x10] =
 201                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10);
 202         dev_priv->saveGR[0x11] =
 203                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11);
 204         dev_priv->saveGR[0x18] =
 205                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18);
 206
 207         /* Sequencer registers */
 208         for (i = 0; i < 8; i++)
 209                 dev_priv->saveSR[i] =
 210                         i915_read_indexed(VGA_SR_INDEX, VGA_SR_DATA, i);
 211 }
 212
 213 static void i915_restore_vga(struct drm_device *dev)
 214 {
 215         struct drm_i915_private *dev_priv = dev->dev_private;
 216         int i;
 217         u16 cr_index, cr_data, st01;
 218
 219         /* MSR bits */
 220         outb(dev_priv->saveMSR, VGA_MSR_WRITE);
 221         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 222                 cr_index = VGA_CR_INDEX_CGA;
 223                 cr_data = VGA_CR_DATA_CGA;
 224                 st01 = VGA_ST01_CGA;
 225         } else {
 226                 cr_index = VGA_CR_INDEX_MDA;
 227                 cr_data = VGA_CR_DATA_MDA;
 228                 st01 = VGA_ST01_MDA;
 229         }
 230
 231         /* Sequencer registers, don't write SR07 */
 232         for (i = 0; i < 7; i++)
 233                 i915_write_indexed(VGA_SR_INDEX, VGA_SR_DATA, i,
 234                                    dev_priv->saveSR[i]);
 235
 236         /* CRT controller regs */
 237         /* Enable CR group 0 writes */
 238         i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
 239         for (i = 0; i <= 0x24; i++)
 240                 i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);
 241
 242         /* Graphics controller regs */
 243         for (i = 0; i < 9; i++)
 244                 i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, i,
 245                                    dev_priv->saveGR[i]);
 246
 247         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10,
 248                            dev_priv->saveGR[0x10]);
 249         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11,
 250                            dev_priv->saveGR[0x11]);
 251         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18,
 252                            dev_priv->saveGR[0x18]);
 253
 254         /* Attribute controller registers */
 255         inb(st01); /* switch back to index mode */
 256         for (i = 0; i <= 0x14; i++)
 257                 i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
 258         inb(st01); /* switch back to index mode */
 259         outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX);
 260         inb(st01);
 261
 262         /* VGA color palette registers */
 263         outb(dev_priv->saveDACMASK, VGA_DACMASK);
 264         /* DACCRX automatically increments during read */
 265         outb(0, VGA_DACWX);
 266         /* Read 3 bytes of color data from each index */
 267         for (i = 0; i < 256 * 3; i++)
 268                 outb(dev_priv->saveDACDATA[i], VGA_DACDATA);
 269
 270 }
 271
 272 static int i915_suspend(struct drm_device *dev, pm_message_t state)
 273 {
 274         struct drm_i915_private *dev_priv = dev->dev_private;
 275
 276         if (!dev || !dev_priv) {
 277                 printk(KERN_ERR "dev: %p, dev_priv: %p\n", dev, dev_priv);
 278                 printk(KERN_ERR "DRM not initialized, aborting suspend.\n");
 279                 return -ENODEV;
 280         }
 281
 282         if (state.event == PM_EVENT_PRETHAW)
 283                 return 0;
 284
 285         pci_save_state(dev->pdev);
 286
 287         i915_save_state(dev);
 288
 289 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)
 290         intel_opregion_free(dev);
 291 #endif
 292
 293         if (state.event == PM_EVENT_SUSPEND) {
 294                 /* Shut down the device */
 295                 pci_disable_device(dev->pdev);
 296                 pci_set_power_state(dev->pdev, PCI_D3hot);
 297         }
 298
 299         return 0;
 300 }
 301
 302 static int i915_resume(struct drm_device *dev)
 303 {
 304         pci_set_power_state(dev->pdev, PCI_D0);
 305         pci_restore_state(dev->pdev);
 306         if (pci_enable_device(dev->pdev))
 307                 return -1;
 308         pci_set_master(dev->pdev);
 309
 310         i915_restore_state(dev);
 311
 312 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)
 313         intel_opregion_init(dev);
 314 #endif
 315
 316         return 0;
 317 }
 318
 319 static int probe(struct pci_dev *pdev, const struct pci_device_id *ent);
 320 static void remove(struct pci_dev *pdev);
 321
 322 static struct drm_driver driver = {
 323         /* don't use mtrr's here, the Xserver or user space app should
 324          * deal with them for intel hardware.
 325          */
 326         .driver_features =
 327             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR | */
 328             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 329         .load = i915_driver_load,
 330         .unload = i915_driver_unload,
 331         .firstopen = i915_driver_firstopen,
 332         .open = i915_driver_open,
 333         .lastclose = i915_driver_lastclose,
 334         .preclose = i915_driver_preclose,
 335         .postclose = i915_driver_postclose,
 336         .suspend = i915_suspend,
 337         .resume = i915_resume,
 338         .device_is_agp = i915_driver_device_is_agp,
 339         .get_vblank_counter = i915_get_vblank_counter,
 340         .enable_vblank = i915_enable_vblank,
 341         .disable_vblank = i915_disable_vblank,
 342         .irq_preinstall = i915_driver_irq_preinstall,
 343         .irq_postinstall = i915_driver_irq_postinstall,
 344         .irq_uninstall = i915_driver_irq_uninstall,
 345         .irq_handler = i915_driver_irq_handler,
 346         .reclaim_buffers = drm_core_reclaim_buffers,
 347         .get_map_ofs = drm_core_get_map_ofs,
 348         .get_reg_ofs = drm_core_get_reg_ofs,
 349         .master_create = i915_master_create,
 350         .master_destroy = i915_master_destroy,
 351         .proc_init = i915_gem_proc_init,
 352         .proc_cleanup = i915_gem_proc_cleanup,
 353         .ioctls = i915_ioctls,
 354         .gem_init_object = i915_gem_init_object,
 355         .gem_free_object = i915_gem_free_object,
 356         .fops = {
 357                 .owner = THIS_MODULE,
 358                 .open = drm_open,
 359                 .release = drm_release,
 360                 .ioctl = drm_ioctl,
 361                 .mmap = drm_mmap,
 362                 .poll = drm_poll,
 363                 .fasync = drm_fasync,
 364 #if defined(CONFIG_COMPAT) && LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
 365                 .compat_ioctl = i915_compat_ioctl,
 366 #endif
 367                 },
 368         .pci_driver = {
 369                 .name = DRIVER_NAME,
 370                 .id_table = pciidlist,
 371                 .probe = probe,
 372                 .remove = remove,
 373                 },
 374 #if defined(I915_HAVE_FENCE) && defined(I915_TTM)
 375         .fence_driver = &i915_fence_driver,
 376 #endif
 377 #if defined(I915_HAVE_BUFFER) && defined(I915_TTM)
 378         .bo_driver = &i915_bo_driver,
 379 #endif
 380         .name = DRIVER_NAME,
 381         .desc = DRIVER_DESC,
 382         .date = DRIVER_DATE,
 383         .major = DRIVER_MAJOR,
 384         .minor = DRIVER_MINOR,
 385         .patchlevel = DRIVER_PATCHLEVEL,
 386 };
 387
 388 static int probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 389 {
 390         int ret;
 391
 392         /* On the 945G/GM, the chipset reports the MSI capability on the
 393          * integrated graphics even though the support isn't actually there
 394          * according to the published specs.  It doesn't appear to function
 395          * correctly in testing on 945G.
 396          * This may be a side effect of MSI having been made available for PEG
 397          * and the registers being closely associated.
 398          */
 399         if (pdev->device != 0x2772 && pdev->device != 0x27A2)
 400                 (void )pci_enable_msi(pdev);
 401
 402         ret = drm_get_dev(pdev, ent, &driver);
 403         if (ret && pdev->msi_enabled)
 404                 pci_disable_msi(pdev);
 405         return ret;
 406 }
 407 static void remove(struct pci_dev *pdev)
 408 {
 409         drm_cleanup_pci(pdev);
 410         if (pdev->msi_enabled)
 411                 pci_disable_msi(pdev);
 412 }
 413
 414 static int __init i915_init(void)
 415 {
 416         driver.num_ioctls = i915_max_ioctl;
 417         if (i915_modeset == 1)
 418                 driver.driver_features |= DRIVER_MODESET;
 419
 420         return drm_init(&driver, pciidlist);
 421 }
 422
 423 static void __exit i915_exit(void)
 424 {
 425         drm_exit(&driver);
 426 }
 427
 428 module_init(i915_init);
 429 module_exit(i915_exit);
 430
 431 MODULE_AUTHOR(DRIVER_AUTHOR);
 432 MODULE_DESCRIPTION(DRIVER_DESC);
 433 MODULE_LICENSE("GPL and additional rights");