1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
27 **************************************************************************/
29 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
36 drm_ttm_backend_t *i915_create_ttm_backend_entry(drm_device_t * dev)
38 return drm_agp_init_ttm(dev);
41 int i915_fence_types(drm_buffer_object_t *bo, uint32_t * class, uint32_t * type)
44 if (bo->mem.flags & (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE))
51 int i915_invalidate_caches(drm_device_t * dev, uint32_t flags)
54 * FIXME: Only emit once per batchbuffer submission.
57 uint32_t flush_cmd = MI_NO_WRITE_FLUSH;
59 if (flags & DRM_BO_FLAG_READ)
60 flush_cmd |= MI_READ_FLUSH;
61 if (flags & DRM_BO_FLAG_EXE)
62 flush_cmd |= MI_EXE_FLUSH;
64 return i915_emit_mi_flush(dev, flush_cmd);
67 int i915_init_mem_type(drm_device_t * dev, uint32_t type,
68 drm_mem_type_manager_t * man)
71 case DRM_BO_MEM_LOCAL:
72 man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
73 _DRM_FLAG_MEMTYPE_CACHED;
74 man->drm_bus_maptype = 0;
77 if (!(drm_core_has_AGP(dev) && dev->agp)) {
78 DRM_ERROR("AGP is not enabled for memory type %u\n",
82 man->io_offset = dev->agp->agp_info.aper_base;
83 man->io_size = dev->agp->agp_info.aper_size * 1024 * 1024;
85 man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
86 _DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_NEEDS_IOREMAP;
87 man->drm_bus_maptype = _DRM_AGP;
90 if (!(drm_core_has_AGP(dev) && dev->agp)) {
91 DRM_ERROR("AGP is not enabled for memory type %u\n",
95 man->io_offset = dev->agp->agp_info.aper_base;
96 man->io_size = dev->agp->agp_info.aper_size * 1024 * 1024;
98 man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
99 _DRM_FLAG_MEMTYPE_FIXED | _DRM_FLAG_NEEDS_IOREMAP;
100 man->drm_bus_maptype = _DRM_AGP;
102 case DRM_BO_MEM_PRIV0: /* for OS preallocated space */
103 DRM_ERROR("PRIV0 not used yet.\n");
106 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
112 uint32_t i915_evict_mask(drm_buffer_object_t *bo)
114 switch (bo->mem.mem_type) {
115 case DRM_BO_MEM_LOCAL:
117 return DRM_BO_FLAG_MEM_LOCAL;
119 return DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_CACHED;
123 static void i915_emit_copy_blit(drm_device_t * dev,
126 uint32_t pages, int direction)
129 uint32_t stride = PAGE_SIZE;
130 drm_i915_private_t *dev_priv = dev->dev_private;
136 i915_kernel_lost_context(dev);
139 if (cur_pages > 2048)
144 OUT_RING(SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
145 XY_SRC_COPY_BLT_WRITE_RGB);
146 OUT_RING((stride & 0xffff) | (0xcc << 16) | (1 << 24) |
147 (1 << 25) | (direction ? (1 << 30) : 0));
148 OUT_RING((cur_pages << 16) | PAGE_SIZE);
149 OUT_RING(dst_offset);
150 OUT_RING(stride & 0xffff);
151 OUT_RING(src_offset);
157 static int i915_move_blit(drm_buffer_object_t * bo,
158 int evict, int no_wait, drm_bo_mem_reg_t * new_mem)
160 drm_bo_mem_reg_t *old_mem = &bo->mem;
163 if ((old_mem->mem_type == new_mem->mem_type) &&
164 (new_mem->mm_node->start <
165 old_mem->mm_node->start + old_mem->mm_node->size)) {
169 i915_emit_copy_blit(bo->dev,
170 old_mem->mm_node->start << PAGE_SHIFT,
171 new_mem->mm_node->start << PAGE_SHIFT,
172 new_mem->num_pages, dir);
174 i915_emit_mi_flush(bo->dev, MI_READ_FLUSH | MI_EXE_FLUSH);
176 return drm_bo_move_accel_cleanup(bo, evict, no_wait, 0,
178 DRM_I915_FENCE_TYPE_RW,
179 DRM_I915_FENCE_FLAG_FLUSHED, new_mem);
183 * Flip destination ttm into cached-coherent AGP,
184 * then blit and subsequently move out again.
187 static int i915_move_flip(drm_buffer_object_t * bo,
188 int evict, int no_wait, drm_bo_mem_reg_t * new_mem)
190 drm_device_t *dev = bo->dev;
191 drm_bo_mem_reg_t tmp_mem;
195 tmp_mem.mm_node = NULL;
196 tmp_mem.mask = DRM_BO_FLAG_MEM_TT |
197 DRM_BO_FLAG_CACHED | DRM_BO_FLAG_FORCE_CACHING;
199 ret = drm_bo_mem_space(bo, &tmp_mem, no_wait);
203 ret = drm_bind_ttm(bo->ttm, 1, tmp_mem.mm_node->start);
207 ret = i915_move_blit(bo, 1, no_wait, &tmp_mem);
211 ret = drm_bo_move_ttm(bo, evict, no_wait, new_mem);
213 if (tmp_mem.mm_node) {
214 mutex_lock(&dev->struct_mutex);
215 if (tmp_mem.mm_node != bo->pinned_node)
216 drm_mm_put_block(tmp_mem.mm_node);
217 tmp_mem.mm_node = NULL;
218 mutex_unlock(&dev->struct_mutex);
223 int i915_move(drm_buffer_object_t * bo,
224 int evict, int no_wait, drm_bo_mem_reg_t * new_mem)
226 drm_bo_mem_reg_t *old_mem = &bo->mem;
228 if (old_mem->mem_type == DRM_BO_MEM_LOCAL) {
229 return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
230 } else if (new_mem->mem_type == DRM_BO_MEM_LOCAL) {
231 if (i915_move_flip(bo, evict, no_wait, new_mem))
232 return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
234 if (i915_move_blit(bo, evict, no_wait, new_mem))
235 return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);