1 /* i810_drv.h -- Private header for the Matrox g200/g400 driver -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
26 * Authors: Rickard E. (Rik) Faith <faith@precisioninsight.com>
27 * Jeff Hartmann <jhartmann@precisioninsight.com>
29 * $XFree86: xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_drv.h,v 1.1 2000/02/11 17:26:05 dawes Exp $
35 typedef struct _drm_i810_ring_buffer{
44 } drm_i810_ring_buffer_t;
46 typedef struct drm_i810_private {
50 drm_i810_ring_buffer_t ring;
51 drm_i810_sarea_t *sarea_priv;
53 unsigned long hw_status_page;
54 unsigned long counter;
57 wait_queue_head_t flush_queue; /* Processes waiting until flush */
61 extern int i810_init(void);
62 extern void i810_cleanup(void);
63 extern int i810_version(struct inode *inode, struct file *filp,
64 unsigned int cmd, unsigned long arg);
65 extern int i810_open(struct inode *inode, struct file *filp);
66 extern int i810_release(struct inode *inode, struct file *filp);
67 extern int i810_ioctl(struct inode *inode, struct file *filp,
68 unsigned int cmd, unsigned long arg);
69 extern int i810_unlock(struct inode *inode, struct file *filp,
70 unsigned int cmd, unsigned long arg);
73 extern int i810_dma_schedule(drm_device_t *dev, int locked);
74 extern int i810_dma(struct inode *inode, struct file *filp,
75 unsigned int cmd, unsigned long arg);
76 extern int i810_irq_install(drm_device_t *dev, int irq);
77 extern int i810_irq_uninstall(drm_device_t *dev);
78 extern int i810_control(struct inode *inode, struct file *filp,
79 unsigned int cmd, unsigned long arg);
80 extern int i810_lock(struct inode *inode, struct file *filp,
81 unsigned int cmd, unsigned long arg);
82 extern int i810_dma_init(struct inode *inode, struct file *filp,
83 unsigned int cmd, unsigned long arg);
84 extern int i810_flush_ioctl(struct inode *inode, struct file *filp,
85 unsigned int cmd, unsigned long arg);
86 extern void i810_reclaim_buffers(drm_device_t *dev, pid_t pid);
87 extern int i810_getage(struct inode *inode, struct file *filp, unsigned int cmd,
92 extern int i810_addbufs(struct inode *inode, struct file *filp,
93 unsigned int cmd, unsigned long arg);
94 extern int i810_infobufs(struct inode *inode, struct file *filp,
95 unsigned int cmd, unsigned long arg);
96 extern int i810_markbufs(struct inode *inode, struct file *filp,
97 unsigned int cmd, unsigned long arg);
98 extern int i810_freebufs(struct inode *inode, struct file *filp,
99 unsigned int cmd, unsigned long arg);
100 extern int i810_mapbufs(struct inode *inode, struct file *filp,
101 unsigned int cmd, unsigned long arg);
102 extern int i810_addmap(struct inode *inode, struct file *filp,
103 unsigned int cmd, unsigned long arg);
106 extern int i810_resctx(struct inode *inode, struct file *filp,
107 unsigned int cmd, unsigned long arg);
108 extern int i810_addctx(struct inode *inode, struct file *filp,
109 unsigned int cmd, unsigned long arg);
110 extern int i810_modctx(struct inode *inode, struct file *filp,
111 unsigned int cmd, unsigned long arg);
112 extern int i810_getctx(struct inode *inode, struct file *filp,
113 unsigned int cmd, unsigned long arg);
114 extern int i810_switchctx(struct inode *inode, struct file *filp,
115 unsigned int cmd, unsigned long arg);
116 extern int i810_newctx(struct inode *inode, struct file *filp,
117 unsigned int cmd, unsigned long arg);
118 extern int i810_rmctx(struct inode *inode, struct file *filp,
119 unsigned int cmd, unsigned long arg);
121 extern int i810_context_switch(drm_device_t *dev, int old, int new);
122 extern int i810_context_switch_complete(drm_device_t *dev, int new);
127 /* Copy the outstanding cliprects for every I810_DMA_VERTEX buffer.
128 * This can be fixed by emitting directly to the ringbuffer in the
129 * 'vertex_dma' ioctl.
134 } drm_i810_buf_priv_t;
137 #define I810_DMA_GENERAL 0
138 #define I810_DMA_VERTEX 1
139 #define I810_DMA_DISCARD 2 /* not used */
141 #define I810_VERBOSE 0
144 int i810_dma_vertex(struct inode *inode, struct file *filp,
145 unsigned int cmd, unsigned long arg);
147 int i810_dma_general(struct inode *inode, struct file *filp,
148 unsigned int cmd, unsigned long arg);
151 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
152 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
153 #define CMD_REPORT_HEAD (7<<23)
154 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
155 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
157 #define INST_PARSER_CLIENT 0x00000000
158 #define INST_OP_FLUSH 0x02000000
159 #define INST_FLUSH_MAP_CACHE 0x00000001
162 #define BB1_START_ADDR_MASK (~0x7)
163 #define BB1_PROTECTED (1<<0)
164 #define BB1_UNPROTECTED (0<<0)
165 #define BB2_END_ADDR_MASK (~0x7)
167 #define I810REG_HWSTAM 0x02098
168 #define I810REG_INT_IDENTITY_R 0x020a4
169 #define I810REG_INT_MASK_R 0x020a8
170 #define I810REG_INT_ENABLE_R 0x020a0
172 #define LP_RING 0x2030
173 #define HP_RING 0x2040
174 #define RING_TAIL 0x00
175 #define TAIL_ADDR 0x000FFFF8
176 #define RING_HEAD 0x04
177 #define HEAD_WRAP_COUNT 0xFFE00000
178 #define HEAD_WRAP_ONE 0x00200000
179 #define HEAD_ADDR 0x001FFFFC
180 #define RING_START 0x08
181 #define START_ADDR 0x00FFFFF8
182 #define RING_LEN 0x0C
183 #define RING_NR_PAGES 0x000FF000
184 #define RING_REPORT_MASK 0x00000006
185 #define RING_REPORT_64K 0x00000002
186 #define RING_REPORT_128K 0x00000004
187 #define RING_NO_REPORT 0x00000000
188 #define RING_VALID_MASK 0x00000001
189 #define RING_VALID 0x00000001
190 #define RING_INVALID 0x00000000
192 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
193 #define SC_UPDATE_SCISSOR (0x1<<1)
194 #define SC_ENABLE_MASK (0x1<<0)
195 #define SC_ENABLE (0x1<<0)
197 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
198 #define SCI_YMIN_MASK (0xffff<<16)
199 #define SCI_XMIN_MASK (0xffff<<0)
200 #define SCI_YMAX_MASK (0xffff<<16)
201 #define SCI_XMAX_MASK (0xffff<<0)