linux-core/atombios_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon_drv.h"
  29
  30 #include "drm_crtc_helper.h"
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33
  34 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
  35 {
  36         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  37         struct drm_device *dev = crtc->dev;
  38         struct drm_radeon_private *dev_priv = dev->dev_private;
  39         int index = GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
  40         ENABLE_CRTC_PS_ALLOCATION args;
  41
  42         memset(&args, 0, sizeof(args));
  43
  44         args.ucCRTC = radeon_crtc->crtc_id;
  45         args.ucEnable = lock;
  46
  47         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
  48 }
  49
  50 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
  51 {
  52         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  53         struct drm_device *dev = crtc->dev;
  54         struct drm_radeon_private *dev_priv = dev->dev_private;
  55         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
  56         ENABLE_CRTC_PS_ALLOCATION args;
  57
  58         memset(&args, 0, sizeof(args));
  59
  60         args.ucCRTC = radeon_crtc->crtc_id;
  61         args.ucEnable = state;
  62
  63         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
  64 }
  65
  66 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
  67 {
  68         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  69         struct drm_device *dev = crtc->dev;
  70         struct drm_radeon_private *dev_priv = dev->dev_private;
  71         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
  72         ENABLE_CRTC_PS_ALLOCATION args;
  73
  74         memset(&args, 0, sizeof(args));
  75
  76         args.ucCRTC = radeon_crtc->crtc_id;
  77         args.ucEnable = state;
  78
  79         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
  80 }
  81
  82 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
  83 {
  84         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  85         struct drm_device *dev = crtc->dev;
  86         struct drm_radeon_private *dev_priv = dev->dev_private;
  87         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
  88         BLANK_CRTC_PS_ALLOCATION args;
  89
  90         memset(&args, 0, sizeof(args));
  91
  92         args.ucCRTC = radeon_crtc->crtc_id;
  93         args.ucBlanking = state;
  94
  95         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
  96 }
  97
  98 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
  99 {
 100         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 101         struct drm_device *dev = crtc->dev;
 102         struct drm_radeon_private *dev_priv = dev->dev_private;
 103
 104         switch(mode) {
 105         case DRM_MODE_DPMS_ON:
 106         case DRM_MODE_DPMS_STANDBY:
 107         case DRM_MODE_DPMS_SUSPEND:
 108                 if (radeon_is_dce3(dev_priv))
 109                         atombios_enable_crtc_memreq(crtc, 1);
 110                 atombios_enable_crtc(crtc, 1);
 111                 atombios_blank_crtc(crtc, 0);
 112
 113                 radeon_crtc_load_lut(crtc);
 114                 break;
 115         case DRM_MODE_DPMS_OFF:
 116                 atombios_blank_crtc(crtc, 1);
 117                 atombios_enable_crtc(crtc, 0);
 118                 if (radeon_is_dce3(dev_priv))
 119                         atombios_enable_crtc_memreq(crtc, 0);
 120                 break;
 121         }
 122 }
 123
 124
 125 void atombios_crtc_set_timing(struct drm_crtc *crtc, SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_param)
 126 {
 127         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 128         struct drm_device *dev = crtc->dev;
 129         struct drm_radeon_private *dev_priv = dev->dev_private;
 130         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION conv_param;
 131         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
 132
 133         conv_param.usH_Total                = cpu_to_le16(crtc_param->usH_Total);
 134         conv_param.usH_Disp                 = cpu_to_le16(crtc_param->usH_Disp);
 135         conv_param.usH_SyncStart            = cpu_to_le16(crtc_param->usH_SyncStart);
 136         conv_param.usH_SyncWidth            = cpu_to_le16(crtc_param->usH_SyncWidth);
 137         conv_param.usV_Total                = cpu_to_le16(crtc_param->usV_Total);
 138         conv_param.usV_Disp                 = cpu_to_le16(crtc_param->usV_Disp);
 139         conv_param.usV_SyncStart            = cpu_to_le16(crtc_param->usV_SyncStart);
 140         conv_param.usV_SyncWidth            = cpu_to_le16(crtc_param->usV_SyncWidth);
 141         conv_param.susModeMiscInfo.usAccess = cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
 142         conv_param.ucCRTC                   = crtc_param->ucCRTC;
 143         conv_param.ucOverscanRight          = crtc_param->ucOverscanRight;
 144         conv_param.ucOverscanLeft           = crtc_param->ucOverscanLeft;
 145         conv_param.ucOverscanBottom         = crtc_param->ucOverscanBottom;
 146         conv_param.ucOverscanTop            = crtc_param->ucOverscanTop;
 147         conv_param.ucReserved               = crtc_param->ucReserved;
 148
 149         printk("executing set crtc timing\n");
 150         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&conv_param);
 151 }
 152
 153 void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 154 {
 155         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 156         struct drm_device *dev = crtc->dev;
 157         struct drm_radeon_private *dev_priv = dev->dev_private;
 158         uint8_t frev, crev;
 159         int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 160         SET_PIXEL_CLOCK_PS_ALLOCATION spc_param;
 161         PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
 162         PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
 163         uint32_t sclock = mode->clock;
 164         uint32_t ref_div = 0, fb_div = 0, post_div = 0;
 165         struct radeon_pll *pll;
 166         int pll_flags = 0;
 167
 168         memset(&spc_param, 0, sizeof(SET_PIXEL_CLOCK_PS_ALLOCATION));
 169
 170         if (!radeon_is_avivo(dev_priv))
 171                 pll_flags |= RADEON_PLL_LEGACY;
 172
 173         if (mode->clock > 120000) /* range limits??? */
 174                 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 175         else
 176                 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 177
 178         if (radeon_crtc->crtc_id == 0)
 179                 pll = &dev_priv->mode_info.p1pll;
 180         else
 181                 pll = &dev_priv->mode_info.p2pll;
 182
 183         radeon_compute_pll(pll, mode->clock, &sclock,
 184                            &fb_div, &ref_div, &post_div, pll_flags);
 185
 186         if (radeon_is_avivo(dev_priv)) {
 187                 uint32_t ss_cntl;
 188
 189                 if (radeon_crtc->crtc_id == 0) {
 190                         ss_cntl = RADEON_READ(AVIVO_P1PLL_INT_SS_CNTL);
 191                         RADEON_WRITE(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl & ~1);
 192                 } else {
 193                         ss_cntl = RADEON_READ(AVIVO_P2PLL_INT_SS_CNTL);
 194                         RADEON_WRITE(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl & ~1);
 195                 }
 196         }
 197
 198         /* */
 199
 200         atom_parse_cmd_header(dev_priv->mode_info.atom_context, index, &frev, &crev);
 201
 202         switch(frev) {
 203         case 1:
 204                 switch(crev) {
 205                 case 1:
 206                 case 2:
 207                         spc2_ptr = (PIXEL_CLOCK_PARAMETERS_V2*)&spc_param.sPCLKInput;
 208                         spc2_ptr->usPixelClock = cpu_to_le16(sclock);
 209                         spc2_ptr->usRefDiv = cpu_to_le16(ref_div);
 210                         spc2_ptr->usFbDiv = cpu_to_le16(fb_div);
 211                         spc2_ptr->ucPostDiv = post_div;
 212                         spc2_ptr->ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
 213                         spc2_ptr->ucCRTC = radeon_crtc->crtc_id;
 214                         spc2_ptr->ucRefDivSrc = 1;
 215                         break;
 216                 case 3:
 217                         spc3_ptr = (PIXEL_CLOCK_PARAMETERS_V3*)&spc_param.sPCLKInput;
 218                         spc3_ptr->usPixelClock = cpu_to_le16(sclock);
 219                         spc3_ptr->usRefDiv = cpu_to_le16(ref_div);
 220                         spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
 221                         spc3_ptr->ucPostDiv = post_div;
 222                         spc3_ptr->ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
 223                         spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2);
 224
 225                         /* TODO insert output encoder object stuff herre for r600 */
 226                         break;
 227                 default:
 228                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 229                         return;
 230                 }
 231                 break;
 232         default:
 233                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 234                 return;
 235         }
 236
 237         printk("executing set pll\n");
 238         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&spc_param);
 239 }
 240
 241 void atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y)
 242 {
 243         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 244         struct drm_device *dev = crtc->dev;
 245         struct drm_radeon_private *dev_priv = dev->dev_private;
 246         struct radeon_framebuffer *radeon_fb;
 247         struct drm_radeon_gem_object *obj_priv;
 248         uint32_t fb_location, fb_format, fb_pitch_pixels;
 249
 250         if (!crtc->fb)
 251                 return;
 252
 253         radeon_fb = to_radeon_framebuffer(crtc->fb);
 254
 255         obj_priv = radeon_fb->obj->driver_private;
 256
 257         fb_location = obj_priv->bo->offset + dev_priv->fb_location;
 258
 259         switch(crtc->fb->bits_per_pixel) {
 260         case 15:
 261                 fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
 262                 break;
 263         case 16:
 264                 fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
 265                 break;
 266         case 24:
 267         case 32:
 268                 fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
 269                 break;
 270         default:
 271                 DRM_ERROR("Unsupported screen depth %d\n", crtc->fb->bits_per_pixel);
 272                 return;
 273         }
 274
 275         /* TODO tiling */
 276         if (radeon_crtc->crtc_id == 0)
 277                 RADEON_WRITE(AVIVO_D1VGA_CONTROL, 0);
 278         else
 279                 RADEON_WRITE(AVIVO_D2VGA_CONTROL, 0);
 280
 281         RADEON_WRITE(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
 282         RADEON_WRITE(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
 283         RADEON_WRITE(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
 284
 285         RADEON_WRITE(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
 286         RADEON_WRITE(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
 287         RADEON_WRITE(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, x);
 288         RADEON_WRITE(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, y);
 289         RADEON_WRITE(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, x + crtc->mode.hdisplay);
 290         RADEON_WRITE(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, y + crtc->mode.vdisplay);
 291
 292         fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
 293         RADEON_WRITE(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
 294         RADEON_WRITE(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
 295
 296         RADEON_WRITE(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
 297                      crtc->mode.vdisplay);
 298         RADEON_WRITE(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
 299         RADEON_WRITE(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
 300                      (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
 301
 302         if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
 303                 RADEON_WRITE(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
 304                              AVIVO_D1MODE_INTERLEAVE_EN);
 305         else
 306                 RADEON_WRITE(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
 307                              0);
 308 }
 309
 310 void atombios_crtc_mode_set(struct drm_crtc *crtc,
 311                             struct drm_display_mode *mode,
 312                             struct drm_display_mode *adjusted_mode,
 313                             int x, int y)
 314 {
 315         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 316         struct drm_device *dev = crtc->dev;
 317         struct drm_radeon_private *dev_priv = dev->dev_private;
 318         struct drm_encoder *encoder;
 319         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
 320         /* TODO color tiling */
 321
 322         memset(&crtc_timing, 0, sizeof(crtc_timing));
 323
 324         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 325
 326
 327
 328         }
 329
 330         crtc_timing.ucCRTC = radeon_crtc->crtc_id;
 331         crtc_timing.usH_Total = adjusted_mode->crtc_htotal;
 332         crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay;
 333         crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start;
 334         crtc_timing.usH_SyncWidth = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
 335
 336         crtc_timing.usV_Total = adjusted_mode->crtc_vtotal;
 337         crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay;
 338         crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start;
 339         crtc_timing.usV_SyncWidth = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
 340
 341         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 342                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
 343
 344         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 345                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
 346
 347         if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
 348                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC;
 349
 350         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
 351                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE;
 352
 353         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 354                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
 355
 356         if (radeon_is_avivo(dev_priv))
 357                 atombios_crtc_set_base(crtc, x, y);
 358         else
 359                 radeon_crtc_set_base(crtc, x, y);
 360
 361         atombios_crtc_set_pll(crtc, adjusted_mode);
 362
 363         atombios_crtc_set_timing(crtc, &crtc_timing);
 364
 365 }
 366
 367 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
 368                                    struct drm_display_mode *mode,
 369                                    struct drm_display_mode *adjusted_mode)
 370 {
 371         return true;
 372 }
 373
 374
 375 static void atombios_crtc_prepare(struct drm_crtc *crtc)
 376 {
 377         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 378         atombios_lock_crtc(crtc, 1);
 379 }
 380
 381 static void atombios_crtc_commit(struct drm_crtc *crtc)
 382 {
 383         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 384         atombios_lock_crtc(crtc, 0);
 385 }
 386
 387 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
 388         .dpms = atombios_crtc_dpms,
 389         .mode_fixup = atombios_crtc_mode_fixup,
 390         .mode_set = atombios_crtc_mode_set,
 391         .mode_set_base = atombios_crtc_set_base,
 392         .prepare = atombios_crtc_prepare,
 393         .commit = atombios_crtc_commit,
 394 };
 395
 396 void radeon_atombios_init_crtc(struct drm_device *dev,
 397                                struct radeon_crtc *radeon_crtc)
 398 {
 399         if (radeon_crtc->crtc_id == 1)
 400                 radeon_crtc->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
 401         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
 402 }