linux-core/atombios_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon_drv.h"
  29
  30 #include "drm_crtc_helper.h"
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33
  34 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
  35 {
  36         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  37         struct drm_device *dev = crtc->dev;
  38         struct drm_radeon_private *dev_priv = dev->dev_private;
  39         int index = GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
  40         ENABLE_CRTC_PS_ALLOCATION args;
  41
  42         memset(&args, 0, sizeof(args));
  43
  44         args.ucCRTC = radeon_crtc->crtc_id;
  45         args.ucEnable = lock;
  46
  47         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
  48 }
  49
  50 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
  51 {
  52         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  53         struct drm_device *dev = crtc->dev;
  54         struct drm_radeon_private *dev_priv = dev->dev_private;
  55         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
  56         ENABLE_CRTC_PS_ALLOCATION args;
  57
  58         memset(&args, 0, sizeof(args));
  59
  60         args.ucCRTC = radeon_crtc->crtc_id;
  61         args.ucEnable = state;
  62
  63         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
  64 }
  65
  66 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
  67 {
  68         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  69         struct drm_device *dev = crtc->dev;
  70         struct drm_radeon_private *dev_priv = dev->dev_private;
  71         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
  72         ENABLE_CRTC_PS_ALLOCATION args;
  73
  74         memset(&args, 0, sizeof(args));
  75
  76         args.ucCRTC = radeon_crtc->crtc_id;
  77         args.ucEnable = state;
  78
  79         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
  80 }
  81
  82 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
  83 {
  84         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  85         struct drm_device *dev = crtc->dev;
  86         struct drm_radeon_private *dev_priv = dev->dev_private;
  87         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
  88         BLANK_CRTC_PS_ALLOCATION args;
  89
  90         memset(&args, 0, sizeof(args));
  91
  92         args.ucCRTC = radeon_crtc->crtc_id;
  93         args.ucBlanking = state;
  94
  95         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
  96 }
  97
  98 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
  99 {
 100         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 101         struct drm_device *dev = crtc->dev;
 102         struct drm_radeon_private *dev_priv = dev->dev_private;
 103
 104         switch(mode) {
 105         case DRM_MODE_DPMS_ON:
 106         case DRM_MODE_DPMS_STANDBY:
 107         case DRM_MODE_DPMS_SUSPEND:
 108                 if (radeon_is_dce3(dev_priv))
 109                         atombios_enable_crtc_memreq(crtc, 1);
 110                 atombios_enable_crtc(crtc, 1);
 111                 atombios_blank_crtc(crtc, 0);
 112
 113                 radeon_crtc_load_lut(crtc);
 114                 break;
 115         case DRM_MODE_DPMS_OFF:
 116                 atombios_blank_crtc(crtc, 1);
 117                 atombios_enable_crtc(crtc, 0);
 118                 if (radeon_is_dce3(dev_priv))
 119                         atombios_enable_crtc_memreq(crtc, 0);
 120                 break;
 121         }
 122 }
 123
 124 static void
 125 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, SET_CRTC_USING_DTD_TIMING_PARAMETERS *crtc_param)
 126 {
 127         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 128         struct drm_device *dev = crtc->dev;
 129         struct drm_radeon_private *dev_priv = dev->dev_private;
 130         SET_CRTC_USING_DTD_TIMING_PARAMETERS conv_param;
 131         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
 132
 133         conv_param.usH_Size                     = cpu_to_le16(crtc_param->usH_Size);
 134         conv_param.usH_Blanking_Time    = cpu_to_le16(crtc_param->usH_Blanking_Time);
 135         conv_param.usV_Size                     = cpu_to_le16(crtc_param->usV_Size);
 136         conv_param.usV_Blanking_Time    = cpu_to_le16(crtc_param->usV_Blanking_Time);
 137         conv_param.usH_SyncOffset               = cpu_to_le16(crtc_param->usH_SyncOffset);
 138         conv_param.usH_SyncWidth                = cpu_to_le16(crtc_param->usH_SyncWidth);
 139         conv_param.usV_SyncOffset               = cpu_to_le16(crtc_param->usV_SyncOffset);
 140         conv_param.usV_SyncWidth                = cpu_to_le16(crtc_param->usV_SyncWidth);
 141         conv_param.susModeMiscInfo.usAccess = cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
 142         conv_param.ucCRTC                       = crtc_param->ucCRTC;
 143
 144         printk("executing set crtc dtd timing\n");
 145         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&conv_param);
 146 }
 147
 148 void atombios_crtc_set_timing(struct drm_crtc *crtc, SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_param)
 149 {
 150         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 151         struct drm_device *dev = crtc->dev;
 152         struct drm_radeon_private *dev_priv = dev->dev_private;
 153         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION conv_param;
 154         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
 155
 156         conv_param.usH_Total                = cpu_to_le16(crtc_param->usH_Total);
 157         conv_param.usH_Disp                 = cpu_to_le16(crtc_param->usH_Disp);
 158         conv_param.usH_SyncStart            = cpu_to_le16(crtc_param->usH_SyncStart);
 159         conv_param.usH_SyncWidth            = cpu_to_le16(crtc_param->usH_SyncWidth);
 160         conv_param.usV_Total                = cpu_to_le16(crtc_param->usV_Total);
 161         conv_param.usV_Disp                 = cpu_to_le16(crtc_param->usV_Disp);
 162         conv_param.usV_SyncStart            = cpu_to_le16(crtc_param->usV_SyncStart);
 163         conv_param.usV_SyncWidth            = cpu_to_le16(crtc_param->usV_SyncWidth);
 164         conv_param.susModeMiscInfo.usAccess = cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
 165         conv_param.ucCRTC                   = crtc_param->ucCRTC;
 166         conv_param.ucOverscanRight          = crtc_param->ucOverscanRight;
 167         conv_param.ucOverscanLeft           = crtc_param->ucOverscanLeft;
 168         conv_param.ucOverscanBottom         = crtc_param->ucOverscanBottom;
 169         conv_param.ucOverscanTop            = crtc_param->ucOverscanTop;
 170         conv_param.ucReserved               = crtc_param->ucReserved;
 171
 172         printk("executing set crtc timing\n");
 173         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&conv_param);
 174 }
 175
 176 void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 177 {
 178         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 179         struct drm_device *dev = crtc->dev;
 180         struct drm_radeon_private *dev_priv = dev->dev_private;
 181         uint8_t frev, crev;
 182         int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 183         SET_PIXEL_CLOCK_PS_ALLOCATION spc_param;
 184         PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
 185         PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
 186         uint32_t sclock = mode->clock;
 187         uint32_t ref_div = 0, fb_div = 0, post_div = 0;
 188         struct radeon_pll *pll;
 189         int pll_flags = 0;
 190
 191         memset(&spc_param, 0, sizeof(SET_PIXEL_CLOCK_PS_ALLOCATION));
 192
 193         if (!radeon_is_avivo(dev_priv))
 194                 pll_flags |= RADEON_PLL_LEGACY;
 195
 196         if (mode->clock > 200000) /* range limits??? */
 197                 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 198         else
 199                 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 200
 201         if (radeon_crtc->crtc_id == 0)
 202                 pll = &dev_priv->mode_info.p1pll;
 203         else
 204                 pll = &dev_priv->mode_info.p2pll;
 205
 206         radeon_compute_pll(pll, mode->clock, &sclock,
 207                            &fb_div, &ref_div, &post_div, pll_flags);
 208
 209         if (radeon_is_avivo(dev_priv)) {
 210                 uint32_t ss_cntl;
 211
 212                 if (radeon_crtc->crtc_id == 0) {
 213                         ss_cntl = RADEON_READ(AVIVO_P1PLL_INT_SS_CNTL);
 214                         RADEON_WRITE(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl & ~1);
 215                 } else {
 216                         ss_cntl = RADEON_READ(AVIVO_P2PLL_INT_SS_CNTL);
 217                         RADEON_WRITE(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl & ~1);
 218                 }
 219         }
 220
 221         /* */
 222
 223         atom_parse_cmd_header(dev_priv->mode_info.atom_context, index, &frev, &crev);
 224
 225         switch(frev) {
 226         case 1:
 227                 switch(crev) {
 228                 case 1:
 229                 case 2:
 230                         spc2_ptr = (PIXEL_CLOCK_PARAMETERS_V2*)&spc_param.sPCLKInput;
 231                         spc2_ptr->usPixelClock = cpu_to_le16(sclock);
 232                         spc2_ptr->usRefDiv = cpu_to_le16(ref_div);
 233                         spc2_ptr->usFbDiv = cpu_to_le16(fb_div);
 234                         spc2_ptr->ucPostDiv = post_div;
 235                         spc2_ptr->ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
 236                         spc2_ptr->ucCRTC = radeon_crtc->crtc_id;
 237                         spc2_ptr->ucRefDivSrc = 1;
 238                         break;
 239                 case 3:
 240                         spc3_ptr = (PIXEL_CLOCK_PARAMETERS_V3*)&spc_param.sPCLKInput;
 241                         spc3_ptr->usPixelClock = cpu_to_le16(sclock);
 242                         spc3_ptr->usRefDiv = cpu_to_le16(ref_div);
 243                         spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
 244                         spc3_ptr->ucPostDiv = post_div;
 245                         spc3_ptr->ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
 246                         spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2);
 247
 248                         /* TODO insert output encoder object stuff herre for r600 */
 249                         break;
 250                 default:
 251                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 252                         return;
 253                 }
 254                 break;
 255         default:
 256                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 257                 return;
 258         }
 259
 260         printk("executing set pll\n");
 261         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&spc_param);
 262 }
 263
 264 void atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y)
 265 {
 266         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 267         struct drm_device *dev = crtc->dev;
 268         struct drm_radeon_private *dev_priv = dev->dev_private;
 269         struct radeon_framebuffer *radeon_fb;
 270         struct drm_gem_object *obj;
 271         struct drm_radeon_gem_object *obj_priv;
 272         uint32_t fb_location, fb_format, fb_pitch_pixels;
 273
 274         if (!crtc->fb)
 275                 return;
 276
 277         radeon_fb = to_radeon_framebuffer(crtc->fb);
 278
 279         obj = radeon_fb->base.mm_private;
 280         obj_priv = obj->driver_private;
 281
 282         fb_location = obj_priv->bo->offset + dev_priv->fb_location;
 283
 284         switch(crtc->fb->bits_per_pixel) {
 285         case 15:
 286                 fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
 287                 break;
 288         case 16:
 289                 fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
 290                 break;
 291         case 24:
 292         case 32:
 293                 fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
 294                 break;
 295         default:
 296                 DRM_ERROR("Unsupported screen depth %d\n", crtc->fb->bits_per_pixel);
 297                 return;
 298         }
 299
 300         /* TODO tiling */
 301         if (radeon_crtc->crtc_id == 0)
 302                 RADEON_WRITE(AVIVO_D1VGA_CONTROL, 0);
 303         else
 304                 RADEON_WRITE(AVIVO_D2VGA_CONTROL, 0);
 305
 306         RADEON_WRITE(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
 307         RADEON_WRITE(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
 308         RADEON_WRITE(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
 309
 310         RADEON_WRITE(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
 311         RADEON_WRITE(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
 312         RADEON_WRITE(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, x);
 313         RADEON_WRITE(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, y);
 314         RADEON_WRITE(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, x + crtc->mode.hdisplay);
 315         RADEON_WRITE(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, y + crtc->mode.vdisplay);
 316
 317         fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
 318         RADEON_WRITE(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
 319         RADEON_WRITE(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
 320
 321         RADEON_WRITE(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
 322                      crtc->mode.vdisplay);
 323         RADEON_WRITE(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
 324         RADEON_WRITE(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
 325                      (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
 326
 327         if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
 328                 RADEON_WRITE(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
 329                              AVIVO_D1MODE_INTERLEAVE_EN);
 330         else
 331                 RADEON_WRITE(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
 332                              0);
 333 }
 334
 335 void atombios_crtc_mode_set(struct drm_crtc *crtc,
 336                             struct drm_display_mode *mode,
 337                             struct drm_display_mode *adjusted_mode,
 338                             int x, int y)
 339 {
 340         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 341         struct drm_device *dev = crtc->dev;
 342         struct drm_radeon_private *dev_priv = dev->dev_private;
 343         struct drm_encoder *encoder;
 344         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
 345
 346         /* TODO color tiling */
 347         memset(&crtc_timing, 0, sizeof(crtc_timing));
 348
 349         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 350
 351
 352
 353         }
 354
 355         crtc_timing.ucCRTC = radeon_crtc->crtc_id;
 356         crtc_timing.usH_Total = adjusted_mode->crtc_htotal;
 357         crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay;
 358         crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start;
 359         crtc_timing.usH_SyncWidth = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
 360
 361         crtc_timing.usV_Total = adjusted_mode->crtc_vtotal;
 362         crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay;
 363         crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start;
 364         crtc_timing.usV_SyncWidth = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
 365
 366         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 367                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
 368
 369         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 370                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
 371
 372         if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
 373                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC;
 374
 375         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
 376                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE;
 377
 378         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 379                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
 380
 381         atombios_crtc_set_pll(crtc, adjusted_mode);
 382         atombios_crtc_set_timing(crtc, &crtc_timing);
 383
 384         if (radeon_is_avivo(dev_priv))
 385                 atombios_crtc_set_base(crtc, x, y);
 386         else {
 387                 if (radeon_crtc->crtc_id == 0) {
 388                         SET_CRTC_USING_DTD_TIMING_PARAMETERS crtc_dtd_timing;
 389                         memset(&crtc_dtd_timing, 0, sizeof(crtc_dtd_timing));
 390
 391                         /* setup FP shadow regs on R4xx */
 392                         crtc_dtd_timing.ucCRTC = radeon_crtc->crtc_id;
 393                         crtc_dtd_timing.usH_Size = adjusted_mode->crtc_hdisplay;
 394                         crtc_dtd_timing.usV_Size = adjusted_mode->crtc_vdisplay;
 395                         crtc_dtd_timing.usH_Blanking_Time = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hdisplay;
 396                         crtc_dtd_timing.usV_Blanking_Time = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vdisplay;
 397                         crtc_dtd_timing.usH_SyncOffset = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
 398                         crtc_dtd_timing.usV_SyncOffset = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
 399                         crtc_dtd_timing.usH_SyncWidth = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
 400                         crtc_dtd_timing.usV_SyncWidth = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
 401                         //crtc_dtd_timing.ucH_Border = adjusted_mode->crtc_hborder;
 402                         //crtc_dtd_timing.ucV_Border = adjusted_mode->crtc_vborder;
 403
 404                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 405                                 crtc_dtd_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
 406
 407                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 408                                 crtc_dtd_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
 409
 410                         if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
 411                                 crtc_dtd_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC;
 412
 413                         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
 414                                 crtc_dtd_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE;
 415
 416                         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 417                                 crtc_dtd_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
 418
 419                         atombios_set_crtc_dtd_timing(crtc, &crtc_dtd_timing);
 420                 }
 421                 radeon_crtc_set_base(crtc, x, y);
 422         }
 423
 424 }
 425
 426 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
 427                                    struct drm_display_mode *mode,
 428                                    struct drm_display_mode *adjusted_mode)
 429 {
 430         return true;
 431 }
 432
 433
 434 static void atombios_crtc_prepare(struct drm_crtc *crtc)
 435 {
 436         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 437         atombios_lock_crtc(crtc, 1);
 438 }
 439
 440 static void atombios_crtc_commit(struct drm_crtc *crtc)
 441 {
 442         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 443         atombios_lock_crtc(crtc, 0);
 444 }
 445
 446 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
 447         .dpms = atombios_crtc_dpms,
 448         .mode_fixup = atombios_crtc_mode_fixup,
 449         .mode_set = atombios_crtc_mode_set,
 450         .mode_set_base = atombios_crtc_set_base,
 451         .prepare = atombios_crtc_prepare,
 452         .commit = atombios_crtc_commit,
 453 };
 454
 455 void radeon_atombios_init_crtc(struct drm_device *dev,
 456                                struct radeon_crtc *radeon_crtc)
 457 {
 458         if (radeon_crtc->crtc_id == 1)
 459                 radeon_crtc->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
 460         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
 461 }