linux-core/atombios.h

   1 /*
   2  * Copyright 2006-2007 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23
  24 /****************************************************************************/
  25 /*Portion I: Definitions  shared between VBIOS and Driver                   */
  26 /****************************************************************************/
  27
  28
  29 #ifndef _ATOMBIOS_H
  30 #define _ATOMBIOS_H
  31
  32 #define ATOM_VERSION_MAJOR                   0x00020000
  33 #define ATOM_VERSION_MINOR                   0x00000002
  34
  35 #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
  36
  37 /* Endianness should be specified before inclusion,
  38  * default to little endian
  39  */
  40 #ifndef ATOM_BIG_ENDIAN
  41 #error Endian not specified
  42 #endif
  43
  44 #ifdef _H2INC
  45   #ifndef ULONG
  46     typedef unsigned long ULONG;
  47   #endif
  48
  49   #ifndef UCHAR
  50     typedef unsigned char UCHAR;
  51   #endif
  52
  53   #ifndef USHORT
  54     typedef unsigned short USHORT;
  55   #endif
  56 #endif
  57
  58 #define ATOM_DAC_A            0
  59 #define ATOM_DAC_B            1
  60 #define ATOM_EXT_DAC          2
  61
  62 #define ATOM_CRTC1            0
  63 #define ATOM_CRTC2            1
  64
  65 #define ATOM_DIGA             0
  66 #define ATOM_DIGB             1
  67
  68 #define ATOM_PPLL1            0
  69 #define ATOM_PPLL2            1
  70
  71 #define ATOM_SCALER1          0
  72 #define ATOM_SCALER2          1
  73
  74 #define ATOM_SCALER_DISABLE   0
  75 #define ATOM_SCALER_CENTER    1
  76 #define ATOM_SCALER_EXPANSION 2
  77 #define ATOM_SCALER_MULTI_EX  3
  78
  79 #define ATOM_DISABLE          0
  80 #define ATOM_ENABLE           1
  81 #define ATOM_LCD_BLOFF                          (ATOM_DISABLE+2)
  82 #define ATOM_LCD_BLON                           (ATOM_ENABLE+2)
  83 #define ATOM_LCD_BL_BRIGHTNESS_CONTROL          (ATOM_ENABLE+3)
  84 #define ATOM_LCD_SELFTEST_START                                                                 (ATOM_DISABLE+5)
  85 #define ATOM_LCD_SELFTEST_STOP                                                                  (ATOM_ENABLE+5)
  86 #define ATOM_ENCODER_INIT                                         (ATOM_DISABLE+7)
  87
  88 #define ATOM_BLANKING         1
  89 #define ATOM_BLANKING_OFF     0
  90
  91 #define ATOM_CURSOR1          0
  92 #define ATOM_CURSOR2          1
  93
  94 #define ATOM_ICON1            0
  95 #define ATOM_ICON2            1
  96
  97 #define ATOM_CRT1             0
  98 #define ATOM_CRT2             1
  99
 100 #define ATOM_TV_NTSC          1
 101 #define ATOM_TV_NTSCJ         2
 102 #define ATOM_TV_PAL           3
 103 #define ATOM_TV_PALM          4
 104 #define ATOM_TV_PALCN         5
 105 #define ATOM_TV_PALN          6
 106 #define ATOM_TV_PAL60         7
 107 #define ATOM_TV_SECAM         8
 108 #define ATOM_TV_CV            16
 109
 110 #define ATOM_DAC1_PS2         1
 111 #define ATOM_DAC1_CV          2
 112 #define ATOM_DAC1_NTSC        3
 113 #define ATOM_DAC1_PAL         4
 114
 115 #define ATOM_DAC2_PS2         ATOM_DAC1_PS2
 116 #define ATOM_DAC2_CV          ATOM_DAC1_CV
 117 #define ATOM_DAC2_NTSC        ATOM_DAC1_NTSC
 118 #define ATOM_DAC2_PAL         ATOM_DAC1_PAL
 119
 120 #define ATOM_PM_ON            0
 121 #define ATOM_PM_STANDBY       1
 122 #define ATOM_PM_SUSPEND       2
 123 #define ATOM_PM_OFF           3
 124
 125 /* Bit0:{=0:single, =1:dual},
 126    Bit1 {=0:666RGB, =1:888RGB},
 127    Bit2:3:{Grey level}
 128    Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/
 129
 130 #define ATOM_PANEL_MISC_DUAL               0x00000001
 131 #define ATOM_PANEL_MISC_888RGB             0x00000002
 132 #define ATOM_PANEL_MISC_GREY_LEVEL         0x0000000C
 133 #define ATOM_PANEL_MISC_FPDI               0x00000010
 134 #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT   2
 135 #define ATOM_PANEL_MISC_SPATIAL            0x00000020
 136 #define ATOM_PANEL_MISC_TEMPORAL           0x00000040
 137 #define ATOM_PANEL_MISC_API_ENABLED        0x00000080
 138
 139
 140 #define MEMTYPE_DDR1              "DDR1"
 141 #define MEMTYPE_DDR2              "DDR2"
 142 #define MEMTYPE_DDR3              "DDR3"
 143 #define MEMTYPE_DDR4              "DDR4"
 144
 145 #define ASIC_BUS_TYPE_PCI         "PCI"
 146 #define ASIC_BUS_TYPE_AGP         "AGP"
 147 #define ASIC_BUS_TYPE_PCIE        "PCI_EXPRESS"
 148
 149 /* Maximum size of that FireGL flag string */
 150
 151 #define ATOM_FIREGL_FLAG_STRING     "FGL"             //Flag used to enable FireGL Support
 152 #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING  3        //sizeof( ATOM_FIREGL_FLAG_STRING )
 153
 154 #define ATOM_FAKE_DESKTOP_STRING    "DSK"             //Flag used to enable mobile ASIC on Desktop
 155 #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING  ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
 156
 157 #define ATOM_M54T_FLAG_STRING       "M54T"            //Flag used to enable M54T Support
 158 #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING    4        //sizeof( ATOM_M54T_FLAG_STRING )
 159
 160 #define HW_ASSISTED_I2C_STATUS_FAILURE          2
 161 #define HW_ASSISTED_I2C_STATUS_SUCCESS          1
 162
 163 #pragma pack(1)                                       /* BIOS data must use byte aligment */
 164
 165 /*  Define offset to location of ROM header. */
 166
 167 #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER            0x00000048L
 168 #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE                               0x00000002L
 169
 170 #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE    0x94
 171 #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE   20    /* including the terminator 0x0! */
 172 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER           0x002f
 173 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START            0x006e
 174
 175 /* Common header for all ROM Data tables.
 176   Every table pointed  _ATOM_MASTER_DATA_TABLE has this common header.
 177   And the pointer actually points to this header. */
 178
 179 typedef struct _ATOM_COMMON_TABLE_HEADER
 180 {
 181   USHORT usStructureSize;
 182   UCHAR  ucTableFormatRevision;   /*Change it when the Parser is not backward compatible */
 183   UCHAR  ucTableContentRevision;  /*Change it only when the table needs to change but the firmware */
 184                                   /*Image can't be updated, while Driver needs to carry the new table! */
 185 }ATOM_COMMON_TABLE_HEADER;
 186
 187 typedef struct _ATOM_ROM_HEADER
 188 {
 189   ATOM_COMMON_TABLE_HEADER              sHeader;
 190   UCHAR  uaFirmWareSignature[4];    /*Signature to distinguish between Atombios and non-atombios,
 191                                       atombios should init it as "ATOM", don't change the position */
 192   USHORT usBiosRuntimeSegmentAddress;
 193   USHORT usProtectedModeInfoOffset;
 194   USHORT usConfigFilenameOffset;
 195   USHORT usCRC_BlockOffset;
 196   USHORT usBIOS_BootupMessageOffset;
 197   USHORT usInt10Offset;
 198   USHORT usPciBusDevInitCode;
 199   USHORT usIoBaseAddress;
 200   USHORT usSubsystemVendorID;
 201   USHORT usSubsystemID;
 202   USHORT usPCI_InfoOffset;
 203   USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */
 204   USHORT usMasterDataTableOffset;   /*Offset for SW to get all data table offsets, Don't change the position */
 205   UCHAR  ucExtendedFunctionCode;
 206   UCHAR  ucReserved;
 207 }ATOM_ROM_HEADER;
 208
 209 /*==============================Command Table Portion==================================== */
 210
 211 #ifdef  UEFI_BUILD
 212         #define UTEMP   USHORT
 213         #define USHORT  void*
 214 #endif
 215
 216 typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
 217   USHORT ASIC_Init;                              //Function Table, used by various SW components,latest version 1.1
 218   USHORT GetDisplaySurfaceSize;                  //Atomic Table,  Used by Bios when enabling HW ICON
 219   USHORT ASIC_RegistersInit;                     //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
 220   USHORT VRAM_BlockVenderDetection;              //Atomic Table,  used only by Bios
 221   USHORT DIGxEncoderControl;                                                                             //Only used by Bios
 222   USHORT MemoryControllerInit;                   //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
 223   USHORT EnableCRTCMemReq;                       //Function Table,directly used by various SW components,latest version 2.1
 224   USHORT MemoryParamAdjust;                                                                              //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock if needed
 225   USHORT DVOEncoderControl;                      //Function Table,directly used by various SW components,latest version 1.2
 226   USHORT GPIOPinControl;                                                                                                 //Atomic Table,  only used by Bios
 227   USHORT SetEngineClock;                         //Function Table,directly used by various SW components,latest version 1.1
 228   USHORT SetMemoryClock;                         //Function Table,directly used by various SW components,latest version 1.1
 229   USHORT SetPixelClock;                          //Function Table,directly used by various SW components,latest version 1.2
 230   USHORT DynamicClockGating;                     //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
 231   USHORT ResetMemoryDLL;                         //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 232   USHORT ResetMemoryDevice;                      //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 233   USHORT MemoryPLLInit;
 234   USHORT AdjustDisplayPll;                                                                                              //only used by Bios
 235   USHORT AdjustMemoryController;                 //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 236   USHORT EnableASIC_StaticPwrMgt;                //Atomic Table,  only used by Bios
 237   USHORT ASIC_StaticPwrMgtStatusChange;          //Obsolete ,     only used by Bios
 238   USHORT DAC_LoadDetection;                      //Atomic Table,  directly used by various SW components,latest version 1.2
 239   USHORT LVTMAEncoderControl;                    //Atomic Table,directly used by various SW components,latest version 1.3
 240   USHORT LCD1OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
 241   USHORT DAC1EncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
 242   USHORT DAC2EncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
 243   USHORT DVOOutputControl;                       //Atomic Table,  directly used by various SW components,latest version 1.1
 244   USHORT CV1OutputControl;                       //Atomic Table,  directly used by various SW components,latest version 1.1
 245   USHORT GetConditionalGoldenSetting;            //only used by Bios
 246   USHORT TVEncoderControl;                       //Function Table,directly used by various SW components,latest version 1.1
 247   USHORT TMDSAEncoderControl;                    //Atomic Table,  directly used by various SW components,latest version 1.3
 248   USHORT LVDSEncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.3
 249   USHORT TV1OutputControl;                       //Atomic Table,  directly used by various SW components,latest version 1.1
 250   USHORT EnableScaler;                           //Atomic Table,  used only by Bios
 251   USHORT BlankCRTC;                              //Atomic Table,  directly used by various SW components,latest version 1.1
 252   USHORT EnableCRTC;                             //Atomic Table,  directly used by various SW components,latest version 1.1
 253   USHORT GetPixelClock;                          //Atomic Table,  directly used by various SW components,latest version 1.1
 254   USHORT EnableVGA_Render;                       //Function Table,directly used by various SW components,latest version 1.1
 255   USHORT EnableVGA_Access;                       //Obsolete ,     only used by Bios
 256   USHORT SetCRTC_Timing;                         //Atomic Table,  directly used by various SW components,latest version 1.1
 257   USHORT SetCRTC_OverScan;                       //Atomic Table,  used by various SW components,latest version 1.1
 258   USHORT SetCRTC_Replication;                    //Atomic Table,  used only by Bios
 259   USHORT SelectCRTC_Source;                      //Atomic Table,  directly used by various SW components,latest version 1.1
 260   USHORT EnableGraphSurfaces;                    //Atomic Table,  used only by Bios
 261   USHORT UpdateCRTC_DoubleBufferRegisters;
 262   USHORT LUT_AutoFill;                           //Atomic Table,  only used by Bios
 263   USHORT EnableHW_IconCursor;                    //Atomic Table,  only used by Bios
 264   USHORT GetMemoryClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1
 265   USHORT GetEngineClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1
 266   USHORT SetCRTC_UsingDTDTiming;                 //Atomic Table,  directly used by various SW components,latest version 1.1
 267   USHORT ExternalEncoderControl;                 //Atomic Table,  directly used by various SW components,latest version 2.1
 268   USHORT LVTMAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
 269   USHORT VRAM_BlockDetectionByStrap;
 270   USHORT MemoryCleanUp;                          //Atomic Table,  only used by Bios
 271   USHORT ProcessI2cChannelTransaction;           //Function Table,only used by Bios
 272   USHORT WriteOneByteToHWAssistedI2C;            //Function Table,indirectly used by various SW components
 273   USHORT ReadHWAssistedI2CStatus;                //Atomic Table,  indirectly used by various SW components
 274   USHORT SpeedFanControl;                        //Function Table,indirectly used by various SW components,called from ASIC_Init
 275   USHORT PowerConnectorDetection;                //Atomic Table,  directly used by various SW components,latest version 1.1
 276   USHORT MC_Synchronization;                     //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 277   USHORT ComputeMemoryEnginePLL;                 //Atomic Table,  indirectly used by various SW components,called from SetMemory/EngineClock
 278   USHORT MemoryRefreshConversion;                //Atomic Table,  indirectly used by various SW components,called from SetMemory or SetEngineClock
 279   USHORT VRAM_GetCurrentInfoBlock;
 280   USHORT DynamicMemorySettings;                  //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 281   USHORT MemoryTraining;
 282   USHORT EnableSpreadSpectrumOnPPLL;             //Atomic Table,  directly used by various SW components,latest version 1.2
 283   USHORT TMDSAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
 284   USHORT SetVoltage;                             //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
 285   USHORT DAC1OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
 286   USHORT DAC2OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
 287   USHORT SetupHWAssistedI2CStatus;               //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
 288   USHORT ClockSource;                            //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
 289   USHORT MemoryDeviceInit;                       //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 290   USHORT EnableYUV;                              //Atomic Table,  indirectly used by various SW components,called from EnableVGARender
 291   USHORT DIG1EncoderControl;                     //Atomic Table,directly used by various SW components,latest version 1.1
 292   USHORT DIG2EncoderControl;                     //Atomic Table,directly used by various SW components,latest version 1.1
 293   USHORT DIG1TransmitterControl;                 //Atomic Table,directly used by various SW components,latest version 1.1
 294   USHORT DIG2TransmitterControl;                       //Atomic Table,directly used by various SW components,latest version 1.1
 295   USHORT ProcessAuxChannelTransaction;                                   //Function Table,only used by Bios
 296   USHORT DPEncoderService;                                                                                       //Function Table,only used by Bios
 297 }ATOM_MASTER_LIST_OF_COMMAND_TABLES;
 298
 299 #define ReadEDIDFromHWAssistedI2C                ProcessI2cChannelTransaction
 300
 301 #define UNIPHYTransmitterControl                                                     DIG1TransmitterControl
 302 #define LVTMATransmitterControl                                                      DIG2TransmitterControl
 303 #define SetCRTC_DPM_State                                    GetConditionalGoldenSetting
 304
 305 typedef struct _ATOM_MASTER_COMMAND_TABLE
 306 {
 307   ATOM_COMMON_TABLE_HEADER           sHeader;
 308   ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
 309 }ATOM_MASTER_COMMAND_TABLE;
 310
 311 typedef struct _ATOM_TABLE_ATTRIBUTE
 312 {
 313 #if ATOM_BIG_ENDIAN
 314   USHORT  UpdatedByUtility:1;         //[15]=Table updated by utility flag
 315   USHORT  PS_SizeInBytes:7;           //[14:8]=Size of parameter space in Bytes (multiple of a dword),
 316   USHORT  WS_SizeInBytes:8;           //[7:0]=Size of workspace in Bytes (in multiple of a dword),
 317 #else
 318   USHORT  WS_SizeInBytes:8;           //[7:0]=Size of workspace in Bytes (in multiple of a dword),
 319   USHORT  PS_SizeInBytes:7;           //[14:8]=Size of parameter space in Bytes (multiple of a dword),
 320   USHORT  UpdatedByUtility:1;         //[15]=Table updated by utility flag
 321 #endif
 322 }ATOM_TABLE_ATTRIBUTE;
 323
 324 typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS
 325 {
 326   ATOM_TABLE_ATTRIBUTE sbfAccess;
 327   USHORT               susAccess;
 328 }ATOM_TABLE_ATTRIBUTE_ACCESS;
 329
 330 // Common header for all command tables.
 331 //Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header.
 332 //And the pointer actually points to this header.
 333
 334 typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
 335 {
 336   ATOM_COMMON_TABLE_HEADER CommonHeader;
 337   ATOM_TABLE_ATTRIBUTE     TableAttribute;
 338 }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
 339
 340
 341 typedef struct _ASIC_INIT_PARAMETERS
 342 {
 343   ULONG ulDefaultEngineClock;         //In 10Khz unit
 344   ULONG ulDefaultMemoryClock;         //In 10Khz unit
 345 }ASIC_INIT_PARAMETERS;
 346
 347 #define COMPUTE_MEMORY_PLL_PARAM        1
 348 #define COMPUTE_ENGINE_PLL_PARAM        2
 349
 350 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
 351 {
 352   ULONG   ulClock;        //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
 353   UCHAR   ucAction;       //0:reserved //1:Memory //2:Engine
 354   UCHAR   ucReserved;     //may expand to return larger Fbdiv later
 355   UCHAR   ucFbDiv;        //return value
 356   UCHAR   ucPostDiv;      //return value
 357 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
 358
 359 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
 360 {
 361   ULONG   ulClock;        //When return, [23:0] return real clock
 362   UCHAR   ucAction;       //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
 363   USHORT  usFbDiv;                  //return Feedback value to be written to register
 364   UCHAR   ucPostDiv;      //return post div to be written to register
 365 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
 366 #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
 367
 368
 369 #define SET_CLOCK_FREQ_MASK                     0x00FFFFFF  //Clock change tables only take bit [23:0] as the requested clock value
 370 #define USE_NON_BUS_CLOCK_MASK                  0x01000000  //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
 371 #define USE_MEMORY_SELF_REFRESH_MASK            0x02000000      //Only applicable to memory clock change, when set, using memory self refresh during clock transition
 372 #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04000000  //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
 373 #define FIRST_TIME_CHANGE_CLOCK                                                                 0x08000000      //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
 374 #define SKIP_SW_PROGRAM_PLL                                                                                     0x10000000      //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
 375 #define USE_SS_ENABLED_PIXEL_CLOCK  USE_NON_BUS_CLOCK_MASK
 376
 377 #define b3USE_NON_BUS_CLOCK_MASK                  0x01       //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
 378 #define b3USE_MEMORY_SELF_REFRESH                 0x02       //Only applicable to memory clock change, when set, using memory self refresh during clock transition
 379 #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04       //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
 380 #define b3FIRST_TIME_CHANGE_CLOCK                                                                       0x08       //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
 381 #define b3SKIP_SW_PROGRAM_PLL                                                                                   0x10                     //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
 382
 383 typedef struct _SET_ENGINE_CLOCK_PARAMETERS
 384 {
 385   ULONG ulTargetEngineClock;          //In 10Khz unit
 386 }SET_ENGINE_CLOCK_PARAMETERS;
 387
 388 typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
 389 {
 390   ULONG ulTargetEngineClock;          //In 10Khz unit
 391   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
 392 }SET_ENGINE_CLOCK_PS_ALLOCATION;
 393
 394
 395 typedef struct _SET_MEMORY_CLOCK_PARAMETERS
 396 {
 397   ULONG ulTargetMemoryClock;          //In 10Khz unit
 398 }SET_MEMORY_CLOCK_PARAMETERS;
 399
 400 typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION
 401 {
 402   ULONG ulTargetMemoryClock;          //In 10Khz unit
 403   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
 404 }SET_MEMORY_CLOCK_PS_ALLOCATION;
 405
 406 typedef struct _ASIC_INIT_PS_ALLOCATION
 407 {
 408   ASIC_INIT_PARAMETERS sASICInitClocks;
 409   SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
 410 }ASIC_INIT_PS_ALLOCATION;
 411
 412
 413 typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS
 414 {
 415   UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
 416   UCHAR ucPadding[3];
 417 }DYNAMIC_CLOCK_GATING_PARAMETERS;
 418 #define  DYNAMIC_CLOCK_GATING_PS_ALLOCATION  DYNAMIC_CLOCK_GATING_PARAMETERS
 419
 420
 421 typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
 422 {
 423   UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
 424   UCHAR ucPadding[3];
 425 }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
 426 #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION  ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
 427
 428
 429 typedef struct _DAC_LOAD_DETECTION_PARAMETERS
 430 {
 431   USHORT usDeviceID;                  //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
 432   UCHAR  ucDacType;                   //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
 433   UCHAR  ucMisc;                                                                                        //Valid only when table revision =1.3 and above
 434 }DAC_LOAD_DETECTION_PARAMETERS;
 435
 436 // DAC_LOAD_DETECTION_PARAMETERS.ucMisc
 437 #define DAC_LOAD_MISC_YPrPb                                             0x01
 438
 439
 440 typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION
 441 {
 442   DAC_LOAD_DETECTION_PARAMETERS            sDacload;
 443   ULONG                                    Reserved[2];// Don't set this one, allocation for EXT DAC
 444 }DAC_LOAD_DETECTION_PS_ALLOCATION;
 445
 446
 447 typedef struct _DAC_ENCODER_CONTROL_PARAMETERS
 448 {
 449   USHORT usPixelClock;                // in 10KHz; for bios convenient
 450   UCHAR  ucDacStandard;               // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
 451   UCHAR  ucAction;                    // 0: turn off encoder
 452                                       // 1: setup and turn on encoder
 453                                       // 7: ATOM_ENCODER_INIT Initialize DAC
 454 }DAC_ENCODER_CONTROL_PARAMETERS;
 455
 456 #define DAC_ENCODER_CONTROL_PS_ALLOCATION  DAC_ENCODER_CONTROL_PARAMETERS
 457
 458 typedef struct _TV_ENCODER_CONTROL_PARAMETERS
 459 {
 460   USHORT usPixelClock;                // in 10KHz; for bios convenient
 461   UCHAR  ucTvStandard;                // See definition "ATOM_TV_NTSC ..."
 462   UCHAR  ucAction;                    // 0: turn off encoder
 463                                       // 1: setup and turn on encoder
 464 }TV_ENCODER_CONTROL_PARAMETERS;
 465
 466 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
 467 {
 468   USHORT usPixelClock;          // in 10KHz; for bios convenient
 469   UCHAR  ucConfig;
 470                             // [2] Link Select:
 471                             // =0: PHY linkA if bfLane<3
 472                             // =1: PHY linkB if bfLanes<3
 473                             // =0: PHY linkA+B if bfLanes=3
 474                             // [3] Transmitter Sel
 475                             // =0: UNIPHY or PCIEPHY
 476                             // =1: LVTMA
 477   UCHAR ucAction;           // =0: turn off encoder
 478                             // =1: turn on encoder
 479   UCHAR ucEncoderMode;
 480                             // =0: DP   encoder
 481                             // =1: LVDS encoder
 482                             // =2: DVI  encoder
 483                             // =3: HDMI encoder
 484                             // =4: SDVO encoder
 485   UCHAR ucLaneNum;          // how many lanes to enable
 486   UCHAR ucReserved[2];
 487 }DIG_ENCODER_CONTROL_PARAMETERS;
 488 #define DIG_ENCODER_CONTROL_PS_ALLOCATION                         DIG_ENCODER_CONTROL_PARAMETERS
 489 #define EXTERNAL_ENCODER_CONTROL_PARAMETER                      DIG_ENCODER_CONTROL_PARAMETERS
 490 #define EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION  DIG_ENCODER_CONTROL_PS_ALLOCATION
 491
 492 //ucConfig
 493 #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK                             0x01
 494 #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ          0x00
 495 #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ          0x01
 496 #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK                                 0x04
 497 #define ATOM_ENCODER_CONFIG_LINKA                                                                 0x00
 498 #define ATOM_ENCODER_CONFIG_LINKB                                                                 0x04
 499 #define ATOM_ENCODER_CONFIG_LINKA_B                                                       ATOM_TRANSMITTER_CONFIG_LINKA
 500 #define ATOM_ENCODER_CONFIG_LINKB_A                                                       ATOM_ENCODER_CONFIG_LINKB
 501 #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK        0x08
 502 #define ATOM_ENCODER_CONFIG_UNIPHY                                                        0x00
 503 #define ATOM_ENCODER_CONFIG_LVTMA                                                                 0x08
 504 #define ATOM_ENCODER_CONFIG_TRANSMITTER1                                  0x00
 505 #define ATOM_ENCODER_CONFIG_TRANSMITTER2                                  0x08
 506 #define ATOM_ENCODER_CONFIG_DIGB                                                                  0x80                  // VBIOS Internal use, outside SW should set this bit=0
 507 // ucAction
 508 // ATOM_ENABLE:  Enable Encoder
 509 // ATOM_DISABLE: Disable Encoder
 510
 511 //ucEncoderMode
 512 #define ATOM_ENCODER_MODE_DP                                                                                    0
 513 #define ATOM_ENCODER_MODE_LVDS                                                                          1
 514 #define ATOM_ENCODER_MODE_DVI                                                                                   2
 515 #define ATOM_ENCODER_MODE_HDMI                                                                          3
 516 #define ATOM_ENCODER_MODE_SDVO                                                                          4
 517 #define ATOM_ENCODER_MODE_TV                                                                                    13
 518 #define ATOM_ENCODER_MODE_CV                                                                                    14
 519 #define ATOM_ENCODER_MODE_CRT                                                                                   15
 520
 521 typedef struct _ATOM_DP_VS_MODE
 522 {
 523   UCHAR ucLaneSel;
 524   UCHAR ucLaneSet;
 525 }ATOM_DP_VS_MODE;
 526
 527 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
 528 {
 529         union
 530         {
 531   USHORT usPixelClock;          // in 10KHz; for bios convenient
 532         USHORT usInitInfo;                      // when init uniphy,lower 8bit is used for connector type defined in objectid.h
 533   ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
 534         };
 535   UCHAR ucConfig;
 536                                                                                                         // [0]=0: 4 lane Link,
 537                                                                                                         //    =1: 8 lane Link ( Dual Links TMDS )
 538                           // [1]=0: InCoherent mode
 539                                                                                                         //    =1: Coherent Mode
 540                                                                                                         // [2] Link Select:
 541                                                                                                 // =0: PHY linkA   if bfLane<3
 542                                                                                                         // =1: PHY linkB   if bfLanes<3
 543                                                                                                 // =0: PHY linkA+B if bfLanes=3
 544                           // [5:4]PCIE lane Sel
 545                           // =0: lane 0~3 or 0~7
 546                           // =1: lane 4~7
 547                           // =2: lane 8~11 or 8~15
 548                           // =3: lane 12~15
 549         UCHAR ucAction;                           // =0: turn off encoder
 550                                 // =1: turn on encoder
 551   UCHAR ucReserved[4];
 552 }DIG_TRANSMITTER_CONTROL_PARAMETERS;
 553
 554 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION           DIG_TRANSMITTER_CONTROL_PARAMETERS
 555
 556 //ucInitInfo
 557 #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK  0x00ff
 558
 559 //ucConfig
 560 #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK                      0x01
 561 #define ATOM_TRANSMITTER_CONFIG_COHERENT                                0x02
 562 #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK           0x04
 563 #define ATOM_TRANSMITTER_CONFIG_LINKA                                           0x00
 564 #define ATOM_TRANSMITTER_CONFIG_LINKB                                           0x04
 565 #define ATOM_TRANSMITTER_CONFIG_LINKA_B                                 0x00
 566 #define ATOM_TRANSMITTER_CONFIG_LINKB_A                                 0x04
 567
 568 #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK        0x08                    // only used when ATOM_TRANSMITTER_ACTION_ENABLE
 569 #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER            0x00                            // only used when ATOM_TRANSMITTER_ACTION_ENABLE
 570 #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER            0x08                            // only used when ATOM_TRANSMITTER_ACTION_ENABLE
 571
 572 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK                     0x30
 573 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL                     0x00
 574 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE                     0x20
 575 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN           0x30
 576 #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK           0xc0
 577 #define ATOM_TRANSMITTER_CONFIG_LANE_0_3                                0x00
 578 #define ATOM_TRANSMITTER_CONFIG_LANE_0_7                                0x00
 579 #define ATOM_TRANSMITTER_CONFIG_LANE_4_7                                0x40
 580 #define ATOM_TRANSMITTER_CONFIG_LANE_8_11                               0x80
 581 #define ATOM_TRANSMITTER_CONFIG_LANE_8_15                               0x80
 582 #define ATOM_TRANSMITTER_CONFIG_LANE_12_15                      0xc0
 583
 584 //ucAction
 585 #define ATOM_TRANSMITTER_ACTION_DISABLE                                        0
 586 #define ATOM_TRANSMITTER_ACTION_ENABLE                                         1
 587 #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF                                      2
 588 #define ATOM_TRANSMITTER_ACTION_LCD_BLON                                       3
 589 #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL  4
 590 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START               5
 591 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP                        6
 592 #define ATOM_TRANSMITTER_ACTION_INIT                                                   7
 593 #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT         8
 594 #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT                  9
 595 #define ATOM_TRANSMITTER_ACTION_SETUP                                                  10
 596 #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH           11
 597
 598 /****************************Device Output Control Command Table Definitions**********************/
 599 typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 600 {
 601   UCHAR  ucAction;                    // Possible input:ATOM_ENABLE||ATOMDISABLE
 602                                       // When the display is LCD, in addition to above:
 603                                       // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||
 604                                       // ATOM_LCD_SELFTEST_STOP
 605
 606   UCHAR  aucPadding[3];               // padding to DWORD aligned
 607 }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
 608
 609 #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 610
 611
 612 #define CRT1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 613 #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
 614
 615 #define CRT2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 616 #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
 617
 618 #define CV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 619 #define CV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
 620
 621 #define TV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 622 #define TV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
 623
 624 #define DFP1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 625 #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
 626
 627 #define DFP2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 628 #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
 629
 630 #define LCD1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 631 #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
 632
 633 #define DVO_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 634 #define DVO_OUTPUT_CONTROL_PS_ALLOCATION   DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
 635 #define DVO_OUTPUT_CONTROL_PARAMETERS_V3         DIG_TRANSMITTER_CONTROL_PARAMETERS
 636
 637 /**************************************************************************/
 638 typedef struct _BLANK_CRTC_PARAMETERS
 639 {
 640   UCHAR  ucCRTC;                        // ATOM_CRTC1 or ATOM_CRTC2
 641   UCHAR  ucBlanking;                  // ATOM_BLANKING or ATOM_BLANKINGOFF
 642   USHORT usBlackColorRCr;
 643   USHORT usBlackColorGY;
 644   USHORT usBlackColorBCb;
 645 }BLANK_CRTC_PARAMETERS;
 646 #define BLANK_CRTC_PS_ALLOCATION    BLANK_CRTC_PARAMETERS
 647
 648
 649 typedef struct _ENABLE_CRTC_PARAMETERS
 650 {
 651   UCHAR ucCRTC;                           // ATOM_CRTC1 or ATOM_CRTC2
 652   UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
 653   UCHAR ucPadding[2];
 654 }ENABLE_CRTC_PARAMETERS;
 655 #define ENABLE_CRTC_PS_ALLOCATION   ENABLE_CRTC_PARAMETERS
 656
 657
 658 typedef struct _SET_CRTC_OVERSCAN_PARAMETERS
 659 {
 660   USHORT usOverscanRight;             // right
 661   USHORT usOverscanLeft;              // left
 662   USHORT usOverscanBottom;            // bottom
 663   USHORT usOverscanTop;               // top
 664   UCHAR  ucCRTC;                      // ATOM_CRTC1 or ATOM_CRTC2
 665   UCHAR  ucPadding[3];
 666 }SET_CRTC_OVERSCAN_PARAMETERS;
 667 #define SET_CRTC_OVERSCAN_PS_ALLOCATION  SET_CRTC_OVERSCAN_PARAMETERS
 668
 669
 670 typedef struct _SET_CRTC_REPLICATION_PARAMETERS
 671 {
 672   UCHAR ucH_Replication;              // horizontal replication
 673   UCHAR ucV_Replication;              // vertical replication
 674   UCHAR usCRTC;                       // ATOM_CRTC1 or ATOM_CRTC2
 675   UCHAR ucPadding;
 676 }SET_CRTC_REPLICATION_PARAMETERS;
 677 #define SET_CRTC_REPLICATION_PS_ALLOCATION  SET_CRTC_REPLICATION_PARAMETERS
 678
 679
 680 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS
 681 {
 682   UCHAR ucCRTC;                           // ATOM_CRTC1 or ATOM_CRTC2
 683   UCHAR ucDevice;                     // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
 684   UCHAR ucPadding[2];
 685 }SELECT_CRTC_SOURCE_PARAMETERS;
 686 #define SELECT_CRTC_SOURCE_PS_ALLOCATION  SELECT_CRTC_SOURCE_PARAMETERS
 687
 688 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2
 689 {
 690   UCHAR ucCRTC;                           // ATOM_CRTC1 or ATOM_CRTC2
 691   UCHAR ucEncoderID;                  // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
 692   UCHAR ucEncodeMode;                                                                   // Encoding mode, only valid when using DIG1/DIG2/DVO
 693   UCHAR ucPadding;
 694 }SELECT_CRTC_SOURCE_PARAMETERS_V2;
 695
 696 //ucEncoderID
 697 //#define ASIC_INT_DAC1_ENCODER_ID                                              0x00
 698 //#define ASIC_INT_TV_ENCODER_ID                                                                        0x02
 699 //#define ASIC_INT_DIG1_ENCODER_ID                                                              0x03
 700 //#define ASIC_INT_DAC2_ENCODER_ID                                                              0x04
 701 //#define ASIC_EXT_TV_ENCODER_ID                                                                        0x06
 702 //#define ASIC_INT_DVO_ENCODER_ID                                                                       0x07
 703 //#define ASIC_INT_DIG2_ENCODER_ID                                                              0x09
 704 //#define ASIC_EXT_DIG_ENCODER_ID                                                                       0x05
 705
 706 //ucEncodeMode
 707 //#define ATOM_ENCODER_MODE_DP                                                                          0
 708 //#define ATOM_ENCODER_MODE_LVDS                                                                        1
 709 //#define ATOM_ENCODER_MODE_DVI                                                                         2
 710 //#define ATOM_ENCODER_MODE_HDMI                                                                        3
 711 //#define ATOM_ENCODER_MODE_SDVO                                                                        4
 712 //#define ATOM_ENCODER_MODE_TV                                                                          13
 713 //#define ATOM_ENCODER_MODE_CV                                                                          14
 714 //#define ATOM_ENCODER_MODE_CRT                                                                         15
 715
 716 //Major revision=1., Minor revision=1
 717 typedef struct _PIXEL_CLOCK_PARAMETERS
 718 {
 719   USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
 720                                       // 0 means disable PPLL
 721   USHORT usRefDiv;                    // Reference divider
 722   USHORT usFbDiv;                     // feedback divider
 723   UCHAR  ucPostDiv;                   // post divider
 724   UCHAR  ucFracFbDiv;                 // fractional feedback divider
 725   UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
 726   UCHAR  ucRefDivSrc;                 // ATOM_PJITTER or ATO_NONPJITTER
 727   UCHAR  ucCRTC;                      // Which CRTC uses this Ppll
 728   UCHAR  ucPadding;
 729 }PIXEL_CLOCK_PARAMETERS;
 730
 731
 732 //Major revision=1., Minor revision=2, add ucMiscIfno
 733 //ucMiscInfo:
 734 #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
 735 #define MISC_DEVICE_INDEX_MASK        0xF0
 736 #define MISC_DEVICE_INDEX_SHIFT       4
 737
 738 typedef struct _PIXEL_CLOCK_PARAMETERS_V2
 739 {
 740   USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
 741                                       // 0 means disable PPLL
 742   USHORT usRefDiv;                    // Reference divider
 743   USHORT usFbDiv;                     // feedback divider
 744   UCHAR  ucPostDiv;                   // post divider
 745   UCHAR  ucFracFbDiv;                 // fractional feedback divider
 746   UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
 747   UCHAR  ucRefDivSrc;                 // ATOM_PJITTER or ATO_NONPJITTER
 748   UCHAR  ucCRTC;                      // Which CRTC uses this Ppll
 749   UCHAR  ucMiscInfo;                  // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
 750 }PIXEL_CLOCK_PARAMETERS_V2;
 751
 752 //Major revision=1., Minor revision=3, structure/definition change
 753 //ucEncoderMode:
 754 //ATOM_ENCODER_MODE_DP
 755 //ATOM_ENOCDER_MODE_LVDS
 756 //ATOM_ENOCDER_MODE_DVI
 757 //ATOM_ENOCDER_MODE_HDMI
 758 //ATOM_ENOCDER_MODE_SDVO
 759 //ATOM_ENCODER_MODE_TV                                                                          13
 760 //ATOM_ENCODER_MODE_CV                                                                          14
 761 //ATOM_ENCODER_MODE_CRT                                                                         15
 762
 763 //ucDVOConfig
 764 //#define DVO_ENCODER_CONFIG_RATE_SEL                                                   0x01
 765 //#define DVO_ENCODER_CONFIG_DDR_SPEED                                          0x00
 766 //#define DVO_ENCODER_CONFIG_SDR_SPEED                                          0x01
 767 //#define DVO_ENCODER_CONFIG_OUTPUT_SEL                                         0x0c
 768 //#define DVO_ENCODER_CONFIG_LOW12BIT                                                   0x00
 769 //#define DVO_ENCODER_CONFIG_UPPER12BIT                                         0x04
 770 //#define DVO_ENCODER_CONFIG_24BIT                                                              0x08
 771
 772 //ucMiscInfo: also changed, see below
 773 #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL                                                0x01
 774 #define PIXEL_CLOCK_MISC_VGA_MODE                                                                               0x02
 775 #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK                                                  0x04
 776 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1                                                 0x00
 777 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2                                                 0x04
 778 #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK                 0x08
 779
 780 typedef struct _PIXEL_CLOCK_PARAMETERS_V3
 781 {
 782   USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
 783                                       // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
 784   USHORT usRefDiv;                    // Reference divider
 785   USHORT usFbDiv;                     // feedback divider
 786   UCHAR  ucPostDiv;                   // post divider
 787   UCHAR  ucFracFbDiv;                 // fractional feedback divider
 788   UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
 789   UCHAR  ucTransmitterId;             // graphic encoder id defined in objectId.h
 790         union
 791         {
 792   UCHAR  ucEncoderMode;               // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
 793         UCHAR  ucDVOConfig;                                                                     // when use DVO, need to know SDR/DDR, 12bit or 24bit
 794         };
 795   UCHAR  ucMiscInfo;                  // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
 796                                       // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
 797 }PIXEL_CLOCK_PARAMETERS_V3;
 798
 799 #define PIXEL_CLOCK_PARAMETERS_LAST                     PIXEL_CLOCK_PARAMETERS_V2
 800 #define GET_PIXEL_CLOCK_PS_ALLOCATION           PIXEL_CLOCK_PARAMETERS_LAST
 801
 802 typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
 803 {
 804         USHORT usPixelClock;
 805         UCHAR ucTransmitterID;
 806         UCHAR ucEncodeMode;
 807         union
 808         {
 809                 UCHAR ucDVOConfig;                                                                      //if DVO, need passing link rate and output 12bitlow or 24bit
 810                 UCHAR ucConfig;                                                                                 //if none DVO, not defined yet
 811         };
 812         UCHAR ucReserved[3];
 813 }ADJUST_DISPLAY_PLL_PARAMETERS;
 814
 815 #define ADJUST_DISPLAY_CONFIG_SS_ENABLE       0x10
 816
 817 #define ADJUST_DISPLAY_PLL_PS_ALLOCATION                        ADJUST_DISPLAY_PLL_PARAMETERS
 818
 819 typedef struct _ENABLE_YUV_PARAMETERS
 820 {
 821   UCHAR ucEnable;                     // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
 822   UCHAR ucCRTC;                       // Which CRTC needs this YUV or RGB format
 823   UCHAR ucPadding[2];
 824 }ENABLE_YUV_PARAMETERS;
 825 #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
 826
 827 typedef struct _GET_MEMORY_CLOCK_PARAMETERS
 828 {
 829   ULONG ulReturnMemoryClock;          // current memory speed in 10KHz unit
 830 } GET_MEMORY_CLOCK_PARAMETERS;
 831 #define GET_MEMORY_CLOCK_PS_ALLOCATION  GET_MEMORY_CLOCK_PARAMETERS
 832
 833
 834 typedef struct _GET_ENGINE_CLOCK_PARAMETERS
 835 {
 836   ULONG ulReturnEngineClock;          // current engine speed in 10KHz unit
 837 } GET_ENGINE_CLOCK_PARAMETERS;
 838 #define GET_ENGINE_CLOCK_PS_ALLOCATION  GET_ENGINE_CLOCK_PARAMETERS
 839
 840
 841 //Maxium 8 bytes,the data read in will be placed in the parameter space.
 842 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
 843 typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
 844 {
 845   USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
 846   USHORT    usVRAMAddress;      //Adress in Frame Buffer where to pace raw EDID
 847   USHORT    usStatus;           //When use output: lower byte EDID checksum, high byte hardware status
 848                                 //WHen use input:  lower byte as 'byte to read':currently limited to 128byte or 1byte
 849   UCHAR     ucSlaveAddr;        //Read from which slave
 850   UCHAR     ucLineNumber;       //Read from which HW assisted line
 851 }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
 852 #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION  READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
 853
 854
 855 #define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE                  0
 856 #define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES              1
 857 #define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK       2
 858 #define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK  3
 859 #define  ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK       4
 860
 861 typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
 862 {
 863   USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
 864   USHORT    usByteOffset;       //Write to which byte
 865                                 //Upper portion of usByteOffset is Format of data
 866                                 //1bytePS+offsetPS
 867                                 //2bytesPS+offsetPS
 868                                 //blockID+offsetPS
 869                                 //blockID+offsetID
 870                                 //blockID+counterID+offsetID
 871   UCHAR     ucData;             //PS data1
 872   UCHAR     ucStatus;           //Status byte 1=success, 2=failure, Also is used as PS data2
 873   UCHAR     ucSlaveAddr;        //Write to which slave
 874   UCHAR     ucLineNumber;       //Write from which HW assisted line
 875 }WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
 876
 877 #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION  WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
 878
 879 typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS
 880 {
 881   USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
 882   UCHAR     ucSlaveAddr;        //Write to which slave
 883   UCHAR     ucLineNumber;       //Write from which HW assisted line
 884 }SET_UP_HW_I2C_DATA_PARAMETERS;
 885
 886
 887 /**************************************************************************/
 888 #define SPEED_FAN_CONTROL_PS_ALLOCATION   WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
 889
 890 typedef struct  _POWER_CONNECTOR_DETECTION_PARAMETERS
 891 {
 892   UCHAR   ucPowerConnectorStatus;      //Used for return value 0: detected, 1:not detected
 893         UCHAR   ucPwrBehaviorId;
 894         USHORT  usPwrBudget;                                                             //how much power currently boot to in unit of watt
 895 }POWER_CONNECTOR_DETECTION_PARAMETERS;
 896
 897 typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION
 898 {
 899   UCHAR   ucPowerConnectorStatus;      //Used for return value 0: detected, 1:not detected
 900         UCHAR   ucReserved;
 901         USHORT  usPwrBudget;                                                             //how much power currently boot to in unit of watt
 902   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION    sReserved;
 903 }POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
 904
 905 /****************************LVDS SS Command Table Definitions**********************/
 906 typedef struct  _ENABLE_LVDS_SS_PARAMETERS
 907 {
 908   USHORT  usSpreadSpectrumPercentage;
 909   UCHAR   ucSpreadSpectrumType;           //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
 910   UCHAR   ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
 911   UCHAR   ucEnable;                       //ATOM_ENABLE or ATOM_DISABLE
 912   UCHAR   ucPadding[3];
 913 }ENABLE_LVDS_SS_PARAMETERS;
 914
 915 //ucTableFormatRevision=1,ucTableContentRevision=2
 916 typedef struct  _ENABLE_LVDS_SS_PARAMETERS_V2
 917 {
 918   USHORT  usSpreadSpectrumPercentage;
 919   UCHAR   ucSpreadSpectrumType;           //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
 920   UCHAR   ucSpreadSpectrumStep;           //
 921   UCHAR   ucEnable;                       //ATOM_ENABLE or ATOM_DISABLE
 922   UCHAR   ucSpreadSpectrumDelay;
 923   UCHAR   ucSpreadSpectrumRange;
 924   UCHAR   ucPadding;
 925 }ENABLE_LVDS_SS_PARAMETERS_V2;
 926
 927 //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
 928 typedef struct  _ENABLE_SPREAD_SPECTRUM_ON_PPLL
 929 {
 930   USHORT  usSpreadSpectrumPercentage;
 931   UCHAR   ucSpreadSpectrumType;           // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
 932   UCHAR   ucSpreadSpectrumStep;           //
 933   UCHAR   ucEnable;                       // ATOM_ENABLE or ATOM_DISABLE
 934   UCHAR   ucSpreadSpectrumDelay;
 935   UCHAR   ucSpreadSpectrumRange;
 936   UCHAR   ucPpll;                                                                                                 // ATOM_PPLL1/ATOM_PPLL2
 937 }ENABLE_SPREAD_SPECTRUM_ON_PPLL;
 938
 939 #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION  ENABLE_SPREAD_SPECTRUM_ON_PPLL
 940
 941 /**************************************************************************/
 942
 943 typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION
 944 {
 945   PIXEL_CLOCK_PARAMETERS sPCLKInput;
 946   ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion
 947 }SET_PIXEL_CLOCK_PS_ALLOCATION;
 948
 949 #define ENABLE_VGA_RENDER_PS_ALLOCATION   SET_PIXEL_CLOCK_PS_ALLOCATION
 950
 951 typedef struct  _MEMORY_TRAINING_PARAMETERS
 952 {
 953   ULONG ulTargetMemoryClock;          //In 10Khz unit
 954 }MEMORY_TRAINING_PARAMETERS;
 955 #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
 956
 957
 958
 959 /****************************LVDS and other encoder command table definitions **********************/
 960 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS
 961 {
 962   USHORT usPixelClock;  // in 10KHz; for bios convenient
 963   UCHAR  ucMisc;        // bit0=0: Enable single link
 964                         //     =1: Enable dual link
 965                         // Bit1=0: 666RGB
 966                         //     =1: 888RGB
 967   UCHAR  ucAction;      // 0: turn off encoder
 968                         // 1: setup and turn on encoder
 969 }LVDS_ENCODER_CONTROL_PARAMETERS;
 970
 971 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION  LVDS_ENCODER_CONTROL_PARAMETERS
 972
 973 #define TMDS1_ENCODER_CONTROL_PARAMETERS    LVDS_ENCODER_CONTROL_PARAMETERS
 974 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
 975
 976 #define TMDS2_ENCODER_CONTROL_PARAMETERS    TMDS1_ENCODER_CONTROL_PARAMETERS
 977 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
 978
 979 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
 980 {
 981   UCHAR    ucEnable;            // Enable or Disable External TMDS encoder
 982   UCHAR    ucMisc;              // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
 983   UCHAR    ucPadding[2];
 984 }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
 985
 986 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
 987 {
 988   ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS    sXTmdsEncoder;
 989   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION   sReserved;     //Caller doesn't need to init this portion
 990 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
 991
 992
 993 //ucTableFormatRevision=1,ucTableContentRevision=2
 994 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2
 995 {
 996   USHORT usPixelClock;  // in 10KHz; for bios convenient
 997   UCHAR  ucMisc;        // see PANEL_ENCODER_MISC_xx defintions below
 998   UCHAR  ucAction;      // 0: turn off encoder
 999                         // 1: setup and turn on encoder
1000   UCHAR  ucTruncate;    // bit0=0: Disable truncate
1001                         //     =1: Enable truncate
1002                         // bit4=0: 666RGB
1003                         //     =1: 888RGB
1004   UCHAR  ucSpatial;     // bit0=0: Disable spatial dithering
1005                         //     =1: Enable spatial dithering
1006                         // bit4=0: 666RGB
1007                         //     =1: 888RGB
1008   UCHAR  ucTemporal;    // bit0=0: Disable temporal dithering
1009                         //     =1: Enable temporal dithering
1010                         // bit4=0: 666RGB
1011                         //     =1: 888RGB
1012                         // bit5=0: Gray level 2
1013                         //     =1: Gray level 4
1014   UCHAR  ucFRC;         // bit4=0: 25FRC_SEL pattern E
1015                         //     =1: 25FRC_SEL pattern F
1016                         // bit6:5=0: 50FRC_SEL pattern A
1017                         //       =1: 50FRC_SEL pattern B
1018                         //       =2: 50FRC_SEL pattern C
1019                         //       =3: 50FRC_SEL pattern D
1020                         // bit7=0: 75FRC_SEL pattern E
1021                         //     =1: 75FRC_SEL pattern F
1022 }LVDS_ENCODER_CONTROL_PARAMETERS_V2;
1023
1024 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2
1025
1026 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2    LVDS_ENCODER_CONTROL_PARAMETERS_V2
1027 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
1028
1029 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2    TMDS1_ENCODER_CONTROL_PARAMETERS_V2
1030 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
1031 #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2
1032
1033 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
1034 {
1035   ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2    sXTmdsEncoder;
1036   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION      sReserved;     //Caller doesn't need to init this portion
1037 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
1038
1039
1040 //ucTableFormatRevision=1,ucTableContentRevision=3
1041
1042 //ucDVOConfig:
1043 #define DVO_ENCODER_CONFIG_RATE_SEL                                                     0x01
1044 #define DVO_ENCODER_CONFIG_DDR_SPEED                                            0x00
1045 #define DVO_ENCODER_CONFIG_SDR_SPEED                                            0x01
1046 #define DVO_ENCODER_CONFIG_OUTPUT_SEL                                           0x0c
1047 #define DVO_ENCODER_CONFIG_LOW12BIT                                                     0x00
1048 #define DVO_ENCODER_CONFIG_UPPER12BIT                                           0x04
1049 #define DVO_ENCODER_CONFIG_24BIT                                                                0x08
1050
1051 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3
1052 {
1053   USHORT usPixelClock;
1054   UCHAR  ucDVOConfig;
1055   UCHAR  ucAction;                                                                                                              //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
1056   UCHAR  ucReseved[4];
1057 }DVO_ENCODER_CONTROL_PARAMETERS_V3;
1058 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3    DVO_ENCODER_CONTROL_PARAMETERS_V3
1059
1060 //ucTableFormatRevision=1
1061 //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
1062 // bit1=0: non-coherent mode
1063 //     =1: coherent mode
1064
1065 #define LVDS_ENCODER_CONTROL_PARAMETERS_V3     LVDS_ENCODER_CONTROL_PARAMETERS_V2
1066 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3  LVDS_ENCODER_CONTROL_PARAMETERS_V3
1067
1068 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3
1069 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
1070
1071 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3
1072 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
1073
1074 //==========================================================================================
1075 //Only change is here next time when changing encoder parameter definitions again!
1076 #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST     LVDS_ENCODER_CONTROL_PARAMETERS_V3
1077 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST  LVDS_ENCODER_CONTROL_PARAMETERS_LAST
1078
1079 #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3
1080 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
1081
1082 #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3
1083 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
1084
1085 #define DVO_ENCODER_CONTROL_PARAMETERS_LAST      DVO_ENCODER_CONTROL_PARAMETERS
1086 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST   DVO_ENCODER_CONTROL_PS_ALLOCATION
1087
1088 //==========================================================================================
1089 #define PANEL_ENCODER_MISC_DUAL                0x01
1090 #define PANEL_ENCODER_MISC_COHERENT            0x02
1091 #define PANEL_ENCODER_MISC_TMDS_LINKB                                    0x04
1092 #define PANEL_ENCODER_MISC_HDMI_TYPE                                     0x08
1093
1094 #define PANEL_ENCODER_ACTION_DISABLE           ATOM_DISABLE
1095 #define PANEL_ENCODER_ACTION_ENABLE            ATOM_ENABLE
1096 #define PANEL_ENCODER_ACTION_COHERENTSEQ       (ATOM_ENABLE+1)
1097
1098 #define PANEL_ENCODER_TRUNCATE_EN              0x01
1099 #define PANEL_ENCODER_TRUNCATE_DEPTH           0x10
1100 #define PANEL_ENCODER_SPATIAL_DITHER_EN        0x01
1101 #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH     0x10
1102 #define PANEL_ENCODER_TEMPORAL_DITHER_EN       0x01
1103 #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH    0x10
1104 #define PANEL_ENCODER_TEMPORAL_LEVEL_4         0x20
1105 #define PANEL_ENCODER_25FRC_MASK               0x10
1106 #define PANEL_ENCODER_25FRC_E                  0x00
1107 #define PANEL_ENCODER_25FRC_F                  0x10
1108 #define PANEL_ENCODER_50FRC_MASK               0x60
1109 #define PANEL_ENCODER_50FRC_A                  0x00
1110 #define PANEL_ENCODER_50FRC_B                  0x20
1111 #define PANEL_ENCODER_50FRC_C                  0x40
1112 #define PANEL_ENCODER_50FRC_D                  0x60
1113 #define PANEL_ENCODER_75FRC_MASK               0x80
1114 #define PANEL_ENCODER_75FRC_E                  0x00
1115 #define PANEL_ENCODER_75FRC_F                  0x80
1116
1117 /**************************************************************************/
1118
1119 #define SET_VOLTAGE_TYPE_ASIC_VDDC             1
1120 #define SET_VOLTAGE_TYPE_ASIC_MVDDC            2
1121 #define SET_VOLTAGE_TYPE_ASIC_MVDDQ            3
1122 #define SET_VOLTAGE_TYPE_ASIC_VDDCI            4
1123
1124 #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE       0x1
1125 #define SET_ASIC_VOLTAGE_MODE_SOURCE_A         0x2
1126 #define SET_ASIC_VOLTAGE_MODE_SOURCE_B         0x4
1127
1128 #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE                        0x0
1129 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL                        0x1
1130 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK               0x2
1131
1132 typedef struct  _SET_VOLTAGE_PARAMETERS
1133 {
1134   UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
1135   UCHAR    ucVoltageMode;               // To set all, to set source A or source B or ...
1136   UCHAR    ucVoltageIndex;              // An index to tell which voltage level
1137   UCHAR    ucReserved;
1138 }SET_VOLTAGE_PARAMETERS;
1139
1140
1141 typedef struct  _SET_VOLTAGE_PARAMETERS_V2
1142 {
1143   UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
1144   UCHAR    ucVoltageMode;               // Not used, maybe use for state machine for differen power mode
1145   USHORT   usVoltageLevel;              // real voltage level
1146 }SET_VOLTAGE_PARAMETERS_V2;
1147
1148
1149 typedef struct _SET_VOLTAGE_PS_ALLOCATION
1150 {
1151   SET_VOLTAGE_PARAMETERS sASICSetVoltage;
1152   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
1153 }SET_VOLTAGE_PS_ALLOCATION;
1154
1155 typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION
1156 {
1157   TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;
1158   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION    sReserved; // Don't set this one
1159 }TV_ENCODER_CONTROL_PS_ALLOCATION;
1160
1161 //==============================Data Table Portion====================================
1162
1163 #ifdef  UEFI_BUILD
1164         #define UTEMP   USHORT
1165         #define USHORT  void*
1166 #endif
1167
1168 typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
1169 {
1170   USHORT        UtilityPipeLine;                // Offest for the utility to get parser info,Don't change this position!
1171   USHORT        MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios
1172   USHORT        MultimediaConfigInfo;     // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
1173   USHORT        StandardVESA_Timing;      // Only used by Bios
1174   USHORT        FirmwareInfo;             // Shared by various SW components,latest version 1.4
1175   USHORT        DAC_Info;                 // Will be obsolete from R600
1176   USHORT        LVDS_Info;                // Shared by various SW components,latest version 1.1
1177   USHORT        TMDS_Info;                // Will be obsolete from R600
1178   USHORT        AnalogTV_Info;            // Shared by various SW components,latest version 1.1
1179   USHORT        SupportedDevicesInfo;     // Will be obsolete from R600
1180   USHORT        GPIO_I2C_Info;            // Shared by various SW components,latest version 1.2 will be used from R600
1181   USHORT        VRAM_UsageByFirmware;     // Shared by various SW components,latest version 1.3 will be used from R600
1182   USHORT        GPIO_Pin_LUT;             // Shared by various SW components,latest version 1.1
1183   USHORT        VESA_ToInternalModeLUT;   // Only used by Bios
1184   USHORT        ComponentVideoInfo;       // Shared by various SW components,latest version 2.1 will be used from R600
1185   USHORT        PowerPlayInfo;            // Shared by various SW components,latest version 2.1,new design from R600
1186   USHORT        CompassionateData;        // Will be obsolete from R600
1187   USHORT        SaveRestoreInfo;          // Only used by Bios
1188   USHORT        PPLL_SS_Info;             // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
1189   USHORT        OemInfo;                  // Defined and used by external SW, should be obsolete soon
1190   USHORT        XTMDS_Info;               // Will be obsolete from R600
1191   USHORT        MclkSS_Info;              // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
1192   USHORT        Object_Header;            // Shared by various SW components,latest version 1.1
1193   USHORT        IndirectIOAccess;         // Only used by Bios,this table position can't change at all!!
1194   USHORT        MC_InitParameter;         // Only used by command table
1195   USHORT        ASIC_VDDC_Info;                                         // Will be obsolete from R600
1196   USHORT        ASIC_InternalSS_Info;                   // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
1197   USHORT        TV_VideoMode;                                                   // Only used by command table
1198   USHORT        VRAM_Info;                                                              // Only used by command table, latest version 1.3
1199   USHORT        MemoryTrainingInfo;                             // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
1200   USHORT        IntegratedSystemInfo;                   // Shared by various SW components
1201   USHORT        ASIC_ProfilingInfo;                             // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
1202   USHORT        VoltageObjectInfo;                              // Shared by various SW components, latest version 1.1
1203         USHORT                          PowerSourceInfo;                                        // Shared by various SW components, latest versoin 1.1
1204 }ATOM_MASTER_LIST_OF_DATA_TABLES;
1205
1206 #ifdef  UEFI_BUILD
1207         #define USHORT  UTEMP
1208 #endif
1209
1210
1211 typedef struct _ATOM_MASTER_DATA_TABLE
1212 {
1213   ATOM_COMMON_TABLE_HEADER sHeader;
1214   ATOM_MASTER_LIST_OF_DATA_TABLES   ListOfDataTables;
1215 }ATOM_MASTER_DATA_TABLE;
1216
1217
1218 typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO
1219 {
1220   ATOM_COMMON_TABLE_HEADER sHeader;
1221   ULONG                    ulSignature;      // HW info table signature string "$ATI"
1222   UCHAR                    ucI2C_Type;       // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
1223   UCHAR                    ucTV_OutInfo;     // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
1224   UCHAR                    ucVideoPortInfo;  // Provides the video port capabilities
1225   UCHAR                    ucHostPortInfo;   // Provides host port configuration information
1226 }ATOM_MULTIMEDIA_CAPABILITY_INFO;
1227
1228
1229 typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
1230 {
1231   ATOM_COMMON_TABLE_HEADER sHeader;
1232   ULONG                    ulSignature;      // MM info table signature sting "$MMT"
1233   UCHAR                    ucTunerInfo;      // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
1234   UCHAR                    ucAudioChipInfo;  // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
1235   UCHAR                    ucProductID;      // Defines as OEM ID or ATI board ID dependent on product type setting
1236   UCHAR                    ucMiscInfo1;      // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
1237   UCHAR                    ucMiscInfo2;      // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
1238   UCHAR                    ucMiscInfo3;      // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
1239   UCHAR                    ucMiscInfo4;      // Video Decoder Host Config (2:0) reserved (7:3)
1240   UCHAR                    ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
1241   UCHAR                    ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
1242   UCHAR                    ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
1243   UCHAR                    ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
1244   UCHAR                    ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
1245 }ATOM_MULTIMEDIA_CONFIG_INFO;
1246
1247 /****************************Firmware Info Table Definitions**********************/
1248
1249 // usBIOSCapability Defintion:
1250 // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
1251 // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
1252 // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
1253 // Others: Reserved
1254 #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED         0x0001
1255 #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT            0x0002
1256 #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT     0x0004
1257 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT      0x0008
1258 #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT      0x0010
1259 #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU         0x0020
1260 #define ATOM_BIOS_INFO_WMI_SUPPORT                  0x0040
1261 #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM   0x0080
1262 #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT          0x0100
1263 #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK        0x1E00
1264 #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
1265 #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE  0x4000
1266
1267
1268 #ifndef _H2INC
1269
1270 //Please don't add or expand this bitfield structure below, this one will retire soon.!
1271 typedef struct _ATOM_FIRMWARE_CAPABILITY
1272 {
1273 #if ATOM_BIG_ENDIAN
1274   USHORT Reserved:3;
1275   USHORT HyperMemory_Size:4;
1276   USHORT HyperMemory_Support:1;
1277   USHORT PPMode_Assigned:1;
1278   USHORT WMI_SUPPORT:1;
1279   USHORT GPUControlsBL:1;
1280   USHORT EngineClockSS_Support:1;
1281   USHORT MemoryClockSS_Support:1;
1282   USHORT ExtendedDesktopSupport:1;
1283   USHORT DualCRTC_Support:1;
1284   USHORT FirmwarePosted:1;
1285 #else
1286   USHORT FirmwarePosted:1;
1287   USHORT DualCRTC_Support:1;
1288   USHORT ExtendedDesktopSupport:1;
1289   USHORT MemoryClockSS_Support:1;
1290   USHORT EngineClockSS_Support:1;
1291   USHORT GPUControlsBL:1;
1292   USHORT WMI_SUPPORT:1;
1293   USHORT PPMode_Assigned:1;
1294   USHORT HyperMemory_Support:1;
1295   USHORT HyperMemory_Size:4;
1296   USHORT Reserved:3;
1297 #endif
1298 }ATOM_FIRMWARE_CAPABILITY;
1299
1300 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
1301 {
1302   ATOM_FIRMWARE_CAPABILITY sbfAccess;
1303   USHORT                   susAccess;
1304 }ATOM_FIRMWARE_CAPABILITY_ACCESS;
1305
1306 #else
1307
1308 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
1309 {
1310   USHORT                   susAccess;
1311 }ATOM_FIRMWARE_CAPABILITY_ACCESS;
1312
1313 #endif
1314
1315 typedef struct _ATOM_FIRMWARE_INFO
1316 {
1317   ATOM_COMMON_TABLE_HEADER        sHeader;
1318   ULONG                           ulFirmwareRevision;
1319   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
1320   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
1321   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
1322   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
1323   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
1324   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
1325   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
1326   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
1327   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
1328   UCHAR                           ucASICMaxTemperature;
1329   UCHAR                           ucPadding[3];               //Don't use them
1330   ULONG                           aulReservedForBIOS[3];      //Don't use them
1331   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
1332   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
1333   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
1334   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
1335   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
1336   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
1337   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
1338   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
1339   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
1340   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit, the definitions above can't change!!!
1341   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
1342   USHORT                          usReferenceClock;           //In 10Khz unit
1343   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
1344   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
1345   UCHAR                           ucDesign_ID;                //Indicate what is the board design
1346   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
1347 }ATOM_FIRMWARE_INFO;
1348
1349 typedef struct _ATOM_FIRMWARE_INFO_V1_2
1350 {
1351   ATOM_COMMON_TABLE_HEADER        sHeader;
1352   ULONG                           ulFirmwareRevision;
1353   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
1354   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
1355   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
1356   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
1357   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
1358   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
1359   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
1360   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
1361   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
1362   UCHAR                           ucASICMaxTemperature;
1363   UCHAR                           ucMinAllowedBL_Level;
1364   UCHAR                           ucPadding[2];               //Don't use them
1365   ULONG                           aulReservedForBIOS[2];      //Don't use them
1366   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
1367   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
1368   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
1369   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
1370   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
1371   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
1372   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
1373   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
1374   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
1375   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
1376   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
1377   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
1378   USHORT                          usReferenceClock;           //In 10Khz unit
1379   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
1380   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
1381   UCHAR                           ucDesign_ID;                //Indicate what is the board design
1382   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
1383 }ATOM_FIRMWARE_INFO_V1_2;
1384
1385 typedef struct _ATOM_FIRMWARE_INFO_V1_3
1386 {
1387   ATOM_COMMON_TABLE_HEADER        sHeader;
1388   ULONG                           ulFirmwareRevision;
1389   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
1390   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
1391   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
1392   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
1393   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
1394   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
1395   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
1396   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
1397   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
1398   UCHAR                           ucASICMaxTemperature;
1399   UCHAR                           ucMinAllowedBL_Level;
1400   UCHAR                           ucPadding[2];               //Don't use them
1401   ULONG                           aulReservedForBIOS;         //Don't use them
1402   ULONG                           ul3DAccelerationEngineClock;//In 10Khz unit
1403   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
1404   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
1405   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
1406   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
1407   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
1408   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
1409   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
1410   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
1411   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
1412   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
1413   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
1414   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
1415   USHORT                          usReferenceClock;           //In 10Khz unit
1416   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
1417   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
1418   UCHAR                           ucDesign_ID;                //Indicate what is the board design
1419   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
1420 }ATOM_FIRMWARE_INFO_V1_3;
1421
1422 typedef struct _ATOM_FIRMWARE_INFO_V1_4
1423 {
1424   ATOM_COMMON_TABLE_HEADER        sHeader;
1425   ULONG                           ulFirmwareRevision;
1426   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
1427   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
1428   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
1429   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
1430   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
1431   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
1432   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
1433   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
1434   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
1435   UCHAR                           ucASICMaxTemperature;
1436   UCHAR                           ucMinAllowedBL_Level;
1437   USHORT                          usBootUpVDDCVoltage;        //In MV unit
1438   USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
1439   USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
1440   ULONG                           ul3DAccelerationEngineClock;//In 10Khz unit
1441   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
1442   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
1443   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
1444   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
1445   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
1446   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
1447   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
1448   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
1449   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
1450   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
1451   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
1452   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
1453   USHORT                          usReferenceClock;           //In 10Khz unit
1454   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
1455   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
1456   UCHAR                           ucDesign_ID;                //Indicate what is the board design
1457   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
1458 }ATOM_FIRMWARE_INFO_V1_4;
1459
1460 #define ATOM_FIRMWARE_INFO_LAST  ATOM_FIRMWARE_INFO_V1_4
1461
1462 #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN      0x2
1463 #define IGP_CAP_FLAG_AC_CARD               0x4
1464 #define IGP_CAP_FLAG_SDVO_CARD             0x8
1465 #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE     0x10
1466
1467 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO
1468 {
1469   ATOM_COMMON_TABLE_HEADER        sHeader;
1470   ULONG                           ulBootUpEngineClock;              //in 10kHz unit
1471   ULONG                           ulBootUpMemoryClock;              //in 10kHz unit
1472   ULONG                           ulMaxSystemMemoryClock;           //in 10kHz unit
1473   ULONG                           ulMinSystemMemoryClock;           //in 10kHz unit
1474   UCHAR                           ucNumberOfCyclesInPeriodHi;
1475   UCHAR                           ucLCDTimingSel;             //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
1476   USHORT                          usReserved1;
1477   USHORT                          usInterNBVoltageLow;        //An intermidiate PMW value to set the voltage
1478   USHORT                          usInterNBVoltageHigh;       //Another intermidiate PMW value to set the voltage
1479   ULONG                           ulReserved[2];
1480
1481   USHORT                                usFSBClock;                                 //In MHz unit
1482   USHORT                          usCapabilityFlag;                     //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
1483                                                                                                                                                               //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
1484                                                               //Bit[4]==1: P/2 mode, ==0: P/1 mode
1485   USHORT                                usPCIENBCfgReg7;                                    //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
1486   USHORT                                usK8MemoryClock;            //in MHz unit
1487   USHORT                                usK8SyncStartDelay;         //in 0.01 us unit
1488   USHORT                                usK8DataReturnTime;         //in 0.01 us unit
1489   UCHAR                           ucMaxNBVoltage;
1490   UCHAR                           ucMinNBVoltage;
1491   UCHAR                           ucMemoryType;                                       //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
1492   UCHAR                           ucNumberOfCyclesInPeriod;             //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
1493   UCHAR                           ucStartingPWM_HighTime;     //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
1494   UCHAR                           ucHTLinkWidth;              //16 bit vs. 8 bit
1495   UCHAR                           ucMaxNBVoltageHigh;
1496   UCHAR                           ucMinNBVoltageHigh;
1497 }ATOM_INTEGRATED_SYSTEM_INFO;
1498
1499 /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
1500 ulBootUpMemoryClock:    For Intel IGP,it's the UMA system memory clock
1501                         For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
1502 ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
1503                         For AMD IGP,for now this can be 0
1504 ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
1505                         For AMD IGP,for now this can be 0
1506
1507 usFSBClock:             For Intel IGP,it's FSB Freq
1508                         For AMD IGP,it's HT Link Speed
1509
1510 usK8MemoryClock:        For AMD IGP only. For RevF CPU, set it to 200
1511 usK8SyncStartDelay:     For AMD IGP only. Memory access latency in K8, required for watermark calculation
1512 usK8DataReturnTime:     For AMD IGP only. Memory access latency in K8, required for watermark calculation
1513
1514 VC:Voltage Control
1515 ucMaxNBVoltage:         Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
1516 ucMinNBVoltage:         Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
1517
1518 ucNumberOfCyclesInPeriod:   Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
1519 ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
1520
1521 ucMaxNBVoltageHigh:     Voltage regulator dependent PWM value. High 8 bits of  the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
1522 ucMinNBVoltageHigh:     Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
1523
1524
1525 usInterNBVoltageLow:    Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
1526 usInterNBVoltageHigh:   Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
1527 */
1528
1529
1530 /*
1531 The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;
1532 Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.
1533 The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
1534
1535 SW components can access the IGP system infor structure in the same way as before
1536 */
1537
1538
1539 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
1540 {
1541   ATOM_COMMON_TABLE_HEADER   sHeader;
1542   ULONG                      ulBootUpEngineClock;       //in 10kHz unit
1543   ULONG                                  ulReserved1[2];            //must be 0x0 for the reserved
1544   ULONG                      ulBootUpUMAClock;          //in 10kHz unit
1545   ULONG                      ulBootUpSidePortClock;     //in 10kHz unit
1546   ULONG                      ulMinSidePortClock;        //in 10kHz unit
1547   ULONG                                  ulReserved2[6];            //must be 0x0 for the reserved
1548   ULONG                      ulSystemConfig;            //see explanation below
1549   ULONG                      ulBootUpReqDisplayVector;
1550   ULONG                      ulOtherDisplayMisc;
1551   ULONG                      ulDDISlot1Config;
1552   ULONG                      ulDDISlot2Config;
1553   UCHAR                      ucMemoryType;              //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
1554   UCHAR                      ucUMAChannelNumber;
1555   UCHAR                      ucDockingPinBit;
1556   UCHAR                      ucDockingPinPolarity;
1557   ULONG                      ulDockingPinCFGInfo;
1558   ULONG                      ulCPUCapInfo;
1559   USHORT                     usNumberOfCyclesInPeriod;
1560   USHORT                     usMaxNBVoltage;
1561   USHORT                     usMinNBVoltage;
1562   USHORT                     usBootUpNBVoltage;
1563   ULONG                      ulHTLinkFreq;              //in 10Khz
1564   USHORT                     usMinHTLinkWidth;
1565   USHORT                     usMaxHTLinkWidth;
1566   USHORT                     usUMASyncStartDelay;
1567   USHORT                     usUMADataReturnTime;
1568   USHORT                     usLinkStatusZeroTime;
1569   USHORT                     usReserved;
1570   ULONG                      ulReserved3[101];          //must be 0x0
1571 }ATOM_INTEGRATED_SYSTEM_INFO_V2;
1572
1573 /*
1574 ulBootUpEngineClock:   Boot-up Engine Clock in 10Khz;
1575 ulBootUpUMAClock:      Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
1576 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock
1577
1578 ulSystemConfig:
1579 Bit[0]: =1 PowerExpress mode =0 Non-PowerExpress mode;
1580 Bit[1]=1: system is running at overdrived engine clock =0:system is not running at overdrived engine clock
1581
1582 ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
1583
1584 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
1585                                       [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition;
1586
1587 ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
1588       [3:0]  - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
1589                         [7:4]  - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
1590                         [15:8] - Lane configuration attribute;
1591       [23:16]- Connector type, possible value:
1592                CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
1593                CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
1594                CONNECTOR_OBJECT_ID_HDMI_TYPE_A
1595                CONNECTOR_OBJECT_ID_DISPLAYPORT
1596                         [31:24]- Reserved
1597
1598 ulDDISlot2Config: Same as Slot1.
1599 ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.
1600 For IGP, Hypermemory is the only memory type showed in CCC.
1601
1602 ucUMAChannelNumber:  how many channels for the UMA;
1603
1604 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin
1605 ucDockingPinBit:     which bit in this register to read the pin status;
1606 ucDockingPinPolarity:Polarity of the pin when docked;
1607
1608 ulCPUCapInfo:        [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, other bits reserved for now and must be 0x0
1609
1610 usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
1611 usMaxNBVoltage:Voltage regulator dependent PWM value.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
1612 usMinNBVoltage:Voltage regulator dependent PWM value.Set this one to 0x00 if VC without PWM or no VC at all.
1613 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
1614
1615
1616 ulHTLinkFreq:        Current HT link Frequency in 10Khz.
1617 usMinHTLinkWidth:
1618 usMaxHTLinkWidth:
1619 usUMASyncStartDelay: Memory access latency, required for watermark calculation
1620 usUMADataReturnTime: Memory access latency, required for watermark calculation
1621 usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us
1622 for Griffin or Greyhound. SBIOS needs to convert to actual time by:
1623                      if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
1624                      if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
1625                      if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
1626                      if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)
1627 */
1628
1629 #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE                 0x00000001
1630 #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE             0x00000002
1631
1632 #define IGP_DDI_SLOT_LANE_CONFIG_MASK                     0x000000FF
1633
1634 #define b0IGP_DDI_SLOT_LANE_MAP_MASK                      0x0F
1635 #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK              0xF0
1636 #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3                    0x01
1637 #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7                    0x02
1638 #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11                   0x04
1639 #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15                  0x08
1640
1641 #define IGP_DDI_SLOT_ATTRIBUTE_MASK                       0x0000FF00
1642 #define IGP_DDI_SLOT_CONFIG_REVERSED                      0x00000100
1643 #define b1IGP_DDI_SLOT_CONFIG_REVERSED                    0x01
1644
1645 #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK                  0x00FF0000
1646
1647 #define ATOM_CRT_INT_ENCODER1_INDEX                       0x00000000
1648 #define ATOM_LCD_INT_ENCODER1_INDEX                       0x00000001
1649 #define ATOM_TV_INT_ENCODER1_INDEX                        0x00000002
1650 #define ATOM_DFP_INT_ENCODER1_INDEX                       0x00000003
1651 #define ATOM_CRT_INT_ENCODER2_INDEX                       0x00000004
1652 #define ATOM_LCD_EXT_ENCODER1_INDEX                       0x00000005
1653 #define ATOM_TV_EXT_ENCODER1_INDEX                        0x00000006
1654 #define ATOM_DFP_EXT_ENCODER1_INDEX                       0x00000007
1655 #define ATOM_CV_INT_ENCODER1_INDEX                        0x00000008
1656 #define ATOM_DFP_INT_ENCODER2_INDEX                       0x00000009
1657 #define ATOM_CRT_EXT_ENCODER1_INDEX                       0x0000000A
1658 #define ATOM_CV_EXT_ENCODER1_INDEX                        0x0000000B
1659 #define ATOM_DFP_INT_ENCODER3_INDEX                       0x0000000C
1660 #define ATOM_DFP_INT_ENCODER4_INDEX                       0x0000000D
1661
1662 // define ASIC internal encoder id ( bit vector )
1663 #define ASIC_INT_DAC1_ENCODER_ID                                                                                        0x00
1664 #define ASIC_INT_TV_ENCODER_ID                                                                                                          0x02
1665 #define ASIC_INT_DIG1_ENCODER_ID                                                                                                        0x03
1666 #define ASIC_INT_DAC2_ENCODER_ID                                                                                                        0x04
1667 #define ASIC_EXT_TV_ENCODER_ID                                                                                                          0x06
1668 #define ASIC_INT_DVO_ENCODER_ID                                                                                                         0x07
1669 #define ASIC_INT_DIG2_ENCODER_ID                                                                                                        0x09
1670 #define ASIC_EXT_DIG_ENCODER_ID                                                                                                         0x05
1671
1672 //define Encoder attribute
1673 #define ATOM_ANALOG_ENCODER                                                                                                                             0
1674 #define ATOM_DIGITAL_ENCODER                                                                                                                    1
1675
1676 #define ATOM_DEVICE_CRT1_INDEX                            0x00000000
1677 #define ATOM_DEVICE_LCD1_INDEX                            0x00000001
1678 #define ATOM_DEVICE_TV1_INDEX                             0x00000002
1679 #define ATOM_DEVICE_DFP1_INDEX                            0x00000003
1680 #define ATOM_DEVICE_CRT2_INDEX                            0x00000004
1681 #define ATOM_DEVICE_LCD2_INDEX                            0x00000005
1682 #define ATOM_DEVICE_TV2_INDEX                             0x00000006
1683 #define ATOM_DEVICE_DFP2_INDEX                            0x00000007
1684 #define ATOM_DEVICE_CV_INDEX                              0x00000008
1685 #define ATOM_DEVICE_DFP3_INDEX                                                                                                          0x00000009
1686 #define ATOM_DEVICE_RESERVEDA_INDEX                       0x0000000A
1687 #define ATOM_DEVICE_RESERVEDB_INDEX                       0x0000000B
1688 #define ATOM_DEVICE_RESERVEDC_INDEX                       0x0000000C
1689 #define ATOM_DEVICE_RESERVEDD_INDEX                       0x0000000D
1690 #define ATOM_DEVICE_RESERVEDE_INDEX                       0x0000000E
1691 #define ATOM_DEVICE_RESERVEDF_INDEX                       0x0000000F
1692 #define ATOM_MAX_SUPPORTED_DEVICE_INFO                    (ATOM_DEVICE_CV_INDEX+2)
1693 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2                  ATOM_MAX_SUPPORTED_DEVICE_INFO
1694 #define ATOM_MAX_SUPPORTED_DEVICE                         (ATOM_DEVICE_RESERVEDF_INDEX+1)
1695
1696 #define ATOM_DEVICE_CRT1_SUPPORT                          (0x1L << ATOM_DEVICE_CRT1_INDEX )
1697 #define ATOM_DEVICE_LCD1_SUPPORT                          (0x1L << ATOM_DEVICE_LCD1_INDEX )
1698 #define ATOM_DEVICE_TV1_SUPPORT                           (0x1L << ATOM_DEVICE_TV1_INDEX  )
1699 #define ATOM_DEVICE_DFP1_SUPPORT                          (0x1L << ATOM_DEVICE_DFP1_INDEX)
1700 #define ATOM_DEVICE_CRT2_SUPPORT                          (0x1L << ATOM_DEVICE_CRT2_INDEX )
1701 #define ATOM_DEVICE_LCD2_SUPPORT                          (0x1L << ATOM_DEVICE_LCD2_INDEX )
1702 #define ATOM_DEVICE_TV2_SUPPORT                           (0x1L << ATOM_DEVICE_TV2_INDEX  )
1703 #define ATOM_DEVICE_DFP2_SUPPORT                          (0x1L << ATOM_DEVICE_DFP2_INDEX)
1704 #define ATOM_DEVICE_CV_SUPPORT                            (0x1L << ATOM_DEVICE_CV_INDEX   )
1705 #define ATOM_DEVICE_DFP3_SUPPORT                                                                                                        (0x1L << ATOM_DEVICE_DFP3_INDEX )
1706
1707 #define ATOM_DEVICE_CRT_SUPPORT                           ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT
1708 #define ATOM_DEVICE_DFP_SUPPORT                           ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT |  ATOM_DEVICE_DFP3_SUPPORT
1709 #define ATOM_DEVICE_TV_SUPPORT                            ATOM_DEVICE_TV1_SUPPORT  | ATOM_DEVICE_TV2_SUPPORT
1710 #define ATOM_DEVICE_LCD_SUPPORT                           ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT
1711
1712 #define ATOM_DEVICE_CONNECTOR_TYPE_MASK                   0x000000F0
1713 #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT                  0x00000004
1714 #define ATOM_DEVICE_CONNECTOR_VGA                         0x00000001
1715 #define ATOM_DEVICE_CONNECTOR_DVI_I                       0x00000002
1716 #define ATOM_DEVICE_CONNECTOR_DVI_D                       0x00000003
1717 #define ATOM_DEVICE_CONNECTOR_DVI_A                       0x00000004
1718 #define ATOM_DEVICE_CONNECTOR_SVIDEO                      0x00000005
1719 #define ATOM_DEVICE_CONNECTOR_COMPOSITE                   0x00000006
1720 #define ATOM_DEVICE_CONNECTOR_LVDS                        0x00000007
1721 #define ATOM_DEVICE_CONNECTOR_DIGI_LINK                   0x00000008
1722 #define ATOM_DEVICE_CONNECTOR_SCART                       0x00000009
1723 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A                 0x0000000A
1724 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B                 0x0000000B
1725 #define ATOM_DEVICE_CONNECTOR_CASE_1                      0x0000000E
1726 #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT                 0x0000000F
1727
1728
1729 #define ATOM_DEVICE_DAC_INFO_MASK                         0x0000000F
1730 #define ATOM_DEVICE_DAC_INFO_SHIFT                        0x00000000
1731 #define ATOM_DEVICE_DAC_INFO_NODAC                        0x00000000
1732 #define ATOM_DEVICE_DAC_INFO_DACA                         0x00000001
1733 #define ATOM_DEVICE_DAC_INFO_DACB                         0x00000002
1734 #define ATOM_DEVICE_DAC_INFO_EXDAC                        0x00000003
1735
1736 #define ATOM_DEVICE_I2C_ID_NOI2C                          0x00000000
1737
1738 #define ATOM_DEVICE_I2C_LINEMUX_MASK                      0x0000000F
1739 #define ATOM_DEVICE_I2C_LINEMUX_SHIFT                     0x00000000
1740
1741 #define ATOM_DEVICE_I2C_ID_MASK                           0x00000070
1742 #define ATOM_DEVICE_I2C_ID_SHIFT                          0x00000004
1743 #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE              0x00000001
1744 #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE                  0x00000002
1745 #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE                0x00000003    //For IGP RS600
1746 #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL                 0x00000004    //For IGP RS690
1747
1748 #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK                 0x00000080
1749 #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT                0x00000007
1750 #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C            0x00000000
1751 #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C            0x00000001
1752
1753 //  usDeviceSupport:
1754 //  Bits0       = 0 - no CRT1 support= 1- CRT1 is supported
1755 //  Bit 1       = 0 - no LCD1 support= 1- LCD1 is supported
1756 //  Bit 2       = 0 - no TV1  support= 1- TV1  is supported
1757 //  Bit 3       = 0 - no DFP1 support= 1- DFP1 is supported
1758 //  Bit 4       = 0 - no CRT2 support= 1- CRT2 is supported
1759 //  Bit 5       = 0 - no LCD2 support= 1- LCD2 is supported
1760 //  Bit 6       = 0 - no TV2  support= 1- TV2  is supported
1761 //  Bit 7       = 0 - no DFP2 support= 1- DFP2 is supported
1762 //  Bit 8       = 0 - no CV   support= 1- CV   is supported
1763 //  Bit 9       = 0 - no DFP3 support= 1- DFP3 is supported
1764 //  Byte1 (Supported Device Info)
1765 //  Bit 0       = = 0 - no CV support= 1- CV is supported
1766 //
1767 //
1768
1769 //              ucI2C_ConfigID
1770 //    [7:0] - I2C LINE Associate ID
1771 //          = 0   - no I2C
1772 //    [7]               -       HW_Cap        = 1,  [6:0]=HW assisted I2C ID(HW line selection)
1773 //                          =   0,  [6:0]=SW assisted I2C ID
1774 //    [6-4]     - HW_ENGINE_ID  =       1,  HW engine for NON multimedia use
1775 //                          =   2,      HW engine for Multimedia use
1776 //                          =   3-7     Reserved for future I2C engines
1777 //              [3-0] - I2C_LINE_MUX  = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
1778
1779
1780 typedef struct _ATOM_I2C_ID_CONFIG
1781 {
1782 #if ATOM_BIG_ENDIAN
1783   UCHAR   bfHW_Capable:1;
1784   UCHAR   bfHW_EngineID:3;
1785   UCHAR   bfI2C_LineMux:4;
1786 #else
1787   UCHAR   bfI2C_LineMux:4;
1788   UCHAR   bfHW_EngineID:3;
1789   UCHAR   bfHW_Capable:1;
1790 #endif
1791 }ATOM_I2C_ID_CONFIG;
1792
1793 typedef union _ATOM_I2C_ID_CONFIG_ACCESS
1794 {
1795   ATOM_I2C_ID_CONFIG sbfAccess;
1796   UCHAR              ucAccess;
1797 }ATOM_I2C_ID_CONFIG_ACCESS;
1798
1799
1800 typedef struct _ATOM_GPIO_I2C_ASSIGMENT
1801 {
1802   USHORT                    usClkMaskRegisterIndex;
1803   USHORT                    usClkEnRegisterIndex;
1804   USHORT                    usClkY_RegisterIndex;
1805   USHORT                    usClkA_RegisterIndex;
1806   USHORT                    usDataMaskRegisterIndex;
1807   USHORT                    usDataEnRegisterIndex;
1808   USHORT                    usDataY_RegisterIndex;
1809   USHORT                    usDataA_RegisterIndex;
1810   ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
1811   UCHAR                     ucClkMaskShift;
1812   UCHAR                     ucClkEnShift;
1813   UCHAR                     ucClkY_Shift;
1814   UCHAR                     ucClkA_Shift;
1815   UCHAR                     ucDataMaskShift;
1816   UCHAR                     ucDataEnShift;
1817   UCHAR                     ucDataY_Shift;
1818   UCHAR                     ucDataA_Shift;
1819   UCHAR                     ucReserved1;
1820   UCHAR                     ucReserved2;
1821 }ATOM_GPIO_I2C_ASSIGMENT;
1822
1823 typedef struct _ATOM_GPIO_I2C_INFO
1824 {
1825   ATOM_COMMON_TABLE_HEADER      sHeader;
1826   ATOM_GPIO_I2C_ASSIGMENT   asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE];
1827 }ATOM_GPIO_I2C_INFO;
1828
1829
1830 #ifndef _H2INC
1831
1832 //Please don't add or expand this bitfield structure below, this one will retire soon.!
1833 typedef struct _ATOM_MODE_MISC_INFO
1834 {
1835 #if ATOM_BIG_ENDIAN
1836   USHORT Reserved:6;
1837   USHORT RGB888:1;
1838   USHORT DoubleClock:1;
1839   USHORT Interlace:1;
1840   USHORT CompositeSync:1;
1841   USHORT V_ReplicationBy2:1;
1842   USHORT H_ReplicationBy2:1;
1843   USHORT VerticalCutOff:1;
1844   USHORT VSyncPolarity:1;      //0=Active High, 1=Active Low
1845   USHORT HSyncPolarity:1;      //0=Active High, 1=Active Low
1846   USHORT HorizontalCutOff:1;
1847 #else
1848   USHORT HorizontalCutOff:1;
1849   USHORT HSyncPolarity:1;      //0=Active High, 1=Active Low
1850   USHORT VSyncPolarity:1;      //0=Active High, 1=Active Low
1851   USHORT VerticalCutOff:1;
1852   USHORT H_ReplicationBy2:1;
1853   USHORT V_ReplicationBy2:1;
1854   USHORT CompositeSync:1;
1855   USHORT Interlace:1;
1856   USHORT DoubleClock:1;
1857   USHORT RGB888:1;
1858   USHORT Reserved:6;
1859 #endif
1860 }ATOM_MODE_MISC_INFO;
1861
1862 typedef union _ATOM_MODE_MISC_INFO_ACCESS
1863 {
1864   ATOM_MODE_MISC_INFO sbfAccess;
1865   USHORT              usAccess;
1866 }ATOM_MODE_MISC_INFO_ACCESS;
1867
1868 #else
1869
1870 typedef union _ATOM_MODE_MISC_INFO_ACCESS
1871 {
1872   USHORT              usAccess;
1873 }ATOM_MODE_MISC_INFO_ACCESS;
1874
1875 #endif
1876
1877 // usModeMiscInfo-
1878 #define ATOM_H_CUTOFF           0x01
1879 #define ATOM_HSYNC_POLARITY     0x02             //0=Active High, 1=Active Low
1880 #define ATOM_VSYNC_POLARITY     0x04             //0=Active High, 1=Active Low
1881 #define ATOM_V_CUTOFF           0x08
1882 #define ATOM_H_REPLICATIONBY2   0x10
1883 #define ATOM_V_REPLICATIONBY2   0x20
1884 #define ATOM_COMPOSITESYNC      0x40
1885 #define ATOM_INTERLACE          0x80
1886 #define ATOM_DOUBLE_CLOCK_MODE  0x100
1887 #define ATOM_RGB888_MODE        0x200
1888
1889 //usRefreshRate-
1890 #define ATOM_REFRESH_43         43
1891 #define ATOM_REFRESH_47         47
1892 #define ATOM_REFRESH_56         56
1893 #define ATOM_REFRESH_60         60
1894 #define ATOM_REFRESH_65         65
1895 #define ATOM_REFRESH_70         70
1896 #define ATOM_REFRESH_72         72
1897 #define ATOM_REFRESH_75         75
1898 #define ATOM_REFRESH_85         85
1899
1900 // ATOM_MODE_TIMING data are exactly the same as VESA timing data.
1901 // Translation from EDID to ATOM_MODE_TIMING, use the following formula.
1902 //
1903 //      VESA_HTOTAL                     =       VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK
1904 //                                              =       EDID_HA + EDID_HBL
1905 //      VESA_HDISP                      =       VESA_ACTIVE     =       EDID_HA
1906 //      VESA_HSYNC_START        =       VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH
1907 //                                              =       EDID_HA + EDID_HSO
1908 //      VESA_HSYNC_WIDTH        =       VESA_HSYNC_TIME =       EDID_HSPW
1909 //      VESA_BORDER                     =       EDID_BORDER
1910
1911
1912 typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS
1913 {
1914   USHORT  usH_Size;
1915   USHORT  usH_Blanking_Time;
1916   USHORT  usV_Size;
1917   USHORT  usV_Blanking_Time;
1918   USHORT  usH_SyncOffset;
1919   USHORT  usH_SyncWidth;
1920   USHORT  usV_SyncOffset;
1921   USHORT  usV_SyncWidth;
1922   ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;
1923   UCHAR   ucH_Border;         // From DFP EDID
1924   UCHAR   ucV_Border;
1925   UCHAR   ucCRTC;             // ATOM_CRTC1 or ATOM_CRTC2
1926   UCHAR   ucPadding[3];
1927 }SET_CRTC_USING_DTD_TIMING_PARAMETERS;
1928
1929 typedef struct _SET_CRTC_TIMING_PARAMETERS
1930 {
1931   USHORT                      usH_Total;        // horizontal total
1932   USHORT                      usH_Disp;         // horizontal display
1933   USHORT                      usH_SyncStart;    // horozontal Sync start
1934   USHORT                      usH_SyncWidth;    // horizontal Sync width
1935   USHORT                      usV_Total;        // vertical total
1936   USHORT                      usV_Disp;         // vertical display
1937   USHORT                      usV_SyncStart;    // vertical Sync start
1938   USHORT                      usV_SyncWidth;    // vertical Sync width
1939   ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;
1940   UCHAR                       ucCRTC;           // ATOM_CRTC1 or ATOM_CRTC2
1941   UCHAR                       ucOverscanRight;  // right
1942   UCHAR                       ucOverscanLeft;   // left
1943   UCHAR                       ucOverscanBottom; // bottom
1944   UCHAR                       ucOverscanTop;    // top
1945   UCHAR                       ucReserved;
1946 }SET_CRTC_TIMING_PARAMETERS;
1947 #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS
1948
1949
1950 typedef struct _ATOM_MODE_TIMING
1951 {
1952   USHORT  usCRTC_H_Total;
1953   USHORT  usCRTC_H_Disp;
1954   USHORT  usCRTC_H_SyncStart;
1955   USHORT  usCRTC_H_SyncWidth;
1956   USHORT  usCRTC_V_Total;
1957   USHORT  usCRTC_V_Disp;
1958   USHORT  usCRTC_V_SyncStart;
1959   USHORT  usCRTC_V_SyncWidth;
1960   USHORT  usPixelClock;                                                  //in 10Khz unit
1961   ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;
1962   USHORT  usCRTC_OverscanRight;
1963   USHORT  usCRTC_OverscanLeft;
1964   USHORT  usCRTC_OverscanBottom;
1965   USHORT  usCRTC_OverscanTop;
1966   USHORT  usReserve;
1967   UCHAR   ucInternalModeNumber;
1968   UCHAR   ucRefreshRate;
1969 }ATOM_MODE_TIMING;
1970
1971
1972 typedef struct _ATOM_DTD_FORMAT
1973 {
1974   USHORT  usPixClk;
1975   USHORT  usHActive;
1976   USHORT  usHBlanking_Time;
1977   USHORT  usVActive;
1978   USHORT  usVBlanking_Time;
1979   USHORT  usHSyncOffset;
1980   USHORT  usHSyncWidth;
1981   USHORT  usVSyncOffset;
1982   USHORT  usVSyncWidth;
1983   USHORT  usImageHSize;
1984   USHORT  usImageVSize;
1985   UCHAR   ucHBorder;
1986   UCHAR   ucVBorder;
1987   ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
1988   UCHAR   ucInternalModeNumber;
1989   UCHAR   ucRefreshRate;
1990 }ATOM_DTD_FORMAT;
1991
1992 #define SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
1993 #define SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
1994 #define SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
1995 #define SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
1996
1997 /****************************LVDS Info Table Definitions **********************/
1998 //ucTableFormatRevision=1
1999 //ucTableContentRevision=1
2000 typedef struct _ATOM_LVDS_INFO
2001 {
2002   ATOM_COMMON_TABLE_HEADER sHeader;
2003   ATOM_DTD_FORMAT     sLCDTiming;
2004   USHORT              usModePatchTableOffset;
2005   USHORT              usSupportedRefreshRate;     //Refer to panel info table in ATOMBIOS extension Spec.
2006   USHORT              usOffDelayInMs;
2007   UCHAR               ucPowerSequenceDigOntoDEin10Ms;
2008   UCHAR               ucPowerSequenceDEtoBLOnin10Ms;
2009   UCHAR               ucLVDS_Misc;               // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
2010                                                  // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
2011                                                  // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
2012                                                  // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
2013   UCHAR               ucPanelDefaultRefreshRate;
2014   UCHAR               ucPanelIdentification;
2015   UCHAR               ucSS_Id;
2016 }ATOM_LVDS_INFO;
2017
2018 //ucTableFormatRevision=1
2019 //ucTableContentRevision=2
2020 typedef struct _ATOM_LVDS_INFO_V12
2021 {
2022   ATOM_COMMON_TABLE_HEADER sHeader;
2023   ATOM_DTD_FORMAT     sLCDTiming;
2024   USHORT              usExtInfoTableOffset;
2025   USHORT              usSupportedRefreshRate;     //Refer to panel info table in ATOMBIOS extension Spec.
2026   USHORT              usOffDelayInMs;
2027   UCHAR               ucPowerSequenceDigOntoDEin10Ms;
2028   UCHAR               ucPowerSequenceDEtoBLOnin10Ms;
2029   UCHAR               ucLVDS_Misc;               // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
2030                                                  // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
2031                                                  // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
2032                                                  // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
2033   UCHAR               ucPanelDefaultRefreshRate;
2034   UCHAR               ucPanelIdentification;
2035   UCHAR               ucSS_Id;
2036   USHORT              usLCDVenderID;
2037   USHORT              usLCDProductID;
2038   UCHAR               ucLCDPanel_SpecialHandlingCap;
2039         UCHAR                                                           ucPanelInfoSize;                                        //  start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
2040   UCHAR               ucReserved[2];
2041 }ATOM_LVDS_INFO_V12;
2042
2043 #define ATOM_LVDS_INFO_LAST  ATOM_LVDS_INFO_V12
2044
2045 typedef struct  _ATOM_PATCH_RECORD_MODE
2046 {
2047   UCHAR     ucRecordType;
2048   USHORT    usHDisp;
2049   USHORT    usVDisp;
2050 }ATOM_PATCH_RECORD_MODE;
2051
2052 typedef struct  _ATOM_LCD_RTS_RECORD
2053 {
2054   UCHAR     ucRecordType;
2055   UCHAR     ucRTSValue;
2056 }ATOM_LCD_RTS_RECORD;
2057
2058 //!! If the record below exits, it shoud always be the first record for easy use in command table!!!
2059 typedef struct  _ATOM_LCD_MODE_CONTROL_CAP
2060 {
2061   UCHAR     ucRecordType;
2062   USHORT    usLCDCap;
2063 }ATOM_LCD_MODE_CONTROL_CAP;
2064
2065 #define LCD_MODE_CAP_BL_OFF                   1
2066 #define LCD_MODE_CAP_CRTC_OFF                 2
2067 #define LCD_MODE_CAP_PANEL_OFF                4
2068
2069 typedef struct _ATOM_FAKE_EDID_PATCH_RECORD
2070 {
2071   UCHAR ucRecordType;
2072   UCHAR ucFakeEDIDLength;
2073   UCHAR ucFakeEDIDString[1];    // This actually has ucFakeEdidLength elements.
2074 } ATOM_FAKE_EDID_PATCH_RECORD;
2075
2076 typedef struct  _ATOM_PANEL_RESOLUTION_PATCH_RECORD
2077 {
2078    UCHAR    ucRecordType;
2079    USHORT               usHSize;
2080    USHORT               usVSize;
2081 }ATOM_PANEL_RESOLUTION_PATCH_RECORD;
2082
2083 #define LCD_MODE_PATCH_RECORD_MODE_TYPE       1
2084 #define LCD_RTS_RECORD_TYPE                   2
2085 #define LCD_CAP_RECORD_TYPE                   3
2086 #define LCD_FAKE_EDID_PATCH_RECORD_TYPE       4
2087 #define LCD_PANEL_RESOLUTION_RECORD_TYPE      5
2088 #define ATOM_RECORD_END_TYPE                  0xFF
2089
2090 /****************************Spread Spectrum Info Table Definitions **********************/
2091
2092 //ucTableFormatRevision=1
2093 //ucTableContentRevision=2
2094 typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
2095 {
2096   USHORT              usSpreadSpectrumPercentage;
2097   UCHAR               ucSpreadSpectrumType;         //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
2098   UCHAR               ucSS_Step;
2099   UCHAR               ucSS_Delay;
2100   UCHAR               ucSS_Id;
2101   UCHAR               ucRecommandedRef_Div;
2102   UCHAR               ucSS_Range;               //it was reserved for V11
2103 }ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
2104
2105 #define ATOM_MAX_SS_ENTRY                      16
2106 #define ATOM_DP_SS_ID1                                                                                           0x0f1                  // SS modulation freq=30k
2107 #define ATOM_DP_SS_ID2                                                                                           0x0f2                  // SS modulation freq=33k
2108
2109
2110 #define ATOM_SS_DOWN_SPREAD_MODE_MASK          0x00000000
2111 #define ATOM_SS_DOWN_SPREAD_MODE               0x00000000
2112 #define ATOM_SS_CENTRE_SPREAD_MODE_MASK        0x00000001
2113 #define ATOM_SS_CENTRE_SPREAD_MODE             0x00000001
2114 #define ATOM_INTERNAL_SS_MASK                  0x00000000
2115 #define ATOM_EXTERNAL_SS_MASK                  0x00000002
2116 #define EXEC_SS_STEP_SIZE_SHIFT                2
2117 #define EXEC_SS_DELAY_SHIFT                    4
2118 #define ACTIVEDATA_TO_BLON_DELAY_SHIFT         4
2119
2120 typedef struct _ATOM_SPREAD_SPECTRUM_INFO
2121 {
2122   ATOM_COMMON_TABLE_HEADER      sHeader;
2123   ATOM_SPREAD_SPECTRUM_ASSIGNMENT   asSS_Info[ATOM_MAX_SS_ENTRY];
2124 }ATOM_SPREAD_SPECTRUM_INFO;
2125
2126
2127
2128
2129 //ucTVBootUpDefaultStd definiton:
2130
2131 //ATOM_TV_NTSC                1
2132 //ATOM_TV_NTSCJ               2
2133 //ATOM_TV_PAL                 3
2134 //ATOM_TV_PALM                4
2135 //ATOM_TV_PALCN               5
2136 //ATOM_TV_PALN                6
2137 //ATOM_TV_PAL60               7
2138 //ATOM_TV_SECAM               8
2139
2140
2141 //ucTVSuppportedStd definition:
2142 #define NTSC_SUPPORT          0x1
2143 #define NTSCJ_SUPPORT         0x2
2144
2145 #define PAL_SUPPORT           0x4
2146 #define PALM_SUPPORT          0x8
2147 #define PALCN_SUPPORT         0x10
2148 #define PALN_SUPPORT          0x20
2149 #define PAL60_SUPPORT         0x40
2150 #define SECAM_SUPPORT         0x80
2151
2152 #define MAX_SUPPORTED_TV_TIMING    2
2153
2154 typedef struct _ATOM_ANALOG_TV_INFO
2155 {
2156   ATOM_COMMON_TABLE_HEADER sHeader;
2157   UCHAR                    ucTV_SupportedStandard;
2158   UCHAR                    ucTV_BootUpDefaultStandard;
2159   UCHAR                    ucExt_TV_ASIC_ID;
2160   UCHAR                    ucExt_TV_ASIC_SlaveAddr;
2161   /*ATOM_DTD_FORMAT          aModeTimings[MAX_SUPPORTED_TV_TIMING];*/
2162   ATOM_MODE_TIMING         aModeTimings[MAX_SUPPORTED_TV_TIMING];
2163 }ATOM_ANALOG_TV_INFO;
2164
2165
2166 /**************************************************************************/
2167 // VRAM usage and their defintions
2168
2169 // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data.
2170 // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below.
2171 // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned!
2172 // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR
2173 // To Bios:  ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
2174
2175 #ifndef VESA_MEMORY_IN_64K_BLOCK
2176 #define VESA_MEMORY_IN_64K_BLOCK        0x100       //256*64K=16Mb (Max. VESA memory is 16Mb!)
2177 #endif
2178
2179 #define ATOM_EDID_RAW_DATASIZE          256         //In Bytes
2180 #define ATOM_HWICON_SURFACE_SIZE        4096        //In Bytes
2181 #define ATOM_HWICON_INFOTABLE_SIZE      32
2182 #define MAX_DTD_MODE_IN_VRAM            6
2183 #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE  (MAX_DTD_MODE_IN_VRAM*28)    //28= (SIZEOF ATOM_DTD_FORMAT)
2184 #define ATOM_STD_MODE_SUPPORT_TBL_SIZE  32*8                         //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT)
2185 #define DFP_ENCODER_TYPE_OFFSET                                 0x80
2186 #define DP_ENCODER_LANE_NUM_OFFSET                      0x84
2187 #define DP_ENCODER_LINK_RATE_OFFSET                     0x88
2188
2189 #define ATOM_HWICON1_SURFACE_ADDR       0
2190 #define ATOM_HWICON2_SURFACE_ADDR       (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
2191 #define ATOM_HWICON_INFOTABLE_ADDR      (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
2192 #define ATOM_CRT1_EDID_ADDR             (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)
2193 #define ATOM_CRT1_DTD_MODE_TBL_ADDR     (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
2194 #define ATOM_CRT1_STD_MODE_TBL_ADDR         (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
2195
2196 #define ATOM_LCD1_EDID_ADDR             (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
2197 #define ATOM_LCD1_DTD_MODE_TBL_ADDR     (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
2198 #define ATOM_LCD1_STD_MODE_TBL_ADDR     (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
2199
2200 #define ATOM_TV1_DTD_MODE_TBL_ADDR      (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
2201
2202 #define ATOM_DFP1_EDID_ADDR             (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
2203 #define ATOM_DFP1_DTD_MODE_TBL_ADDR     (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
2204 #define ATOM_DFP1_STD_MODE_TBL_ADDR         (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
2205
2206 #define ATOM_CRT2_EDID_ADDR             (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
2207 #define ATOM_CRT2_DTD_MODE_TBL_ADDR     (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
2208 #define ATOM_CRT2_STD_MODE_TBL_ADDR         (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
2209
2210 #define ATOM_LCD2_EDID_ADDR             (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
2211 #define ATOM_LCD2_DTD_MODE_TBL_ADDR     (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
2212 #define ATOM_LCD2_STD_MODE_TBL_ADDR     (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
2213
2214 #define ATOM_TV2_EDID_ADDR              (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
2215 #define ATOM_TV2_DTD_MODE_TBL_ADDR      (ATOM_TV2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
2216 #define ATOM_TV2_STD_MODE_TBL_ADDR        (ATOM_TV2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
2217
2218 #define ATOM_DFP2_EDID_ADDR             (ATOM_TV2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
2219 #define ATOM_DFP2_DTD_MODE_TBL_ADDR     (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
2220 #define ATOM_DFP2_STD_MODE_TBL_ADDR     (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
2221
2222 #define ATOM_CV_EDID_ADDR               (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
2223 #define ATOM_CV_DTD_MODE_TBL_ADDR       (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
2224 #define ATOM_CV_STD_MODE_TBL_ADDR       (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
2225
2226 #define ATOM_DFP3_EDID_ADDR             (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
2227 #define ATOM_DFP3_DTD_MODE_TBL_ADDR     (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
2228 #define ATOM_DFP3_STD_MODE_TBL_ADDR     (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
2229
2230 #define ATOM_DP_TRAINING_TBL_ADDR                               (ATOM_DFP3_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE)
2231
2232 #define ATOM_STACK_STORAGE_START        (ATOM_DP_TRAINING_TBL_ADDR+256)
2233 #define ATOM_STACK_STORAGE_END          ATOM_STACK_STORAGE_START+512
2234
2235 //The size below is in Kb!
2236 #define ATOM_VRAM_RESERVE_SIZE         ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)
2237
2238 #define ATOM_VRAM_OPERATION_FLAGS_MASK         0xC0000000L
2239 #define ATOM_VRAM_OPERATION_FLAGS_SHIFT        30
2240 #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION   0x1
2241 #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION      0x0
2242
2243 #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO                       1
2244
2245 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO
2246 {
2247   ULONG   ulStartAddrUsedByFirmware;
2248   USHORT  usFirmwareUseInKb;
2249   USHORT  usReserved;
2250 }ATOM_FIRMWARE_VRAM_RESERVE_INFO;
2251
2252 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE
2253 {
2254   ATOM_COMMON_TABLE_HEADER sHeader;
2255   ATOM_FIRMWARE_VRAM_RESERVE_INFO       asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
2256 }ATOM_VRAM_USAGE_BY_FIRMWARE;
2257
2258 /**************************************************************************/
2259 //GPIO Pin lut table definition
2260 typedef struct _ATOM_GPIO_PIN_ASSIGNMENT
2261 {
2262   USHORT                   usGpioPin_AIndex;
2263   UCHAR                    ucGpioPinBitShift;
2264   UCHAR                    ucGPIO_ID;
2265 }ATOM_GPIO_PIN_ASSIGNMENT;
2266
2267 typedef struct _ATOM_GPIO_PIN_LUT
2268 {
2269   ATOM_COMMON_TABLE_HEADER  sHeader;
2270   ATOM_GPIO_PIN_ASSIGNMENT      asGPIO_Pin[1];
2271 }ATOM_GPIO_PIN_LUT;
2272
2273 /**************************************************************************/
2274
2275
2276 #define GPIO_PIN_ACTIVE_HIGH          0x1
2277
2278 #define MAX_SUPPORTED_CV_STANDARDS    5
2279
2280 // definitions for ATOM_D_INFO.ucSettings
2281 #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK  0x1F    // [4:0]
2282 #define ATOM_GPIO_SETTINGS_RESERVED_MASK  0x60    // [6:5] = must be zeroed out
2283 #define ATOM_GPIO_SETTINGS_ACTIVE_MASK    0x80    // [7]
2284
2285 typedef struct _ATOM_GPIO_INFO
2286 {
2287   USHORT  usAOffset;
2288   UCHAR   ucSettings;
2289   UCHAR   ucReserved;
2290 }ATOM_GPIO_INFO;
2291
2292 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector)
2293 #define ATOM_CV_RESTRICT_FORMAT_SELECTION           0x2
2294
2295 // definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i
2296 #define ATOM_GPIO_DEFAULT_MODE_EN                   0x80 //[7];
2297 #define ATOM_GPIO_SETTING_PERMODE_MASK              0x7F //[6:0]
2298
2299 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode
2300 //Line 3 out put 5V.
2301 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A       0x01     //represent gpio 3 state for 16:9
2302 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B       0x02     //represent gpio 4 state for 16:9
2303 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT   0x0
2304
2305 //Line 3 out put 2.2V
2306 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04     //represent gpio 3 state for 4:3 Letter box
2307 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08     //represent gpio 4 state for 4:3 Letter box
2308 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2
2309
2310 //Line 3 out put 0V
2311 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A        0x10     //represent gpio 3 state for 4:3
2312 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B        0x20     //represent gpio 4 state for 4:3
2313 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT    0x4
2314
2315 #define ATOM_CV_LINE3_ASPECTRATIO_MASK              0x3F     // bit [5:0]
2316
2317 #define ATOM_CV_LINE3_ASPECTRATIO_EXIST             0x80     //bit 7
2318
2319 //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.
2320 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A   3   //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
2321 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B   4   //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
2322
2323
2324 typedef struct _ATOM_COMPONENT_VIDEO_INFO
2325 {
2326   ATOM_COMMON_TABLE_HEADER sHeader;
2327   USHORT             usMask_PinRegisterIndex;
2328   USHORT             usEN_PinRegisterIndex;
2329   USHORT             usY_PinRegisterIndex;
2330   USHORT             usA_PinRegisterIndex;
2331   UCHAR              ucBitShift;
2332   UCHAR              ucPinActiveState;  //ucPinActiveState: Bit0=1 active high, =0 active low
2333   ATOM_DTD_FORMAT    sReserved;         // must be zeroed out
2334   UCHAR              ucMiscInfo;
2335   UCHAR              uc480i;
2336   UCHAR              uc480p;
2337   UCHAR              uc720p;
2338   UCHAR              uc1080i;
2339   UCHAR              ucLetterBoxMode;
2340   UCHAR              ucReserved[3];
2341   UCHAR              ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
2342   ATOM_GPIO_INFO     aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
2343   ATOM_DTD_FORMAT    aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
2344 }ATOM_COMPONENT_VIDEO_INFO;
2345
2346 //ucTableFormatRevision=2
2347 //ucTableContentRevision=1
2348 typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21
2349 {
2350   ATOM_COMMON_TABLE_HEADER sHeader;
2351   UCHAR              ucMiscInfo;
2352   UCHAR              uc480i;
2353   UCHAR              uc480p;
2354   UCHAR              uc720p;
2355   UCHAR              uc1080i;
2356   UCHAR              ucReserved;
2357   UCHAR              ucLetterBoxMode;
2358   UCHAR              ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
2359   ATOM_GPIO_INFO     aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
2360   ATOM_DTD_FORMAT    aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
2361 }ATOM_COMPONENT_VIDEO_INFO_V21;
2362
2363 #define ATOM_COMPONENT_VIDEO_INFO_LAST  ATOM_COMPONENT_VIDEO_INFO_V21
2364
2365 /**************************************************************************/
2366 //Object table starts here
2367 typedef struct _ATOM_OBJECT_HEADER
2368 {
2369   ATOM_COMMON_TABLE_HEADER      sHeader;
2370   USHORT                    usDeviceSupport;
2371   USHORT                    usConnectorObjectTableOffset;
2372   USHORT                    usRouterObjectTableOffset;
2373   USHORT                    usEncoderObjectTableOffset;
2374   USHORT                    usProtectionObjectTableOffset; //only available when Protection block is independent.
2375   USHORT                    usDisplayPathTableOffset;
2376 }ATOM_OBJECT_HEADER;
2377
2378
2379 typedef struct  _ATOM_DISPLAY_OBJECT_PATH
2380 {
2381   USHORT    usDeviceTag;                                   //supported device
2382   USHORT    usSize;                                        //the size of ATOM_DISPLAY_OBJECT_PATH
2383   USHORT    usConnObjectId;                                //Connector Object ID
2384   USHORT    usGPUObjectId;                                 //GPU ID
2385   USHORT    usGraphicObjIds[1];                             //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.
2386 }ATOM_DISPLAY_OBJECT_PATH;
2387
2388 typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE
2389 {
2390   UCHAR                           ucNumOfDispPath;
2391   UCHAR                           ucVersion;
2392   UCHAR                           ucPadding[2];
2393   ATOM_DISPLAY_OBJECT_PATH        asDispPath[1];
2394 }ATOM_DISPLAY_OBJECT_PATH_TABLE;
2395
2396
2397 typedef struct _ATOM_OBJECT                                //each object has this structure
2398 {
2399   USHORT              usObjectID;
2400   USHORT              usSrcDstTableOffset;
2401   USHORT              usRecordOffset;                     //this pointing to a bunch of records defined below
2402   USHORT              usReserved;
2403 }ATOM_OBJECT;
2404
2405 typedef struct _ATOM_OBJECT_TABLE                         //Above 4 object table offset pointing to a bunch of objects all have this structure
2406 {
2407   UCHAR               ucNumberOfObjects;
2408   UCHAR               ucPadding[3];
2409   ATOM_OBJECT         asObjects[1];
2410 }ATOM_OBJECT_TABLE;
2411
2412 typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT         //usSrcDstTableOffset pointing to this structure
2413 {
2414   UCHAR               ucNumberOfSrc;
2415   USHORT              usSrcObjectID[1];
2416   UCHAR               ucNumberOfDst;
2417   USHORT              usDstObjectID[1];
2418 }ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
2419
2420
2421 //Related definitions, all records are differnt but they have a commond header
2422 typedef struct _ATOM_COMMON_RECORD_HEADER
2423 {
2424   UCHAR               ucRecordType;                      //An emun to indicate the record type
2425   UCHAR               ucRecordSize;                      //The size of the whole record in byte
2426 }ATOM_COMMON_RECORD_HEADER;
2427
2428
2429 #define ATOM_I2C_RECORD_TYPE                           1
2430 #define ATOM_HPD_INT_RECORD_TYPE                       2
2431 #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE             3
2432 #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE          4
2433 #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE             5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
2434 #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE          6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
2435 #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE      7
2436 #define ATOM_JTAG_RECORD_TYPE                          8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
2437 #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE              9
2438 #define ATOM_ENCODER_DVO_CF_RECORD_TYPE               10
2439 #define ATOM_CONNECTOR_CF_RECORD_TYPE                 11
2440 #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE       12
2441 #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE  13
2442 #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE                         14
2443 #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE                                  15
2444
2445 //Must be updated when new record type is added,equal to that record definition!
2446 #define ATOM_MAX_OBJECT_RECORD_NUMBER             ATOM_CONNECTOR_CF_RECORD_TYPE
2447
2448 typedef struct  _ATOM_I2C_RECORD
2449 {
2450   ATOM_COMMON_RECORD_HEADER   sheader;
2451   ATOM_I2C_ID_CONFIG          sucI2cId;
2452   UCHAR                       ucI2CAddr;              //The slave address, it's 0 when the record is attached to connector for DDC
2453 }ATOM_I2C_RECORD;
2454
2455 typedef struct  _ATOM_HPD_INT_RECORD
2456 {
2457   ATOM_COMMON_RECORD_HEADER   sheader;
2458   UCHAR                       ucHPDIntGPIOID;         //Corresponding block in GPIO_PIN_INFO table gives the pin info
2459   UCHAR                       ucPluggged_PinState;
2460 }ATOM_HPD_INT_RECORD;
2461
2462
2463 typedef struct  _ATOM_OUTPUT_PROTECTION_RECORD
2464 {
2465   ATOM_COMMON_RECORD_HEADER   sheader;
2466   UCHAR                       ucProtectionFlag;
2467   UCHAR                       ucReserved;
2468 }ATOM_OUTPUT_PROTECTION_RECORD;
2469
2470 typedef struct  _ATOM_CONNECTOR_DEVICE_TAG
2471 {
2472   ULONG                       ulACPIDeviceEnum;       //Reserved for now
2473   USHORT                      usDeviceID;             //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"
2474   USHORT                      usPadding;
2475 }ATOM_CONNECTOR_DEVICE_TAG;
2476
2477 typedef struct  _ATOM_CONNECTOR_DEVICE_TAG_RECORD
2478 {
2479   ATOM_COMMON_RECORD_HEADER   sheader;
2480   UCHAR                       ucNumberOfDevice;
2481   UCHAR                       ucReserved;
2482   ATOM_CONNECTOR_DEVICE_TAG   asDeviceTag[1];         //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation
2483 }ATOM_CONNECTOR_DEVICE_TAG_RECORD;
2484
2485
2486 typedef struct  _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
2487 {
2488   ATOM_COMMON_RECORD_HEADER   sheader;
2489   UCHAR                                                     ucConfigGPIOID;
2490   UCHAR                                                     ucConfigGPIOState;      //Set to 1 when it's active high to enable external flow in
2491   UCHAR                       ucFlowinGPIPID;
2492   UCHAR                       ucExtInGPIPID;
2493 }ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD;
2494
2495 typedef struct  _ATOM_ENCODER_FPGA_CONTROL_RECORD
2496 {
2497   ATOM_COMMON_RECORD_HEADER   sheader;
2498   UCHAR                       ucCTL1GPIO_ID;
2499   UCHAR                       ucCTL1GPIOState;        //Set to 1 when it's active high
2500   UCHAR                       ucCTL2GPIO_ID;
2501   UCHAR                       ucCTL2GPIOState;        //Set to 1 when it's active high
2502   UCHAR                       ucCTL3GPIO_ID;
2503   UCHAR                       ucCTL3GPIOState;        //Set to 1 when it's active high
2504   UCHAR                       ucCTLFPGA_IN_ID;
2505   UCHAR                       ucPadding[3];
2506 }ATOM_ENCODER_FPGA_CONTROL_RECORD;
2507
2508 typedef struct  _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
2509 {
2510   ATOM_COMMON_RECORD_HEADER   sheader;
2511   UCHAR                       ucGPIOID;               //Corresponding block in GPIO_PIN_INFO table gives the pin info
2512   UCHAR                       ucTVActiveState;        //Indicating when the pin==0 or 1 when TV is connected
2513 }ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD;
2514
2515 typedef struct  _ATOM_JTAG_RECORD
2516 {
2517   ATOM_COMMON_RECORD_HEADER   sheader;
2518   UCHAR                       ucTMSGPIO_ID;
2519   UCHAR                       ucTMSGPIOState;         //Set to 1 when it's active high
2520   UCHAR                       ucTCKGPIO_ID;
2521   UCHAR                       ucTCKGPIOState;         //Set to 1 when it's active high
2522   UCHAR                       ucTDOGPIO_ID;
2523   UCHAR                       ucTDOGPIOState;         //Set to 1 when it's active high
2524   UCHAR                       ucTDIGPIO_ID;
2525   UCHAR                       ucTDIGPIOState;         //Set to 1 when it's active high
2526   UCHAR                       ucPadding[2];
2527 }ATOM_JTAG_RECORD;
2528
2529
2530 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
2531 typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR
2532 {
2533   UCHAR                       ucGPIOID;               // GPIO_ID, find the corresponding ID in GPIO_LUT table
2534   UCHAR                       ucGPIO_PinState;        // Pin state showing how to set-up the pin
2535 }ATOM_GPIO_PIN_CONTROL_PAIR;
2536
2537 typedef struct  _ATOM_OBJECT_GPIO_CNTL_RECORD
2538 {
2539   ATOM_COMMON_RECORD_HEADER   sheader;
2540   UCHAR                       ucFlags;                // Future expnadibility
2541   UCHAR                       ucNumberOfPins;         // Number of GPIO pins used to control the object
2542   ATOM_GPIO_PIN_CONTROL_PAIR  asGpio[1];              // the real gpio pin pair determined by number of pins ucNumberOfPins
2543 }ATOM_OBJECT_GPIO_CNTL_RECORD;
2544
2545 //Definitions for GPIO pin state
2546 #define GPIO_PIN_TYPE_INPUT             0x00
2547 #define GPIO_PIN_TYPE_OUTPUT            0x10
2548 #define GPIO_PIN_TYPE_HW_CONTROL        0x20
2549
2550 //For GPIO_PIN_TYPE_OUTPUT the following is defined
2551 #define GPIO_PIN_OUTPUT_STATE_MASK      0x01
2552 #define GPIO_PIN_OUTPUT_STATE_SHIFT     0
2553 #define GPIO_PIN_STATE_ACTIVE_LOW       0x0
2554 #define GPIO_PIN_STATE_ACTIVE_HIGH      0x1
2555
2556 typedef struct  _ATOM_ENCODER_DVO_CF_RECORD
2557 {
2558   ATOM_COMMON_RECORD_HEADER   sheader;
2559   ULONG                       ulStrengthControl;      // DVOA strength control for CF
2560   UCHAR                       ucPadding[2];
2561 }ATOM_ENCODER_DVO_CF_RECORD;
2562
2563 // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle
2564 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA   1
2565 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB   2
2566
2567 typedef struct  _ATOM_CONNECTOR_CF_RECORD
2568 {
2569   ATOM_COMMON_RECORD_HEADER   sheader;
2570   USHORT                      usMaxPixClk;
2571   UCHAR                       ucFlowCntlGpioId;
2572   UCHAR                       ucSwapCntlGpioId;
2573   UCHAR                       ucConnectedDvoBundle;
2574   UCHAR                       ucPadding;
2575 }ATOM_CONNECTOR_CF_RECORD;
2576
2577 typedef struct  _ATOM_CONNECTOR_HARDCODE_DTD_RECORD
2578 {
2579   ATOM_COMMON_RECORD_HEADER   sheader;
2580         ATOM_DTD_FORMAT                                                 asTiming;
2581 }ATOM_CONNECTOR_HARDCODE_DTD_RECORD;
2582
2583 typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD
2584 {
2585   ATOM_COMMON_RECORD_HEADER   sheader;                //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE
2586   UCHAR                       ucSubConnectorType;     //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A
2587   UCHAR                       ucReserved;
2588 }ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD;
2589
2590
2591 typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD
2592 {
2593         ATOM_COMMON_RECORD_HEADER   sheader;
2594         UCHAR                                                                                           ucMuxType;                                                      //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state
2595         UCHAR                                                                                           ucMuxControlPin;
2596         UCHAR                                                                                           ucMuxState[2];                                  //for alligment purpose
2597 }ATOM_ROUTER_DDC_PATH_SELECT_RECORD;
2598
2599 typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
2600 {
2601         ATOM_COMMON_RECORD_HEADER   sheader;
2602         UCHAR                                                                                           ucMuxType;
2603         UCHAR                                                                                           ucMuxControlPin;
2604         UCHAR                                                                                           ucMuxState[2];                                  //for alligment purpose
2605 }ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD;
2606
2607 // define ucMuxType
2608 #define ATOM_ROUTER_MUX_PIN_STATE_MASK                                                          0x0f
2609 #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT             0x01
2610
2611 /**************************************************************************/
2612 //ASIC voltage data table starts here
2613
2614 typedef struct  _ATOM_VOLTAGE_INFO_HEADER
2615 {
2616    USHORT   usVDDCBaseLevel;                //In number of 50mv unit
2617    USHORT   usReserved;                     //For possible extension table offset
2618    UCHAR    ucNumOfVoltageEntries;
2619    UCHAR    ucBytesPerVoltageEntry;
2620    UCHAR    ucVoltageStep;                  //Indicating in how many mv increament is one step, 0.5mv unit
2621    UCHAR    ucDefaultVoltageEntry;
2622    UCHAR    ucVoltageControlI2cLine;
2623    UCHAR    ucVoltageControlAddress;
2624    UCHAR    ucVoltageControlOffset;
2625 }ATOM_VOLTAGE_INFO_HEADER;
2626
2627 typedef struct  _ATOM_VOLTAGE_INFO
2628 {
2629    ATOM_COMMON_TABLE_HEADER     sHeader;
2630    ATOM_VOLTAGE_INFO_HEADER viHeader;
2631    UCHAR    ucVoltageEntries[64];            //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry
2632 }ATOM_VOLTAGE_INFO;
2633
2634
2635 typedef struct  _ATOM_VOLTAGE_FORMULA
2636 {
2637    USHORT   usVoltageBaseLevel;             // In number of 1mv unit
2638    USHORT   usVoltageStep;                  // Indicating in how many mv increament is one step, 1mv unit
2639          UCHAR          ucNumOfVoltageEntries;                                  // Number of Voltage Entry, which indicate max Voltage
2640          UCHAR          ucFlag;                                                                                                 // bit0=0 :step is 1mv =1 0.5mv
2641          UCHAR          ucBaseVID;                                                                                      // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep
2642          UCHAR          ucReserved;
2643          UCHAR          ucVIDAdjustEntries[32];                                 // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries
2644 }ATOM_VOLTAGE_FORMULA;
2645
2646 typedef struct _ATOM_VOLTAGE_CONTROL
2647 {
2648         UCHAR            ucVoltageControlId;                                                    //Indicate it is controlled by I2C or GPIO or HW state machine
2649   UCHAR    ucVoltageControlI2cLine;
2650   UCHAR    ucVoltageControlAddress;
2651   UCHAR    ucVoltageControlOffset;
2652   USHORT   usGpioPin_AIndex;                                                            //GPIO_PAD register index
2653   UCHAR    ucGpioPinBitShift[9];                                                //at most 8 pin support 255 VIDs, termintate with 0xff
2654         UCHAR            ucReserved;
2655 }ATOM_VOLTAGE_CONTROL;
2656
2657 // Define ucVoltageControlId
2658 #define VOLTAGE_CONTROLLED_BY_HW                                                        0x00
2659 #define VOLTAGE_CONTROLLED_BY_I2C_MASK                          0x7F
2660 #define VOLTAGE_CONTROLLED_BY_GPIO                                              0x80
2661 #define VOLTAGE_CONTROL_ID_LM64                                                         0x01                                                                    //I2C control, used for R5xx Core Voltage
2662 #define VOLTAGE_CONTROL_ID_DAC                                                          0x02                                                                    //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI
2663 #define VOLTAGE_CONTROL_ID_VT116xM                                              0x03                                                                    //I2C control, used for R6xx Core Voltage
2664 #define VOLTAGE_CONTROL_ID_DS4402                                                       0x04
2665
2666 typedef struct  _ATOM_VOLTAGE_OBJECT
2667 {
2668          UCHAR          ucVoltageType;                                                                  //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
2669          UCHAR          ucSize;                                                                                                 //Size of Object
2670          ATOM_VOLTAGE_CONTROL                   asControl;                      //describ how to control
2671          ATOM_VOLTAGE_FORMULA                   asFormula;                      //Indicate How to convert real Voltage to VID
2672 }ATOM_VOLTAGE_OBJECT;
2673
2674 typedef struct  _ATOM_VOLTAGE_OBJECT_INFO
2675 {
2676    ATOM_COMMON_TABLE_HEADER     sHeader;
2677          ATOM_VOLTAGE_OBJECT                    asVoltageObj[3];        //Info for Voltage control
2678 }ATOM_VOLTAGE_OBJECT_INFO;
2679
2680 typedef struct  _ATOM_LEAKID_VOLTAGE
2681 {
2682         UCHAR           ucLeakageId;
2683         UCHAR           ucReserved;
2684         USHORT  usVoltage;
2685 }ATOM_LEAKID_VOLTAGE;
2686
2687 typedef struct  _ATOM_ASIC_PROFILE_VOLTAGE
2688 {
2689         UCHAR           ucProfileId;
2690         UCHAR           ucReserved;
2691         USHORT  usSize;
2692         USHORT  usEfuseSpareStartAddr;
2693         USHORT  usFuseIndex[8];                                                                                         //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id,
2694         ATOM_LEAKID_VOLTAGE                                     asLeakVol[2];                   //Leakid and relatd voltage
2695 }ATOM_ASIC_PROFILE_VOLTAGE;
2696
2697 //ucProfileId
2698 #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE                      1
2699 #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE                  1
2700 #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE                                      2
2701
2702 typedef struct  _ATOM_ASIC_PROFILING_INFO
2703 {
2704   ATOM_COMMON_TABLE_HEADER                      asHeader;
2705         ATOM_ASIC_PROFILE_VOLTAGE                       asVoltage;
2706 }ATOM_ASIC_PROFILING_INFO;
2707
2708 typedef struct _ATOM_POWER_SOURCE_OBJECT
2709 {
2710         UCHAR   ucPwrSrcId;                                                                                                     // Power source
2711         UCHAR   ucPwrSensorType;                                                                                // GPIO, I2C or none
2712         UCHAR   ucPwrSensId;                                                                                      // if GPIO detect, it is GPIO id,  if I2C detect, it is I2C id
2713         UCHAR   ucPwrSensSlaveAddr;                                                                     // Slave address if I2C detect
2714         UCHAR ucPwrSensRegIndex;                                                                        // I2C register Index if I2C detect
2715         UCHAR ucPwrSensRegBitMask;                                                              // detect which bit is used if I2C detect
2716         UCHAR   ucPwrSensActiveState;                                                           // high active or low active
2717         UCHAR   ucReserve[3];                                                                                           // reserve
2718         USHORT usSensPwr;                                                                                                       // in unit of watt
2719 }ATOM_POWER_SOURCE_OBJECT;
2720
2721 typedef struct _ATOM_POWER_SOURCE_INFO
2722 {
2723                 ATOM_COMMON_TABLE_HEADER                asHeader;
2724                 UCHAR                                                                                           asPwrbehave[16];
2725                 ATOM_POWER_SOURCE_OBJECT                asPwrObj[1];
2726 }ATOM_POWER_SOURCE_INFO;
2727
2728
2729 //Define ucPwrSrcId
2730 #define POWERSOURCE_PCIE_ID1                                            0x00
2731 #define POWERSOURCE_6PIN_CONNECTOR_ID1  0x01
2732 #define POWERSOURCE_8PIN_CONNECTOR_ID1  0x02
2733 #define POWERSOURCE_6PIN_CONNECTOR_ID2  0x04
2734 #define POWERSOURCE_8PIN_CONNECTOR_ID2  0x08
2735
2736 //define ucPwrSensorId
2737 #define POWER_SENSOR_ALWAYS                                                     0x00
2738 #define POWER_SENSOR_GPIO                                                               0x01
2739 #define POWER_SENSOR_I2C                                                                0x02
2740
2741 /**************************************************************************/
2742 // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design
2743 //Memory SS Info Table
2744 //Define Memory Clock SS chip ID
2745 #define ICS91719  1
2746 #define ICS91720  2
2747
2748 //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
2749 typedef struct _ATOM_I2C_DATA_RECORD
2750 {
2751   UCHAR         ucNunberOfBytes;                                              //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
2752   UCHAR         ucI2CData[1];                                                 //I2C data in bytes, should be less than 16 bytes usually
2753 }ATOM_I2C_DATA_RECORD;
2754
2755
2756 //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information
2757 typedef struct _ATOM_I2C_DEVICE_SETUP_INFO
2758 {
2759   ATOM_I2C_ID_CONFIG_ACCESS       sucI2cId;               //I2C line and HW/SW assisted cap.
2760   UCHAR                                 ucSSChipID;             //SS chip being used
2761   UCHAR                                 ucSSChipSlaveAddr;      //Slave Address to set up this SS chip
2762   UCHAR                           ucNumOfI2CDataRecords;  //number of data block
2763   ATOM_I2C_DATA_RECORD            asI2CData[1];
2764 }ATOM_I2C_DEVICE_SETUP_INFO;
2765
2766 //==========================================================================================
2767 typedef struct  _ATOM_ASIC_MVDD_INFO
2768 {
2769   ATOM_COMMON_TABLE_HEADER            sHeader;
2770   ATOM_I2C_DEVICE_SETUP_INFO      asI2CSetup[1];
2771 }ATOM_ASIC_MVDD_INFO;
2772
2773 //==========================================================================================
2774 #define ATOM_MCLK_SS_INFO         ATOM_ASIC_MVDD_INFO
2775
2776 //==========================================================================================
2777 /**************************************************************************/
2778
2779 typedef struct _ATOM_ASIC_SS_ASSIGNMENT
2780 {
2781         ULONG                                                           ulTargetClockRange;                                             //Clock Out frequence (VCO ), in unit of 10Khz
2782   USHORT              usSpreadSpectrumPercentage;               //in unit of 0.01%
2783         USHORT                                                  usSpreadRateInKhz;                                              //in unit of kHz, modulation freq
2784   UCHAR               ucClockIndication;                                          //Indicate which clock source needs SS
2785         UCHAR                                                           ucSpreadSpectrumMode;                                   //Bit1=0 Down Spread,=1 Center Spread.
2786         UCHAR                                                           ucReserved[2];
2787 }ATOM_ASIC_SS_ASSIGNMENT;
2788
2789 //Define ucSpreadSpectrumType
2790 #define ASIC_INTERNAL_MEMORY_SS                 1
2791 #define ASIC_INTERNAL_ENGINE_SS                 2
2792 #define ASIC_INTERNAL_UVD_SS                            3
2793
2794 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{
2795   ATOM_COMMON_TABLE_HEADER            sHeader;
2796   ATOM_ASIC_SS_ASSIGNMENT                     asSpreadSpectrum[4];
2797 }ATOM_ASIC_INTERNAL_SS_INFO;
2798
2799 //==============================Scratch Pad Definition Portion===============================
2800 #define ATOM_DEVICE_CONNECT_INFO_DEF  0
2801 #define ATOM_ROM_LOCATION_DEF         1
2802 #define ATOM_TV_STANDARD_DEF          2
2803 #define ATOM_ACTIVE_INFO_DEF          3
2804 #define ATOM_LCD_INFO_DEF             4
2805 #define ATOM_DOS_REQ_INFO_DEF         5
2806 #define ATOM_ACC_CHANGE_INFO_DEF      6
2807 #define ATOM_DOS_MODE_INFO_DEF        7
2808 #define ATOM_I2C_CHANNEL_STATUS_DEF   8
2809 #define ATOM_I2C_CHANNEL_STATUS1_DEF  9
2810
2811
2812 // BIOS_0_SCRATCH Definition
2813 #define ATOM_S0_CRT1_MONO               0x00000001L
2814 #define ATOM_S0_CRT1_COLOR              0x00000002L
2815 #define ATOM_S0_CRT1_MASK               (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR)
2816
2817 #define ATOM_S0_TV1_COMPOSITE_A         0x00000004L
2818 #define ATOM_S0_TV1_SVIDEO_A            0x00000008L
2819 #define ATOM_S0_TV1_MASK_A              (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A)
2820
2821 #define ATOM_S0_CV_A                    0x00000010L
2822 #define ATOM_S0_CV_DIN_A                0x00000020L
2823 #define ATOM_S0_CV_MASK_A               (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A)
2824
2825
2826 #define ATOM_S0_CRT2_MONO               0x00000100L
2827 #define ATOM_S0_CRT2_COLOR              0x00000200L
2828 #define ATOM_S0_CRT2_MASK               (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR)
2829
2830 #define ATOM_S0_TV1_COMPOSITE           0x00000400L
2831 #define ATOM_S0_TV1_SVIDEO              0x00000800L
2832 #define ATOM_S0_TV1_SCART               0x00004000L
2833 #define ATOM_S0_TV1_MASK                (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART)
2834
2835 #define ATOM_S0_CV                      0x00001000L
2836 #define ATOM_S0_CV_DIN                  0x00002000L
2837 #define ATOM_S0_CV_MASK                 (ATOM_S0_CV+ATOM_S0_CV_DIN)
2838
2839
2840 #define ATOM_S0_DFP1                    0x00010000L
2841 #define ATOM_S0_DFP2                    0x00020000L
2842 #define ATOM_S0_LCD1                    0x00040000L
2843 #define ATOM_S0_LCD2                    0x00080000L
2844 #define ATOM_S0_TV2                     0x00100000L
2845 #define ATOM_S0_DFP3                                                                            0x00200000L
2846
2847 #define ATOM_S0_FAD_REGISTER_BUG        0x02000000L // If set, indicates we are running a PCIE asic with
2848                                                     // the FAD/HDP reg access bug.  Bit is read by DAL
2849
2850 #define ATOM_S0_THERMAL_STATE_MASK      0x1C000000L
2851 #define ATOM_S0_THERMAL_STATE_SHIFT     26
2852
2853 #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L
2854 #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29
2855
2856 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC     1
2857 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC     2
2858 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
2859
2860 //Byte aligned defintion for BIOS usage
2861 #define ATOM_S0_CRT1_MONOb0             0x01
2862 #define ATOM_S0_CRT1_COLORb0            0x02
2863 #define ATOM_S0_CRT1_MASKb0             (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
2864
2865 #define ATOM_S0_TV1_COMPOSITEb0         0x04
2866 #define ATOM_S0_TV1_SVIDEOb0            0x08
2867 #define ATOM_S0_TV1_MASKb0              (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0)
2868
2869 #define ATOM_S0_CVb0                    0x10
2870 #define ATOM_S0_CV_DINb0                0x20
2871 #define ATOM_S0_CV_MASKb0               (ATOM_S0_CVb0+ATOM_S0_CV_DINb0)
2872
2873 #define ATOM_S0_CRT2_MONOb1             0x01
2874 #define ATOM_S0_CRT2_COLORb1            0x02
2875 #define ATOM_S0_CRT2_MASKb1             (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1)
2876
2877 #define ATOM_S0_TV1_COMPOSITEb1         0x04
2878 #define ATOM_S0_TV1_SVIDEOb1            0x08
2879 #define ATOM_S0_TV1_SCARTb1             0x40
2880 #define ATOM_S0_TV1_MASKb1              (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1)
2881
2882 #define ATOM_S0_CVb1                    0x10
2883 #define ATOM_S0_CV_DINb1                0x20
2884 #define ATOM_S0_CV_MASKb1               (ATOM_S0_CVb1+ATOM_S0_CV_DINb1)
2885
2886 #define ATOM_S0_DFP1b2                  0x01
2887 #define ATOM_S0_DFP2b2                  0x02
2888 #define ATOM_S0_LCD1b2                  0x04
2889 #define ATOM_S0_LCD2b2                  0x08
2890 #define ATOM_S0_TV2b2                   0x10
2891 #define ATOM_S0_DFP3b2                                                                  0x20
2892
2893 #define ATOM_S0_THERMAL_STATE_MASKb3    0x1C
2894 #define ATOM_S0_THERMAL_STATE_SHIFTb3   2
2895
2896 #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0
2897 #define ATOM_S0_LCD1_SHIFT              18
2898
2899 // BIOS_1_SCRATCH Definition
2900 #define ATOM_S1_ROM_LOCATION_MASK       0x0000FFFFL
2901 #define ATOM_S1_PCI_BUS_DEV_MASK        0xFFFF0000L
2902
2903
2904 //      BIOS_2_SCRATCH Definition
2905 #define ATOM_S2_TV1_STANDARD_MASK       0x0000000FL
2906 #define ATOM_S2_CURRENT_BL_LEVEL_MASK   0x0000FF00L
2907 #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT  8
2908
2909 #define ATOM_S2_CRT1_DPMS_STATE         0x00010000L
2910 #define ATOM_S2_LCD1_DPMS_STATE         0x00020000L
2911 #define ATOM_S2_TV1_DPMS_STATE          0x00040000L
2912 #define ATOM_S2_DFP1_DPMS_STATE         0x00080000L
2913 #define ATOM_S2_CRT2_DPMS_STATE         0x00100000L
2914 #define ATOM_S2_LCD2_DPMS_STATE         0x00200000L
2915 #define ATOM_S2_TV2_DPMS_STATE          0x00400000L
2916 #define ATOM_S2_DFP2_DPMS_STATE         0x00800000L
2917 #define ATOM_S2_CV_DPMS_STATE           0x01000000L
2918 #define ATOM_S2_DFP3_DPMS_STATE                                 0x02000000L
2919
2920 #define ATOM_S2_DEVICE_DPMS_STATE       (ATOM_S2_CRT1_DPMS_STATE+ATOM_S2_LCD1_DPMS_STATE+ATOM_S2_TV1_DPMS_STATE+\
2921                                         ATOM_S2_DFP1I_DPMS_STATE+ATOM_S2_CRT2_DPMS_STATE+ATOM_S2_LCD2_DPMS_STATE+\
2922                                         ATOM_S2_TV2_DPMS_STATE+ATOM_S2_DFP1X_DPMS_STATE+ATOM_S2_CV_DPMS_STATE+\
2923                                         ATOM_S2_DFP3_DPMS_STATE)
2924
2925
2926 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK       0x0C000000L
2927 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26
2928 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE     0x10000000L
2929
2930 #define ATOM_S2_VRI_BRIGHT_ENABLE       0x20000000L
2931
2932 #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE     0x0
2933 #define ATOM_S2_DISPLAY_ROTATION_90_DEGREE    0x1
2934 #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE   0x2
2935 #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE   0x3
2936 #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30
2937 #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK   0xC0000000L
2938
2939
2940 //Byte aligned defintion for BIOS usage
2941 #define ATOM_S2_TV1_STANDARD_MASKb0     0x0F
2942 #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
2943 #define ATOM_S2_CRT1_DPMS_STATEb2       0x01
2944 #define ATOM_S2_LCD1_DPMS_STATEb2       0x02
2945 #define ATOM_S2_TV1_DPMS_STATEb2        0x04
2946 #define ATOM_S2_DFP1_DPMS_STATEb2       0x08
2947 #define ATOM_S2_CRT2_DPMS_STATEb2       0x10
2948 #define ATOM_S2_LCD2_DPMS_STATEb2       0x20
2949 #define ATOM_S2_TV2_DPMS_STATEb2        0x40
2950 #define ATOM_S2_DFP2_DPMS_STATEb2       0x80
2951 #define ATOM_S2_CV_DPMS_STATEb3         0x01
2952 #define ATOM_S2_DFP3_DPMS_STATEb3                               0x02
2953
2954 #define ATOM_S2_DEVICE_DPMS_MASKw1      0x3FF
2955 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3     0x0C
2956 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3   0x10
2957 #define ATOM_S2_VRI_BRIGHT_ENABLEb3     0x20
2958 #define ATOM_S2_ROTATION_STATE_MASKb3   0xC0
2959
2960
2961 // BIOS_3_SCRATCH Definition
2962 #define ATOM_S3_CRT1_ACTIVE             0x00000001L
2963 #define ATOM_S3_LCD1_ACTIVE             0x00000002L
2964 #define ATOM_S3_TV1_ACTIVE              0x00000004L
2965 #define ATOM_S3_DFP1_ACTIVE             0x00000008L
2966 #define ATOM_S3_CRT2_ACTIVE             0x00000010L
2967 #define ATOM_S3_LCD2_ACTIVE             0x00000020L
2968 #define ATOM_S3_TV2_ACTIVE              0x00000040L
2969 #define ATOM_S3_DFP2_ACTIVE             0x00000080L
2970 #define ATOM_S3_CV_ACTIVE               0x00000100L
2971 #define ATOM_S3_DFP3_ACTIVE                                                     0x00000200L
2972
2973 #define ATOM_S3_DEVICE_ACTIVE_MASK      0x000003FFL
2974
2975 #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE         0x00001000L
2976 #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L
2977
2978 #define ATOM_S3_CRT1_CRTC_ACTIVE        0x00010000L
2979 #define ATOM_S3_LCD1_CRTC_ACTIVE        0x00020000L
2980 #define ATOM_S3_TV1_CRTC_ACTIVE         0x00040000L
2981 #define ATOM_S3_DFP1_CRTC_ACTIVE        0x00080000L
2982 #define ATOM_S3_CRT2_CRTC_ACTIVE        0x00100000L
2983 #define ATOM_S3_LCD2_CRTC_ACTIVE        0x00200000L
2984 #define ATOM_S3_TV2_CRTC_ACTIVE         0x00400000L
2985 #define ATOM_S3_DFP2_CRTC_ACTIVE        0x00800000L
2986 #define ATOM_S3_CV_CRTC_ACTIVE          0x01000000L
2987 #define ATOM_S3_DFP3_CRTC_ACTIVE                                0x02000000L
2988
2989 #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x03FF0000L
2990 #define ATOM_S3_ASIC_GUI_ENGINE_HUNG    0x20000000L
2991 #define ATOM_S3_ALLOW_FAST_PWR_SWITCH   0x40000000L
2992 #define ATOM_S3_RQST_GPU_USE_MIN_PWR    0x80000000L
2993
2994 //Byte aligned defintion for BIOS usage
2995 #define ATOM_S3_CRT1_ACTIVEb0           0x01
2996 #define ATOM_S3_LCD1_ACTIVEb0           0x02
2997 #define ATOM_S3_TV1_ACTIVEb0            0x04
2998 #define ATOM_S3_DFP1_ACTIVEb0           0x08
2999 #define ATOM_S3_CRT2_ACTIVEb0           0x10
3000 #define ATOM_S3_LCD2_ACTIVEb0           0x20
3001 #define ATOM_S3_TV2_ACTIVEb0            0x40
3002 #define ATOM_S3_DFP2_ACTIVEb0           0x80
3003 #define ATOM_S3_CV_ACTIVEb1             0x01
3004 #define ATOM_S3_DFP3_ACTIVEb1                                           0x02
3005
3006 #define ATOM_S3_ACTIVE_CRTC1w0          0x3FF
3007
3008 #define ATOM_S3_CRT1_CRTC_ACTIVEb2      0x01
3009 #define ATOM_S3_LCD1_CRTC_ACTIVEb2      0x02
3010 #define ATOM_S3_TV1_CRTC_ACTIVEb2       0x04
3011 #define ATOM_S3_DFP1_CRTC_ACTIVEb2      0x08
3012 #define ATOM_S3_CRT2_CRTC_ACTIVEb2      0x10
3013 #define ATOM_S3_LCD2_CRTC_ACTIVEb2      0x20
3014 #define ATOM_S3_TV2_CRTC_ACTIVEb2       0x40
3015 #define ATOM_S3_DFP2_CRTC_ACTIVEb2      0x80
3016 #define ATOM_S3_CV_CRTC_ACTIVEb3        0x01
3017 #define ATOM_S3_DFP3_CRTC_ACTIVEb3                      0x02
3018
3019 #define ATOM_S3_ACTIVE_CRTC2w1          0x3FF
3020
3021 #define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3  0x20
3022 #define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40
3023 #define ATOM_S3_RQST_GPU_USE_MIN_PWRb3  0x80
3024
3025 // BIOS_4_SCRATCH Definition
3026 #define ATOM_S4_LCD1_PANEL_ID_MASK      0x000000FFL
3027 #define ATOM_S4_LCD1_REFRESH_MASK       0x0000FF00L
3028 #define ATOM_S4_LCD1_REFRESH_SHIFT      8
3029
3030
3031 //Byte aligned defintion for BIOS usage
3032 #define ATOM_S4_LCD1_PANEL_ID_MASKb0      0x0FF
3033 #define ATOM_S4_LCD1_REFRESH_MASKb1               ATOM_S4_LCD1_PANEL_ID_MASKb0
3034 #define ATOM_S4_VRAM_INFO_MASKb2        ATOM_S4_LCD1_PANEL_ID_MASKb0
3035
3036
3037 // BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!!
3038 #define ATOM_S5_DOS_REQ_CRT1b0          0x01
3039 #define ATOM_S5_DOS_REQ_LCD1b0          0x02
3040 #define ATOM_S5_DOS_REQ_TV1b0           0x04
3041 #define ATOM_S5_DOS_REQ_DFP1b0          0x08
3042 #define ATOM_S5_DOS_REQ_CRT2b0          0x10
3043 #define ATOM_S5_DOS_REQ_LCD2b0          0x20
3044 #define ATOM_S5_DOS_REQ_TV2b0           0x40
3045 #define ATOM_S5_DOS_REQ_DFP2b0          0x80
3046 #define ATOM_S5_DOS_REQ_CVb1            0x01
3047 #define ATOM_S5_DOS_REQ_DFP3b1                                  0x02
3048
3049 #define ATOM_S5_DOS_REQ_DEVICEw0        0x03FF
3050
3051 #define ATOM_S5_DOS_REQ_CRT1            0x0001
3052 #define ATOM_S5_DOS_REQ_LCD1            0x0002
3053 #define ATOM_S5_DOS_REQ_TV1             0x0004
3054 #define ATOM_S5_DOS_REQ_DFP1            0x0008
3055 #define ATOM_S5_DOS_REQ_CRT2            0x0010
3056 #define ATOM_S5_DOS_REQ_LCD2            0x0020
3057 #define ATOM_S5_DOS_REQ_TV2             0x0040
3058 #define ATOM_S5_DOS_REQ_DFP2            0x0080
3059 #define ATOM_S5_DOS_REQ_CV              0x0100
3060 #define ATOM_S5_DOS_REQ_DFP3                                            0x0200
3061
3062 #define ATOM_S5_DOS_FORCE_CRT1b2        ATOM_S5_DOS_REQ_CRT1b0
3063 #define ATOM_S5_DOS_FORCE_TV1b2         ATOM_S5_DOS_REQ_TV1b0
3064 #define ATOM_S5_DOS_FORCE_CRT2b2        ATOM_S5_DOS_REQ_CRT2b0
3065 #define ATOM_S5_DOS_FORCE_CVb3          ATOM_S5_DOS_REQ_CVb1
3066 #define ATOM_S5_DOS_FORCE_DEVICEw1      (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\
3067                                         (ATOM_S5_DOS_FORCE_CVb3<<8))
3068
3069 // BIOS_6_SCRATCH Definition
3070 #define ATOM_S6_DEVICE_CHANGE           0x00000001L
3071 #define ATOM_S6_SCALER_CHANGE           0x00000002L
3072 #define ATOM_S6_LID_CHANGE              0x00000004L
3073 #define ATOM_S6_DOCKING_CHANGE          0x00000008L
3074 #define ATOM_S6_ACC_MODE                0x00000010L
3075 #define ATOM_S6_EXT_DESKTOP_MODE        0x00000020L
3076 #define ATOM_S6_LID_STATE               0x00000040L
3077 #define ATOM_S6_DOCK_STATE              0x00000080L
3078 #define ATOM_S6_CRITICAL_STATE          0x00000100L
3079 #define ATOM_S6_HW_I2C_BUSY_STATE       0x00000200L
3080 #define ATOM_S6_THERMAL_STATE_CHANGE    0x00000400L
3081 #define ATOM_S6_INTERRUPT_SET_BY_BIOS   0x00000800L
3082 #define ATOM_S6_REQ_LCD_EXPANSION_FULL         0x00001000L //Normal expansion Request bit for LCD
3083 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO  0x00002000L //Aspect ratio expansion Request bit for LCD
3084
3085 #define ATOM_S6_DISPLAY_STATE_CHANGE    0x00004000L        //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion
3086 #define ATOM_S6_I2C_STATE_CHANGE        0x00008000L        //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion
3087
3088
3089 #define ATOM_S6_ACC_REQ_CRT1            0x00010000L
3090 #define ATOM_S6_ACC_REQ_LCD1            0x00020000L
3091 #define ATOM_S6_ACC_REQ_TV1             0x00040000L
3092 #define ATOM_S6_ACC_REQ_DFP1            0x00080000L
3093 #define ATOM_S6_ACC_REQ_CRT2            0x00100000L
3094 #define ATOM_S6_ACC_REQ_LCD2            0x00200000L
3095 #define ATOM_S6_ACC_REQ_TV2             0x00400000L
3096 #define ATOM_S6_ACC_REQ_DFP2            0x00800000L
3097 #define ATOM_S6_ACC_REQ_CV              0x01000000L
3098 #define ATOM_S6_ACC_REQ_DFP3                                            0x02000000L
3099
3100 #define ATOM_S6_ACC_REQ_MASK                0x03FF0000L
3101 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE    0x10000000L
3102 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH    0x20000000L
3103 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE       0x40000000L
3104 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK  0x80000000L
3105
3106 //Byte aligned defintion for BIOS usage
3107 #define ATOM_S6_DEVICE_CHANGEb0         0x01
3108 #define ATOM_S6_SCALER_CHANGEb0         0x02
3109 #define ATOM_S6_LID_CHANGEb0            0x04
3110 #define ATOM_S6_DOCKING_CHANGEb0        0x08
3111 #define ATOM_S6_ACC_MODEb0              0x10
3112 #define ATOM_S6_EXT_DESKTOP_MODEb0      0x20
3113 #define ATOM_S6_LID_STATEb0             0x40
3114 #define ATOM_S6_DOCK_STATEb0            0x80
3115 #define ATOM_S6_CRITICAL_STATEb1        0x01
3116 #define ATOM_S6_HW_I2C_BUSY_STATEb1     0x02
3117 #define ATOM_S6_THERMAL_STATE_CHANGEb1  0x04
3118 #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08
3119 #define ATOM_S6_REQ_LCD_EXPANSION_FULLb1        0x10
3120 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20
3121
3122 #define ATOM_S6_ACC_REQ_CRT1b2          0x01
3123 #define ATOM_S6_ACC_REQ_LCD1b2          0x02
3124 #define ATOM_S6_ACC_REQ_TV1b2           0x04
3125 #define ATOM_S6_ACC_REQ_DFP1b2          0x08
3126 #define ATOM_S6_ACC_REQ_CRT2b2          0x10
3127 #define ATOM_S6_ACC_REQ_LCD2b2          0x20
3128 #define ATOM_S6_ACC_REQ_TV2b2           0x40
3129 #define ATOM_S6_ACC_REQ_DFP2b2          0x80
3130 #define ATOM_S6_ACC_REQ_CVb3            0x01
3131 #define ATOM_S6_ACC_REQ_DFP3b3                                  0x02
3132
3133 #define ATOM_S6_ACC_REQ_DEVICEw1        ATOM_S5_DOS_REQ_DEVICEw0
3134 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10
3135 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20
3136 #define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3    0x40
3137 #define ATOM_S6_CONFIG_DISPLAY_CHANGEb3    0x80
3138
3139 #define ATOM_S6_DEVICE_CHANGE_SHIFT             0
3140 #define ATOM_S6_SCALER_CHANGE_SHIFT             1
3141 #define ATOM_S6_LID_CHANGE_SHIFT                2
3142 #define ATOM_S6_DOCKING_CHANGE_SHIFT            3
3143 #define ATOM_S6_ACC_MODE_SHIFT                  4
3144 #define ATOM_S6_EXT_DESKTOP_MODE_SHIFT          5
3145 #define ATOM_S6_LID_STATE_SHIFT                 6
3146 #define ATOM_S6_DOCK_STATE_SHIFT                7
3147 #define ATOM_S6_CRITICAL_STATE_SHIFT            8
3148 #define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT         9
3149 #define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT      10
3150 #define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT     11
3151 #define ATOM_S6_REQ_SCALER_SHIFT                12
3152 #define ATOM_S6_REQ_SCALER_ARATIO_SHIFT         13
3153 #define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT      14
3154 #define ATOM_S6_I2C_STATE_CHANGE_SHIFT          15
3155 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT  28
3156 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT  29
3157 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT     30
3158 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT     31
3159
3160 // BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!!
3161 #define ATOM_S7_DOS_MODE_TYPEb0             0x03
3162 #define ATOM_S7_DOS_MODE_VGAb0              0x00
3163 #define ATOM_S7_DOS_MODE_VESAb0             0x01
3164 #define ATOM_S7_DOS_MODE_EXTb0              0x02
3165 #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0      0x0C
3166 #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0     0xF0
3167 #define ATOM_S7_DOS_8BIT_DAC_ENb1           0x01
3168 #define ATOM_S7_DOS_MODE_NUMBERw1           0x0FFFF
3169
3170 #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT       8
3171
3172 // BIOS_8_SCRATCH Definition
3173 #define ATOM_S8_I2C_CHANNEL_BUSY_MASK       0x00000FFFF
3174 #define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK     0x0FFFF0000
3175
3176 #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT      0
3177 #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT       16
3178
3179 // BIOS_9_SCRATCH Definition
3180 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK
3181 #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK  0x0000FFFF
3182 #endif
3183 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK
3184 #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK    0xFFFF0000
3185 #endif
3186 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT
3187 #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0
3188 #endif
3189 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT
3190 #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT   16
3191 #endif
3192
3193
3194 #define ATOM_FLAG_SET                         0x20
3195 #define ATOM_FLAG_CLEAR                       0
3196 #define CLEAR_ATOM_S6_ACC_MODE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR)
3197 #define SET_ATOM_S6_DEVICE_CHANGE             ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET)
3198 #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE     ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET)
3199 #define SET_ATOM_S6_SCALER_CHANGE             ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET)
3200 #define SET_ATOM_S6_LID_CHANGE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET)
3201
3202 #define SET_ATOM_S6_LID_STATE                 ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET)
3203 #define CLEAR_ATOM_S6_LID_STATE               ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR)
3204
3205 #define SET_ATOM_S6_DOCK_CHANGE                           ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET)
3206 #define SET_ATOM_S6_DOCK_STATE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET)
3207 #define CLEAR_ATOM_S6_DOCK_STATE              ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR)
3208
3209 #define SET_ATOM_S6_THERMAL_STATE_CHANGE      ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET)
3210 #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE  ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET)
3211 #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS     ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET)
3212
3213 #define SET_ATOM_S6_CRITICAL_STATE            ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET)
3214 #define CLEAR_ATOM_S6_CRITICAL_STATE          ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR)
3215
3216 #define SET_ATOM_S6_REQ_SCALER                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET)
3217 #define CLEAR_ATOM_S6_REQ_SCALER              ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR )
3218
3219 #define SET_ATOM_S6_REQ_SCALER_ARATIO         ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET )
3220 #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO       ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR )
3221
3222 #define SET_ATOM_S6_I2C_STATE_CHANGE          ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
3223
3224 #define SET_ATOM_S6_DISPLAY_STATE_CHANGE      ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
3225
3226 #define SET_ATOM_S6_DEVICE_RECONFIG           ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET)
3227 #define CLEAR_ATOM_S0_LCD1                    ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )|  ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR )
3228 #define SET_ATOM_S7_DOS_8BIT_DAC_EN           ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET )
3229 #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN         ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR )
3230
3231 /****************************************************************************/
3232 //Portion II: Definitinos only used in Driver
3233 /****************************************************************************/
3234
3235 // Macros used by driver
3236
3237 #define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
3238
3239 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
3240 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)  ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
3241
3242 #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION
3243 #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION
3244
3245 /****************************************************************************/
3246 //Portion III: Definitinos only used in VBIOS
3247 /****************************************************************************/
3248 #define ATOM_DAC_SRC                                    0x80
3249 #define ATOM_SRC_DAC1                                   0
3250 #define ATOM_SRC_DAC2                                   0x80
3251
3252
3253 #ifdef  UEFI_BUILD
3254         #define USHORT  UTEMP
3255 #endif
3256
3257 typedef struct _MEMORY_PLLINIT_PARAMETERS
3258 {
3259   ULONG ulTargetMemoryClock; //In 10Khz unit
3260   UCHAR   ucAction;                                      //not define yet
3261   UCHAR   ucFbDiv_Hi;                            //Fbdiv Hi byte
3262   UCHAR   ucFbDiv;                                       //FB value
3263   UCHAR   ucPostDiv;                             //Post div
3264 }MEMORY_PLLINIT_PARAMETERS;
3265
3266 #define MEMORY_PLLINIT_PS_ALLOCATION  MEMORY_PLLINIT_PARAMETERS
3267
3268
3269 #define GPIO_PIN_WRITE                                                                                                  0x01
3270 #define GPIO_PIN_READ                                                                                                           0x00
3271
3272 typedef struct  _GPIO_PIN_CONTROL_PARAMETERS
3273 {
3274   UCHAR ucGPIO_ID;           //return value, read from GPIO pins
3275   UCHAR ucGPIOBitShift;      //define which bit in uGPIOBitVal need to be update
3276         UCHAR ucGPIOBitVal;                  //Set/Reset corresponding bit defined in ucGPIOBitMask
3277   UCHAR ucAction;                                    //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
3278 }GPIO_PIN_CONTROL_PARAMETERS;
3279
3280 typedef struct _ENABLE_SCALER_PARAMETERS
3281 {
3282   UCHAR ucScaler;            // ATOM_SCALER1, ATOM_SCALER2
3283   UCHAR ucEnable;            // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION
3284   UCHAR ucTVStandard;        //
3285   UCHAR ucPadding[1];
3286 }ENABLE_SCALER_PARAMETERS;
3287 #define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS
3288
3289 //ucEnable:
3290 #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION    0
3291 #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION  1
3292 #define SCALER_ENABLE_2TAP_ALPHA_MODE               2
3293 #define SCALER_ENABLE_MULTITAP_MODE                 3
3294
3295 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS
3296 {
3297   ULONG  usHWIconHorzVertPosn;        // Hardware Icon Vertical position
3298   UCHAR  ucHWIconVertOffset;          // Hardware Icon Vertical offset
3299   UCHAR  ucHWIconHorzOffset;          // Hardware Icon Horizontal offset
3300   UCHAR  ucSelection;                 // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2
3301   UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
3302 }ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS;
3303
3304 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION
3305 {
3306   ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS  sEnableIcon;
3307   ENABLE_CRTC_PARAMETERS                  sReserved;
3308 }ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION;
3309
3310 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS
3311 {
3312   USHORT usHight;                     // Image Hight
3313   USHORT usWidth;                     // Image Width
3314   UCHAR  ucSurface;                   // Surface 1 or 2
3315   UCHAR  ucPadding[3];
3316 }ENABLE_GRAPH_SURFACE_PARAMETERS;
3317
3318 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2
3319 {
3320   USHORT usHight;                     // Image Hight
3321   USHORT usWidth;                     // Image Width
3322   UCHAR  ucSurface;                   // Surface 1 or 2
3323   UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
3324   UCHAR  ucPadding[2];
3325 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2;
3326
3327 typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION
3328 {
3329   ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface;
3330   ENABLE_YUV_PS_ALLOCATION        sReserved; // Don't set this one
3331 }ENABLE_GRAPH_SURFACE_PS_ALLOCATION;
3332
3333 typedef struct _MEMORY_CLEAN_UP_PARAMETERS
3334 {
3335   USHORT  usMemoryStart;                //in 8Kb boundry, offset from memory base address
3336   USHORT  usMemorySize;                 //8Kb blocks aligned
3337 }MEMORY_CLEAN_UP_PARAMETERS;
3338 #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS
3339
3340 typedef struct  _GET_DISPLAY_SURFACE_SIZE_PARAMETERS
3341 {
3342   USHORT  usX_Size;                     //When use as input parameter, usX_Size indicates which CRTC
3343   USHORT  usY_Size;
3344 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS;
3345
3346 typedef struct _INDIRECT_IO_ACCESS
3347 {
3348   ATOM_COMMON_TABLE_HEADER sHeader;
3349   UCHAR                    IOAccessSequence[256];
3350 } INDIRECT_IO_ACCESS;
3351
3352 #define INDIRECT_READ              0x00
3353 #define INDIRECT_WRITE             0x80
3354
3355 #define INDIRECT_IO_MM             0
3356 #define INDIRECT_IO_PLL            1
3357 #define INDIRECT_IO_MC             2
3358 #define INDIRECT_IO_PCIE           3
3359 #define INDIRECT_IO_PCIEP          4
3360 #define INDIRECT_IO_NBMISC         5
3361
3362 #define INDIRECT_IO_PLL_READ       INDIRECT_IO_PLL   | INDIRECT_READ
3363 #define INDIRECT_IO_PLL_WRITE      INDIRECT_IO_PLL   | INDIRECT_WRITE
3364 #define INDIRECT_IO_MC_READ        INDIRECT_IO_MC    | INDIRECT_READ
3365 #define INDIRECT_IO_MC_WRITE       INDIRECT_IO_MC    | INDIRECT_WRITE
3366 #define INDIRECT_IO_PCIE_READ      INDIRECT_IO_PCIE  | INDIRECT_READ
3367 #define INDIRECT_IO_PCIE_WRITE     INDIRECT_IO_PCIE  | INDIRECT_WRITE
3368 #define INDIRECT_IO_PCIEP_READ     INDIRECT_IO_PCIEP | INDIRECT_READ
3369 #define INDIRECT_IO_PCIEP_WRITE    INDIRECT_IO_PCIEP | INDIRECT_WRITE
3370 #define INDIRECT_IO_NBMISC_READ    INDIRECT_IO_NBMISC | INDIRECT_READ
3371 #define INDIRECT_IO_NBMISC_WRITE   INDIRECT_IO_NBMISC | INDIRECT_WRITE
3372
3373 typedef struct _ATOM_OEM_INFO
3374 {
3375   ATOM_COMMON_TABLE_HEADER      sHeader;
3376   ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
3377 }ATOM_OEM_INFO;
3378
3379 typedef struct _ATOM_TV_MODE
3380 {
3381    UCHAR        ucVMode_Num;                      //Video mode number
3382    UCHAR        ucTV_Mode_Num;                  //Internal TV mode number
3383 }ATOM_TV_MODE;
3384
3385 typedef struct _ATOM_BIOS_INT_TVSTD_MODE
3386 {
3387   ATOM_COMMON_TABLE_HEADER sHeader;
3388    USHORT       usTV_Mode_LUT_Offset;   // Pointer to standard to internal number conversion table
3389    USHORT       usTV_FIFO_Offset;                 // Pointer to FIFO entry table
3390    USHORT       usNTSC_Tbl_Offset;              // Pointer to SDTV_Mode_NTSC table
3391    USHORT       usPAL_Tbl_Offset;                 // Pointer to SDTV_Mode_PAL table
3392    USHORT       usCV_Tbl_Offset;                  // Pointer to SDTV_Mode_PAL table
3393 }ATOM_BIOS_INT_TVSTD_MODE;
3394
3395
3396 typedef struct _ATOM_TV_MODE_SCALER_PTR
3397 {
3398    USHORT       ucFilter0_Offset;               //Pointer to filter format 0 coefficients
3399    USHORT       usFilter1_Offset;               //Pointer to filter format 0 coefficients
3400    UCHAR        ucTV_Mode_Num;
3401 }ATOM_TV_MODE_SCALER_PTR;
3402
3403 typedef struct _ATOM_STANDARD_VESA_TIMING
3404 {
3405   ATOM_COMMON_TABLE_HEADER sHeader;
3406   ATOM_MODE_TIMING                               aModeTimings[16];      // 16 is not the real array number, just for initial allocation
3407 }ATOM_STANDARD_VESA_TIMING;
3408
3409
3410 typedef struct _ATOM_STD_FORMAT
3411 {
3412   USHORT    usSTD_HDisp;
3413   USHORT    usSTD_VDisp;
3414   USHORT    usSTD_RefreshRate;
3415   USHORT    usReserved;
3416 }ATOM_STD_FORMAT;
3417
3418 typedef struct _ATOM_VESA_TO_EXTENDED_MODE
3419 {
3420   USHORT  usVESA_ModeNumber;
3421   USHORT  usExtendedModeNumber;
3422 }ATOM_VESA_TO_EXTENDED_MODE;
3423
3424 typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT
3425 {
3426   ATOM_COMMON_TABLE_HEADER   sHeader;
3427   ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76];
3428 }ATOM_VESA_TO_INTENAL_MODE_LUT;
3429
3430 /*************** ATOM Memory Related Data Structure ***********************/
3431 typedef struct _ATOM_MEMORY_VENDOR_BLOCK{
3432         UCHAR                                                                                           ucMemoryType;
3433         UCHAR                                                                                           ucMemoryVendor;
3434         UCHAR                                                                                           ucAdjMCId;
3435         UCHAR                                                                                           ucDynClkId;
3436         ULONG                                                                                           ulDllResetClkRange;
3437 }ATOM_MEMORY_VENDOR_BLOCK;
3438
3439
3440 typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{
3441 #if ATOM_BIG_ENDIAN
3442         ULONG                                                                                           ucMemBlkId:8;
3443         ULONG                                                                                           ulMemClockRange:24;
3444 #else
3445         ULONG                                                                                           ulMemClockRange:24;
3446         ULONG                                                                                           ucMemBlkId:8;
3447 #endif
3448 }ATOM_MEMORY_SETTING_ID_CONFIG;
3449
3450 typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS
3451 {
3452   ATOM_MEMORY_SETTING_ID_CONFIG slAccess;
3453   ULONG                         ulAccess;
3454 }ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS;
3455
3456
3457 typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{
3458         ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS                    ulMemoryID;
3459         ULONG                                                                                                                           aulMemData[1];
3460 }ATOM_MEMORY_SETTING_DATA_BLOCK;
3461
3462
3463 typedef struct _ATOM_INIT_REG_INDEX_FORMAT{
3464          USHORT                                                                                 usRegIndex;                                     // MC register index
3465          UCHAR                                                                                  ucPreRegDataLength;                             // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf
3466 }ATOM_INIT_REG_INDEX_FORMAT;
3467
3468
3469 typedef struct _ATOM_INIT_REG_BLOCK{
3470         USHORT                                                                                                  usRegIndexTblSize;                                                                                                      //size of asRegIndexBuf
3471         USHORT                                                                                                  usRegDataBlkSize;                                                                                                               //size of ATOM_MEMORY_SETTING_DATA_BLOCK
3472         ATOM_INIT_REG_INDEX_FORMAT                      asRegIndexBuf[1];
3473         ATOM_MEMORY_SETTING_DATA_BLOCK  asRegDataBuf[1];
3474 }ATOM_INIT_REG_BLOCK;
3475
3476 #define END_OF_REG_INDEX_BLOCK  0x0ffff
3477 #define END_OF_REG_DATA_BLOCK   0x00000000
3478 #define ATOM_INIT_REG_MASK_FLAG 0x80
3479 #define CLOCK_RANGE_HIGHEST                     0x00ffffff
3480
3481 #define VALUE_DWORD             SIZEOF ULONG
3482 #define VALUE_SAME_AS_ABOVE     0
3483 #define VALUE_MASK_DWORD        0x84
3484
3485 typedef struct _ATOM_MC_INIT_PARAM_TABLE
3486 {
3487   ATOM_COMMON_TABLE_HEADER              sHeader;
3488   USHORT                                                                                        usAdjustARB_SEQDataOffset;
3489   USHORT                                                                                        usMCInitMemTypeTblOffset;
3490   USHORT                                                                                        usMCInitCommonTblOffset;
3491   USHORT                                                                                        usMCInitPowerDownTblOffset;
3492         ULONG                                                                                           ulARB_SEQDataBuf[32];
3493         ATOM_INIT_REG_BLOCK                                     asMCInitMemType;
3494         ATOM_INIT_REG_BLOCK                                     asMCInitCommon;
3495 }ATOM_MC_INIT_PARAM_TABLE;
3496
3497
3498 #define _4Mx16              0x2
3499 #define _4Mx32              0x3
3500 #define _8Mx16              0x12
3501 #define _8Mx32              0x13
3502 #define _16Mx16             0x22
3503 #define _16Mx32             0x23
3504 #define _32Mx16             0x32
3505 #define _32Mx32             0x33
3506 #define _64Mx8              0x41
3507 #define _64Mx16             0x42
3508
3509 #define SAMSUNG             0x1
3510 #define INFINEON            0x2
3511 #define ELPIDA              0x3
3512 #define ETRON               0x4
3513 #define NANYA               0x5
3514 #define HYNIX               0x6
3515 #define MOSEL               0x7
3516 #define WINBOND             0x8
3517 #define ESMT                0x9
3518 #define MICRON              0xF
3519
3520 #define QIMONDA             INFINEON
3521 #define PROMOS              MOSEL
3522
3523 #define ATOM_MAX_NUMBER_OF_VRAM_MODULE  16
3524
3525 #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK  0xF
3526 typedef struct _ATOM_VRAM_MODULE_V1
3527 {
3528   ULONG                      ulReserved;
3529   USHORT                     usEMRSValue;
3530   USHORT                     usMRSValue;
3531   USHORT                     usReserved;
3532   UCHAR                      ucExtMemoryID;     // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
3533   UCHAR                      ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;
3534   UCHAR                      ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender
3535   UCHAR                      ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
3536   UCHAR                      ucRow;             // Number of Row,in power of 2;
3537   UCHAR                      ucColumn;          // Number of Column,in power of 2;
3538   UCHAR                      ucBank;            // Nunber of Bank;
3539   UCHAR                      ucRank;            // Number of Rank, in power of 2
3540   UCHAR                      ucChannelNum;      // Number of channel;
3541   UCHAR                      ucChannelConfig;   // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
3542   UCHAR                      ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
3543   UCHAR                      ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
3544   UCHAR                      ucReserved[2];
3545 }ATOM_VRAM_MODULE_V1;
3546
3547
3548 typedef struct _ATOM_VRAM_MODULE_V2
3549 {
3550   ULONG                      ulReserved;
3551   ULONG                      ulFlags;                           // To enable/disable functionalities based on memory type
3552   ULONG                      ulEngineClock;     // Override of default engine clock for particular memory type
3553   ULONG                      ulMemoryClock;     // Override of default memory clock for particular memory type
3554   USHORT                     usEMRS2Value;      // EMRS2 Value is used for GDDR2 and GDDR4 memory type
3555   USHORT                     usEMRS3Value;      // EMRS3 Value is used for GDDR2 and GDDR4 memory type
3556   USHORT                     usEMRSValue;
3557   USHORT                     usMRSValue;
3558   USHORT                     usReserved;
3559   UCHAR                      ucExtMemoryID;     // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
3560   UCHAR                      ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
3561   UCHAR                      ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
3562   UCHAR                      ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
3563   UCHAR                      ucRow;             // Number of Row,in power of 2;
3564   UCHAR                      ucColumn;          // Number of Column,in power of 2;
3565   UCHAR                      ucBank;            // Nunber of Bank;
3566   UCHAR                      ucRank;            // Number of Rank, in power of 2
3567   UCHAR                      ucChannelNum;      // Number of channel;
3568   UCHAR                      ucChannelConfig;   // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
3569   UCHAR                      ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
3570   UCHAR                      ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
3571   UCHAR                      ucRefreshRateFactor;
3572   UCHAR                      ucReserved[3];
3573 }ATOM_VRAM_MODULE_V2;
3574
3575
3576 typedef struct _ATOM_MEMORY_TIMING_FORMAT
3577 {
3578         ULONG                                                                                    ulClkRange;                            // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
3579         USHORT                                                                           usMRS;                                                 // mode register
3580         USHORT                                                                           usEMRS;                                                // extended mode register
3581         UCHAR                                                                                    ucCL;                                                  // CAS latency
3582         UCHAR                                                                                    ucWL;                                                  // WRITE Latency
3583         UCHAR                                                                                    uctRAS;                                                // tRAS
3584         UCHAR                                                                                    uctRC;                                                 // tRC
3585         UCHAR                                                                                    uctRFC;                                                // tRFC
3586         UCHAR                                                                                    uctRCDR;                                               // tRCDR
3587         UCHAR                                                                                    uctRCDW;                                               // tRCDW
3588         UCHAR                                                                                    uctRP;                                                 // tRP
3589         UCHAR                                                                                    uctRRD;                                                // tRRD
3590         UCHAR                                                                                    uctWR;                                                 // tWR
3591         UCHAR                                                                                    uctWTR;                                                // tWTR
3592         UCHAR                                                                                    uctPDIX;                                               // tPDIX
3593         UCHAR                                                                                    uctFAW;                                                // tFAW
3594         UCHAR                                                                                    uctAOND;                                               // tAOND
3595         UCHAR                                                                                    ucflag;                                                // flag to control memory timing calculation. bit0= control EMRS2 Infineon
3596         UCHAR                                                                                    ucReserved;                            //
3597 }ATOM_MEMORY_TIMING_FORMAT;
3598
3599 #define MEM_TIMING_FLAG_APP_MODE                                                                0x01                                                                    // =0 mid clock range  =1 high clock range
3600
3601 typedef struct _ATOM_MEMORY_FORMAT
3602 {
3603         ULONG                                                                                    ulDllDisClock;                 // memory DLL will be disable when target memory clock is below this clock
3604   USHORT                     usEMRS2Value;      // EMRS2 Value is used for GDDR2 and GDDR4 memory type
3605   USHORT                     usEMRS3Value;      // EMRS3 Value is used for GDDR2 and GDDR4 memory type
3606   UCHAR                      ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
3607   UCHAR                      ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
3608   UCHAR                      ucRow;             // Number of Row,in power of 2;
3609   UCHAR                      ucColumn;          // Number of Column,in power of 2;
3610   UCHAR                      ucBank;            // Nunber of Bank;
3611   UCHAR                      ucRank;            // Number of Rank, in power of 2
3612         UCHAR                                                                                    ucBurstSize;                           // burst size, 0= burst size=4  1= burst size=8
3613   UCHAR                      ucDllDisBit;                               // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
3614   UCHAR                      ucRefreshRateFactor;       // memory refresh rate in unit of ms
3615         UCHAR                                                                                    ucDensity;                                     // _8Mx32, _16Mx32, _16Mx16, _32Mx16
3616         UCHAR                                                                                    ucPreamble;                            //[7:4] Write Preamble, [3:0] Read Preamble
3617   UCHAR                                                                                  ucMemAttrib;                           // Memory Device Addribute, like RDBI/WDBI etc
3618         ATOM_MEMORY_TIMING_FORMAT        asMemTiming[5];                //Memory Timing block sort from lower clock to higher clock
3619 }ATOM_MEMORY_FORMAT;
3620
3621
3622 typedef struct _ATOM_VRAM_MODULE_V3
3623 {
3624         ULONG                                                                                    ulChannelMapCfg;               // board dependent paramenter:Channel combination
3625         USHORT                                                                           usSize;                                                // size of ATOM_VRAM_MODULE_V3
3626   USHORT                     usDefaultMVDDQ;            // board dependent parameter:Default Memory Core Voltage
3627   USHORT                     usDefaultMVDDC;            // board dependent parameter:Default Memory IO Voltage
3628         UCHAR                      ucExtMemoryID;     // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
3629   UCHAR                      ucChannelNum;      // board dependent parameter:Number of channel;
3630         UCHAR                                                                                    ucChannelSize;                 // board dependent parameter:32bit or 64bit
3631         UCHAR                                                                                    ucVREFI;                                               // board dependnt parameter: EXT or INT +160mv to -140mv
3632         UCHAR                                                                                    ucNPL_RT;                                      // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
3633         UCHAR                                                                                    ucFlag;                                                // To enable/disable functionalities based on memory type
3634         ATOM_MEMORY_FORMAT                               asMemory;                                      // describ all of video memory parameters from memory spec
3635 }ATOM_VRAM_MODULE_V3;
3636
3637
3638 //ATOM_VRAM_MODULE_V3.ucNPL_RT
3639 #define NPL_RT_MASK                                                                                                                     0x0f
3640 #define BATTERY_ODT_MASK                                                                                                0xc0
3641
3642 #define ATOM_VRAM_MODULE                 ATOM_VRAM_MODULE_V3
3643
3644 typedef struct _ATOM_VRAM_INFO_V2
3645 {
3646   ATOM_COMMON_TABLE_HEADER   sHeader;
3647   UCHAR                      ucNumOfVRAMModule;
3648   ATOM_VRAM_MODULE           aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
3649 }ATOM_VRAM_INFO_V2;
3650
3651 typedef struct _ATOM_VRAM_INFO_V3
3652 {
3653   ATOM_COMMON_TABLE_HEADER   sHeader;
3654         USHORT                                                                           usMemAdjustTblOffset;                                                                                                   // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
3655         USHORT                                                                           usMemClkPatchTblOffset;                                                                                                 //     offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
3656         USHORT                                                                           usRerseved;
3657         UCHAR                            aVID_PinsShift[9];                                                                                                                      // 8 bit strap maximum+terminator
3658   UCHAR                      ucNumOfVRAMModule;
3659   ATOM_VRAM_MODULE                     aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
3660         ATOM_INIT_REG_BLOCK                              asMemPatch;                                                                                                                                             // for allocation
3661                                                                                                                                                                                                                                                                                                                  //     ATOM_INIT_REG_BLOCK                              aMemAdjust;
3662 }ATOM_VRAM_INFO_V3;
3663
3664 #define ATOM_VRAM_INFO_LAST          ATOM_VRAM_INFO_V3
3665
3666 typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO
3667 {
3668   ATOM_COMMON_TABLE_HEADER   sHeader;
3669   UCHAR                          aVID_PinsShift[9];   //8 bit strap maximum+terminator
3670 }ATOM_VRAM_GPIO_DETECTION_INFO;
3671
3672
3673 typedef struct _ATOM_MEMORY_TRAINING_INFO
3674 {
3675         ATOM_COMMON_TABLE_HEADER   sHeader;
3676         UCHAR                                                                                    ucTrainingLoop;
3677         UCHAR                                                                                    ucReserved[3];
3678         ATOM_INIT_REG_BLOCK                              asMemTrainingSetting;
3679 }ATOM_MEMORY_TRAINING_INFO;
3680
3681
3682 typedef struct SW_I2C_CNTL_DATA_PARAMETERS
3683 {
3684   UCHAR    ucControl;
3685   UCHAR    ucData;
3686   UCHAR    ucSatus;
3687   UCHAR    ucTemp;
3688 } SW_I2C_CNTL_DATA_PARAMETERS;
3689
3690 #define SW_I2C_CNTL_DATA_PS_ALLOCATION  SW_I2C_CNTL_DATA_PARAMETERS
3691
3692 typedef struct _SW_I2C_IO_DATA_PARAMETERS
3693 {
3694   USHORT   GPIO_Info;
3695   UCHAR    ucAct;
3696   UCHAR    ucData;
3697  } SW_I2C_IO_DATA_PARAMETERS;
3698
3699 #define SW_I2C_IO_DATA_PS_ALLOCATION  SW_I2C_IO_DATA_PARAMETERS
3700
3701 /****************************SW I2C CNTL DEFINITIONS**********************/
3702 #define SW_I2C_IO_RESET       0
3703 #define SW_I2C_IO_GET         1
3704 #define SW_I2C_IO_DRIVE       2
3705 #define SW_I2C_IO_SET         3
3706 #define SW_I2C_IO_START       4
3707
3708 #define SW_I2C_IO_CLOCK       0
3709 #define SW_I2C_IO_DATA        0x80
3710
3711 #define SW_I2C_IO_ZERO        0
3712 #define SW_I2C_IO_ONE         0x100
3713
3714 #define SW_I2C_CNTL_READ      0
3715 #define SW_I2C_CNTL_WRITE     1
3716 #define SW_I2C_CNTL_START     2
3717 #define SW_I2C_CNTL_STOP      3
3718 #define SW_I2C_CNTL_OPEN      4
3719 #define SW_I2C_CNTL_CLOSE     5
3720 #define SW_I2C_CNTL_WRITE1BIT 6
3721
3722 //==============================VESA definition Portion===============================
3723 #define VESA_OEM_PRODUCT_REV                                '01.00'
3724 #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT             0xBB       //refer to VBE spec p.32, no TTY support
3725 #define VESA_MODE_WIN_ATTRIBUTE                                              7
3726 #define VESA_WIN_SIZE                                                                                        64
3727
3728 typedef struct _PTR_32_BIT_STRUCTURE
3729 {
3730         USHORT  Offset16;
3731         USHORT  Segment16;
3732 } PTR_32_BIT_STRUCTURE;
3733
3734 typedef union _PTR_32_BIT_UNION
3735 {
3736         PTR_32_BIT_STRUCTURE    SegmentOffset;
3737         ULONG                                           Ptr32_Bit;
3738 } PTR_32_BIT_UNION;
3739
3740 typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE
3741 {
3742         UCHAR                                 VbeSignature[4];
3743         USHORT                              VbeVersion;
3744         PTR_32_BIT_UNION        OemStringPtr;
3745         UCHAR                                 Capabilities[4];
3746         PTR_32_BIT_UNION        VideoModePtr;
3747         USHORT                              TotalMemory;
3748 } VBE_1_2_INFO_BLOCK_UPDATABLE;
3749
3750
3751 typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE
3752 {
3753         VBE_1_2_INFO_BLOCK_UPDATABLE    CommonBlock;
3754         USHORT                                                      OemSoftRev;
3755         PTR_32_BIT_UNION                                OemVendorNamePtr;
3756         PTR_32_BIT_UNION                                OemProductNamePtr;
3757         PTR_32_BIT_UNION                                OemProductRevPtr;
3758 } VBE_2_0_INFO_BLOCK_UPDATABLE;
3759
3760 typedef union _VBE_VERSION_UNION
3761 {
3762         VBE_2_0_INFO_BLOCK_UPDATABLE    VBE_2_0_InfoBlock;
3763         VBE_1_2_INFO_BLOCK_UPDATABLE    VBE_1_2_InfoBlock;
3764 } VBE_VERSION_UNION;
3765
3766 typedef struct _VBE_INFO_BLOCK
3767 {
3768         VBE_VERSION_UNION                       UpdatableVBE_Info;
3769         UCHAR                                                 Reserved[222];
3770         UCHAR                                                 OemData[256];
3771 } VBE_INFO_BLOCK;
3772
3773 typedef struct _VBE_FP_INFO
3774 {
3775   USHORT        HSize;
3776         USHORT  VSize;
3777         USHORT  FPType;
3778         UCHAR           RedBPP;
3779         UCHAR           GreenBPP;
3780         UCHAR           BlueBPP;
3781         UCHAR           ReservedBPP;
3782         ULONG           RsvdOffScrnMemSize;
3783         ULONG           RsvdOffScrnMEmPtr;
3784         UCHAR           Reserved[14];
3785 } VBE_FP_INFO;
3786
3787 typedef struct _VESA_MODE_INFO_BLOCK
3788 {
3789 // Mandatory information for all VBE revisions
3790   USHORT    ModeAttributes;  //                 dw      ?       ; mode attributes
3791         UCHAR     WinAAttributes;  //                   db      ?       ; window A attributes
3792         UCHAR     WinBAttributes;  //                   db      ?       ; window B attributes
3793         USHORT    WinGranularity;  //                   dw      ?       ; window granularity
3794         USHORT    WinSize;         //                   dw      ?       ; window size
3795         USHORT    WinASegment;     //                   dw      ?       ; window A start segment
3796         USHORT    WinBSegment;     //                   dw      ?       ; window B start segment
3797         ULONG     WinFuncPtr;      //                   dd      ?       ; real mode pointer to window function
3798         USHORT    BytesPerScanLine;//                   dw      ?       ; bytes per scan line
3799
3800 //; Mandatory information for VBE 1.2 and above
3801   USHORT    XResolution;      //                        dw      ?       ; horizontal resolution in pixels or characters
3802         USHORT    YResolution;      //                  dw      ?       ; vertical resolution in pixels or characters
3803         UCHAR     XCharSize;        //                  db      ?       ; character cell width in pixels
3804         UCHAR     YCharSize;        //                  db      ?       ; character cell height in pixels
3805         UCHAR     NumberOfPlanes;   //                  db      ?       ; number of memory planes
3806         UCHAR     BitsPerPixel;     //                  db      ?       ; bits per pixel
3807         UCHAR     NumberOfBanks;    //                  db      ?       ; number of banks
3808         UCHAR     MemoryModel;      //                  db      ?       ; memory model type
3809         UCHAR     BankSize;         //                  db      ?       ; bank size in KB
3810         UCHAR     NumberOfImagePages;//           db    ?       ; number of images
3811         UCHAR     ReservedForPageFunction;//db  1       ; reserved for page function
3812
3813 //; Direct Color fields(required for direct/6 and YUV/7 memory models)
3814         UCHAR                   RedMaskSize;        //          db      ?       ; size of direct color red mask in bits
3815         UCHAR                   RedFieldPosition;   //          db      ?       ; bit position of lsb of red mask
3816         UCHAR                   GreenMaskSize;      //          db      ?       ; size of direct color green mask in bits
3817         UCHAR                   GreenFieldPosition; //          db      ?       ; bit position of lsb of green mask
3818         UCHAR                   BlueMaskSize;       //          db      ?       ; size of direct color blue mask in bits
3819         UCHAR                   BlueFieldPosition;  //          db      ?       ; bit position of lsb of blue mask
3820         UCHAR                   RsvdMaskSize;       //          db      ?       ; size of direct color reserved mask in bits
3821         UCHAR                   RsvdFieldPosition;  //          db      ?       ; bit position of lsb of reserved mask
3822         UCHAR                   DirectColorModeInfo;//          db      ?       ; direct color mode attributes
3823
3824 //; Mandatory information for VBE 2.0 and above
3825         ULONG                   PhysBasePtr;        //          dd      ?       ; physical address for flat memory frame buffer
3826         ULONG                   Reserved_1;         //          dd      0       ; reserved - always set to 0
3827         USHORT          Reserved_2;         //    dw    0       ; reserved - always set to 0
3828
3829 //; Mandatory information for VBE 3.0 and above
3830         USHORT          LinBytesPerScanLine;  //        dw      ?       ; bytes per scan line for linear modes
3831         UCHAR                   BnkNumberOfImagePages;//        db      ?       ; number of images for banked modes
3832         UCHAR                   LinNumberOfImagPages; //        db      ?       ; number of images for linear modes
3833         UCHAR                   LinRedMaskSize;       //        db      ?       ; size of direct color red mask(linear modes)
3834         UCHAR                   LinRedFieldPosition;  //        db      ?       ; bit position of lsb of red mask(linear modes)
3835         UCHAR                   LinGreenMaskSize;     //        db      ?       ; size of direct color green mask(linear modes)
3836         UCHAR                   LinGreenFieldPosition;//        db      ?       ; bit position of lsb of green mask(linear modes)
3837         UCHAR                   LinBlueMaskSize;      //        db      ?       ; size of direct color blue mask(linear modes)
3838         UCHAR                   LinBlueFieldPosition; //        db      ?       ; bit position of lsb of blue mask(linear modes)
3839         UCHAR                   LinRsvdMaskSize;      //        db      ?       ; size of direct color reserved mask(linear modes)
3840         UCHAR                   LinRsvdFieldPosition; //        db      ?       ; bit position of lsb of reserved mask(linear modes)
3841         ULONG                   MaxPixelClock;        //        dd      ?       ; maximum pixel clock(in Hz) for graphics mode
3842         UCHAR                   Reserved;             //        db      190 dup (0)
3843 } VESA_MODE_INFO_BLOCK;
3844
3845 // BIOS function CALLS
3846 #define ATOM_BIOS_EXTENDED_FUNCTION_CODE        0xA0            // ATI Extended Function code
3847 #define ATOM_BIOS_FUNCTION_COP_MODE             0x00
3848 #define ATOM_BIOS_FUNCTION_SHORT_QUERY1         0x04
3849 #define ATOM_BIOS_FUNCTION_SHORT_QUERY2         0x05
3850 #define ATOM_BIOS_FUNCTION_SHORT_QUERY3         0x06
3851 #define ATOM_BIOS_FUNCTION_GET_DDC              0x0B
3852 #define ATOM_BIOS_FUNCTION_ASIC_DSTATE          0x0E
3853 #define ATOM_BIOS_FUNCTION_DEBUG_PLAY           0x0F
3854 #define ATOM_BIOS_FUNCTION_STV_STD              0x16
3855 #define ATOM_BIOS_FUNCTION_DEVICE_DET           0x17
3856 #define ATOM_BIOS_FUNCTION_DEVICE_SWITCH        0x18
3857
3858 #define ATOM_BIOS_FUNCTION_PANEL_CONTROL        0x82
3859 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET       0x83
3860 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH    0x84
3861 #define ATOM_BIOS_FUNCTION_HW_ICON              0x8A
3862 #define ATOM_BIOS_FUNCTION_SET_CMOS             0x8B
3863 #define SUB_FUNCTION_UPDATE_DISPLAY_INFO        0x8000          // Sub function 80
3864 #define SUB_FUNCTION_UPDATE_EXPANSION_INFO      0x8100          // Sub function 80
3865
3866 #define ATOM_BIOS_FUNCTION_DISPLAY_INFO         0x8D
3867 #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF        0x8E
3868 #define ATOM_BIOS_FUNCTION_VIDEO_STATE          0x8F
3869 #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE    0x0300          // Sub function 03
3870 #define ATOM_SUB_FUNCTION_GET_LIDSTATE          0x0700          // Sub function 7
3871 #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE  0x1400          // Notify caller the current thermal state
3872 #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300          // Notify caller the current critical state
3873 #define ATOM_SUB_FUNCTION_SET_LIDSTATE          0x8500          // Sub function 85
3874 #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89
3875 #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT    0x9400          // Notify caller that ADC is supported
3876
3877
3878 #define ATOM_BIOS_FUNCTION_VESA_DPMS            0x4F10          // Set DPMS
3879 #define ATOM_SUB_FUNCTION_SET_DPMS              0x0001          // BL: Sub function 01
3880 #define ATOM_SUB_FUNCTION_GET_DPMS              0x0002          // BL: Sub function 02
3881 #define ATOM_PARAMETER_VESA_DPMS_ON             0x0000          // BH Parameter for DPMS ON.
3882 #define ATOM_PARAMETER_VESA_DPMS_STANDBY        0x0100          // BH Parameter for DPMS STANDBY
3883 #define ATOM_PARAMETER_VESA_DPMS_SUSPEND        0x0200          // BH Parameter for DPMS SUSPEND
3884 #define ATOM_PARAMETER_VESA_DPMS_OFF            0x0400          // BH Parameter for DPMS OFF
3885 #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON      0x0800          // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED)
3886
3887 #define ATOM_BIOS_RETURN_CODE_MASK              0x0000FF00L
3888 #define ATOM_BIOS_REG_HIGH_MASK                 0x0000FF00L
3889 #define ATOM_BIOS_REG_LOW_MASK                  0x000000FFL
3890
3891 // structure used for VBIOS only
3892
3893 //DispOutInfoTable
3894 typedef struct _ASIC_TRANSMITTER_INFO
3895 {
3896         USHORT usTransmitterObjId;
3897         USHORT usSupportDevice;
3898   UCHAR  ucTransmitterCmdTblId;
3899         UCHAR  ucConfig;
3900         UCHAR  ucEncoderID;                                      //available 1st encoder ( default )
3901         UCHAR  ucOptionEncoderID;    //available 2nd encoder ( optional )
3902         UCHAR  uc2ndEncoderID;
3903         UCHAR  ucReserved;
3904 }ASIC_TRANSMITTER_INFO;
3905
3906 typedef struct _ASIC_ENCODER_INFO
3907 {
3908         UCHAR ucEncoderID;
3909         UCHAR ucEncoderConfig;
3910   USHORT usEncoderCmdTblId;
3911 }ASIC_ENCODER_INFO;
3912
3913 typedef struct _ATOM_DISP_OUT_INFO
3914 {
3915   ATOM_COMMON_TABLE_HEADER sHeader;
3916         USHORT ptrTransmitterInfo;
3917         USHORT ptrEncoderInfo;
3918         ASIC_TRANSMITTER_INFO  asTransmitterInfo[1];
3919         ASIC_ENCODER_INFO      asEncoderInfo[1];
3920 }ATOM_DISP_OUT_INFO;
3921
3922 // DispDevicePriorityInfo
3923 typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO
3924 {
3925   ATOM_COMMON_TABLE_HEADER sHeader;
3926         USHORT asDevicePriority[16];
3927 }ATOM_DISPLAY_DEVICE_PRIORITY_INFO;
3928
3929 //ProcessAuxChannelTransactionTable
3930 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
3931 {
3932         USHORT  lpAuxRequest;
3933         USHORT  lpDataOut;
3934         UCHAR           ucChannelID;
3935         union
3936         {
3937   UCHAR   ucReplyStatus;
3938         UCHAR   ucDelay;
3939         };
3940   UCHAR   ucDataOutLen;
3941         UCHAR   ucReserved;
3942 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS;
3943
3944 #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION                   PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
3945
3946 //GetSinkType
3947
3948 typedef struct _DP_ENCODER_SERVICE_PARAMETERS
3949 {
3950         USHORT ucLinkClock;
3951         union
3952         {
3953         UCHAR ucConfig;                         // for DP training command
3954         UCHAR ucI2cId;                          // use for GET_SINK_TYPE command
3955         };
3956         UCHAR ucAction;
3957         UCHAR ucStatus;
3958         UCHAR ucLaneNum;
3959         UCHAR ucReserved[2];
3960 }DP_ENCODER_SERVICE_PARAMETERS;
3961
3962 // ucAction
3963 #define ATOM_DP_ACTION_GET_SINK_TYPE                                                    0x01
3964 #define ATOM_DP_ACTION_TRAINING_START                                                   0x02
3965 #define ATOM_DP_ACTION_TRAINING_COMPLETE                                        0x03
3966 #define ATOM_DP_ACTION_TRAINING_PATTERN_SEL                             0x04
3967 #define ATOM_DP_ACTION_SET_VSWING_PREEMP                                        0x05
3968 #define ATOM_DP_ACTION_GET_VSWING_PREEMP                                        0x06
3969
3970 // ucConfig
3971 #define ATOM_DP_CONFIG_ENCODER_SEL_MASK                                         0x03
3972 #define ATOM_DP_CONFIG_DIG1_ENCODER                                                             0x00
3973 #define ATOM_DP_CONFIG_DIG2_ENCODER                                                             0x01
3974 #define ATOM_DP_CONFIG_EXTERNAL_ENCODER                                         0x02
3975 #define ATOM_DP_CONFIG_LINK_SEL_MASK                                                    0x04
3976 #define ATOM_DP_CONFIG_LINK_A                                                                                   0x00
3977 #define ATOM_DP_CONFIG_LINK_B                                                                                   0x04
3978
3979 #define DP_ENCODER_SERVICE_PS_ALLOCATION                                WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
3980
3981 // DP_TRAINING_TABLE
3982 #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR                             ATOM_DP_TRAINING_TBL_ADDR
3983 #define DPCD_SET_SS_CNTL_TBL_ADDR                                                                                                       (ATOM_DP_TRAINING_TBL_ADDR + 8 )
3984 #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR                                                    (ATOM_DP_TRAINING_TBL_ADDR + 16 )
3985 #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR                                                             (ATOM_DP_TRAINING_TBL_ADDR + 24 )
3986 #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR                                                             (ATOM_DP_TRAINING_TBL_ADDR + 32)
3987 #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR                                                   (ATOM_DP_TRAINING_TBL_ADDR + 40)
3988 #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR                                                    (ATOM_DP_TRAINING_TBL_ADDR + 48)
3989 #define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR                                                             (ATOM_DP_TRAINING_TBL_ADDR + 60)
3990 #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR                                                                                   (ATOM_DP_TRAINING_TBL_ADDR + 64)
3991 #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR                                                              (ATOM_DP_TRAINING_TBL_ADDR + 72)
3992 #define DP_I2C_AUX_DDC_READ_TBL_ADDR                                                                                    (ATOM_DP_TRAINING_TBL_ADDR + 76)
3993 #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR                                                                        (ATOM_DP_TRAINING_TBL_ADDR + 80)
3994
3995
3996 typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
3997 {
3998         UCHAR   ucI2CSpeed;
3999         union
4000         {
4001    UCHAR ucRegIndex;
4002    UCHAR ucStatus;
4003         };
4004         USHORT  lpI2CDataOut;
4005   UCHAR   ucFlag;
4006   UCHAR   ucTransBytes;
4007   UCHAR   ucSlaveAddr;
4008   UCHAR   ucLineNumber;
4009 }PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS;
4010
4011 #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION       PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
4012
4013 //ucFlag
4014 #define HW_I2C_WRITE        1
4015 #define HW_I2C_READ         0
4016
4017
4018 /****************************************************************************/
4019 //Portion VI: Definitinos being oboselete
4020 /****************************************************************************/
4021
4022 //==========================================================================================
4023 //Remove the definitions below when driver is ready!
4024 typedef struct _ATOM_DAC_INFO
4025 {
4026   ATOM_COMMON_TABLE_HEADER sHeader;
4027   USHORT                   usMaxFrequency;      // in 10kHz unit
4028   USHORT                   usReserved;
4029 }ATOM_DAC_INFO;
4030
4031
4032 typedef struct  _COMPASSIONATE_DATA
4033 {
4034   ATOM_COMMON_TABLE_HEADER sHeader;
4035
4036   //==============================  DAC1 portion
4037   UCHAR   ucDAC1_BG_Adjustment;
4038   UCHAR   ucDAC1_DAC_Adjustment;
4039   USHORT  usDAC1_FORCE_Data;
4040   //==============================  DAC2 portion
4041   UCHAR   ucDAC2_CRT2_BG_Adjustment;
4042   UCHAR   ucDAC2_CRT2_DAC_Adjustment;
4043   USHORT  usDAC2_CRT2_FORCE_Data;
4044   USHORT  usDAC2_CRT2_MUX_RegisterIndex;
4045   UCHAR   ucDAC2_CRT2_MUX_RegisterInfo;     //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
4046   UCHAR   ucDAC2_NTSC_BG_Adjustment;
4047   UCHAR   ucDAC2_NTSC_DAC_Adjustment;
4048   USHORT  usDAC2_TV1_FORCE_Data;
4049   USHORT  usDAC2_TV1_MUX_RegisterIndex;
4050   UCHAR   ucDAC2_TV1_MUX_RegisterInfo;      //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
4051   UCHAR   ucDAC2_CV_BG_Adjustment;
4052   UCHAR   ucDAC2_CV_DAC_Adjustment;
4053   USHORT  usDAC2_CV_FORCE_Data;
4054   USHORT  usDAC2_CV_MUX_RegisterIndex;
4055   UCHAR   ucDAC2_CV_MUX_RegisterInfo;       //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
4056   UCHAR   ucDAC2_PAL_BG_Adjustment;
4057   UCHAR   ucDAC2_PAL_DAC_Adjustment;
4058   USHORT  usDAC2_TV2_FORCE_Data;
4059 }COMPASSIONATE_DATA;
4060
4061 /****************************Supported Device Info Table Definitions**********************/
4062 //  ucConnectInfo:
4063 //    [7:4] - connector type
4064 //      = 1   - VGA connector
4065 //      = 2   - DVI-I
4066 //      = 3   - DVI-D
4067 //      = 4   - DVI-A
4068 //      = 5   - SVIDEO
4069 //      = 6   - COMPOSITE
4070 //      = 7   - LVDS
4071 //      = 8   - DIGITAL LINK
4072 //      = 9   - SCART
4073 //      = 0xA - HDMI_type A
4074 //      = 0xB - HDMI_type B
4075 //      = 0xE - Special case1 (DVI+DIN)
4076 //      Others=TBD
4077 //    [3:0] - DAC Associated
4078 //      = 0   - no DAC
4079 //      = 1   - DACA
4080 //      = 2   - DACB
4081 //      = 3   - External DAC
4082 //      Others=TBD
4083 //
4084
4085 typedef struct _ATOM_CONNECTOR_INFO
4086 {
4087 #if ATOM_BIG_ENDIAN
4088   UCHAR   bfConnectorType:4;
4089   UCHAR   bfAssociatedDAC:4;
4090 #else
4091   UCHAR   bfAssociatedDAC:4;
4092   UCHAR   bfConnectorType:4;
4093 #endif
4094 }ATOM_CONNECTOR_INFO;
4095
4096 typedef union _ATOM_CONNECTOR_INFO_ACCESS
4097 {
4098   ATOM_CONNECTOR_INFO sbfAccess;
4099   UCHAR               ucAccess;
4100 }ATOM_CONNECTOR_INFO_ACCESS;
4101
4102 typedef struct _ATOM_CONNECTOR_INFO_I2C
4103 {
4104   ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo;
4105   ATOM_I2C_ID_CONFIG_ACCESS  sucI2cId;
4106 }ATOM_CONNECTOR_INFO_I2C;
4107
4108
4109 typedef struct _ATOM_SUPPORTED_DEVICES_INFO
4110 {
4111   ATOM_COMMON_TABLE_HEADER      sHeader;
4112   USHORT                    usDeviceSupport;
4113   ATOM_CONNECTOR_INFO_I2C   asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO];
4114 }ATOM_SUPPORTED_DEVICES_INFO;
4115
4116 #define NO_INT_SRC_MAPPED       0xFF
4117
4118 typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP
4119 {
4120   UCHAR   ucIntSrcBitmap;
4121 }ATOM_CONNECTOR_INC_SRC_BITMAP;
4122
4123 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2
4124 {
4125   ATOM_COMMON_TABLE_HEADER      sHeader;
4126   USHORT                        usDeviceSupport;
4127   ATOM_CONNECTOR_INFO_I2C       asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
4128   ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
4129 }ATOM_SUPPORTED_DEVICES_INFO_2;
4130
4131 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1
4132 {
4133   ATOM_COMMON_TABLE_HEADER      sHeader;
4134   USHORT                        usDeviceSupport;
4135   ATOM_CONNECTOR_INFO_I2C       asConnInfo[ATOM_MAX_SUPPORTED_DEVICE];
4136   ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE];
4137 }ATOM_SUPPORTED_DEVICES_INFO_2d1;
4138
4139 #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1
4140
4141
4142
4143 typedef struct _ATOM_MISC_CONTROL_INFO
4144 {
4145    USHORT usFrequency;
4146    UCHAR  ucPLL_ChargePump;                                             // PLL charge-pump gain control
4147    UCHAR  ucPLL_DutyCycle;                                              // PLL duty cycle control
4148    UCHAR  ucPLL_VCO_Gain;                                                 // PLL VCO gain control
4149    UCHAR  ucPLL_VoltageSwing;                                   // PLL driver voltage swing control
4150 }ATOM_MISC_CONTROL_INFO;
4151
4152
4153 #define ATOM_MAX_MISC_INFO       4
4154
4155 typedef struct _ATOM_TMDS_INFO
4156 {
4157   ATOM_COMMON_TABLE_HEADER sHeader;
4158   USHORT                                                        usMaxFrequency;             // in 10Khz
4159   ATOM_MISC_CONTROL_INFO                                asMiscInfo[ATOM_MAX_MISC_INFO];
4160 }ATOM_TMDS_INFO;
4161
4162
4163 typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE
4164 {
4165   UCHAR ucTVStandard;     //Same as TV standards defined above,
4166   UCHAR ucPadding[1];
4167 }ATOM_ENCODER_ANALOG_ATTRIBUTE;
4168
4169 typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE
4170 {
4171   UCHAR ucAttribute;      //Same as other digital encoder attributes defined above
4172   UCHAR ucPadding[1];
4173 }ATOM_ENCODER_DIGITAL_ATTRIBUTE;
4174
4175 typedef union _ATOM_ENCODER_ATTRIBUTE
4176 {
4177   ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib;
4178   ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib;
4179 }ATOM_ENCODER_ATTRIBUTE;
4180
4181
4182 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS
4183 {
4184   USHORT usPixelClock;
4185   USHORT usEncoderID;
4186   UCHAR  ucDeviceType;                                                                                          //Use ATOM_DEVICE_xxx1_Index to indicate device type only.
4187   UCHAR  ucAction;                                                                                                              //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
4188   ATOM_ENCODER_ATTRIBUTE usDevAttr;
4189 }DVO_ENCODER_CONTROL_PARAMETERS;
4190
4191 typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION
4192 {
4193   DVO_ENCODER_CONTROL_PARAMETERS    sDVOEncoder;
4194   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION      sReserved;     //Caller doesn't need to init this portion
4195 }DVO_ENCODER_CONTROL_PS_ALLOCATION;
4196
4197
4198 #define ATOM_XTMDS_ASIC_SI164_ID        1
4199 #define ATOM_XTMDS_ASIC_SI178_ID        2
4200 #define ATOM_XTMDS_ASIC_TFP513_ID       3
4201 #define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001
4202 #define ATOM_XTMDS_SUPPORTED_DUALLINK   0x00000002
4203 #define ATOM_XTMDS_MVPU_FPGA            0x00000004
4204
4205
4206 typedef struct _ATOM_XTMDS_INFO
4207 {
4208   ATOM_COMMON_TABLE_HEADER   sHeader;
4209   USHORT                     usSingleLinkMaxFrequency;
4210   ATOM_I2C_ID_CONFIG_ACCESS  sucI2cId;           //Point the ID on which I2C is used to control external chip
4211   UCHAR                      ucXtransimitterID;
4212   UCHAR                      ucSupportedLink;    // Bit field, bit0=1, single link supported;bit1=1,dual link supported
4213   UCHAR                      ucSequnceAlterID;   // Even with the same external TMDS asic, it's possible that the program seqence alters
4214                                                  // due to design. This ID is used to alert driver that the sequence is not "standard"!
4215   UCHAR                      ucMasterAddress;    // Address to control Master xTMDS Chip
4216   UCHAR                      ucSlaveAddress;     // Address to control Slave xTMDS Chip
4217 }ATOM_XTMDS_INFO;
4218
4219 typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS
4220 {
4221   UCHAR ucEnable;                     // ATOM_ENABLE=On or ATOM_DISABLE=Off
4222   UCHAR ucDevice;                     // ATOM_DEVICE_DFP1_INDEX....
4223   UCHAR ucPadding[2];
4224 }DFP_DPMS_STATUS_CHANGE_PARAMETERS;
4225
4226 /****************************Legacy Power Play Table Definitions **********************/
4227
4228 //Definitions for ulPowerPlayMiscInfo
4229 #define ATOM_PM_MISCINFO_SPLIT_CLOCK                     0x00000000L
4230 #define ATOM_PM_MISCINFO_USING_MCLK_SRC                  0x00000001L
4231 #define ATOM_PM_MISCINFO_USING_SCLK_SRC                  0x00000002L
4232
4233 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT            0x00000004L
4234 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH        0x00000008L
4235
4236 #define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN             0x00000010L
4237
4238 #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN          0x00000020L
4239 #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN          0x00000040L
4240 #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE                 0x00000080L  //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program
4241
4242 #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN      0x00000100L
4243 #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN         0x00000200L
4244 #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN              0x00000400L
4245 #define ATOM_PM_MISCINFO_LOAD_BALANCE_EN                 0x00000800L
4246 #define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE     0x00001000L
4247 #define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L
4248 #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE            0x00004000L
4249
4250 #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE             0x00008000L
4251 #define ATOM_PM_MISCINFO_OVER_CLOCK_MODE                 0x00010000L
4252 #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE                 0x00020000L
4253 #define ATOM_PM_MISCINFO_POWER_SAVING_MODE               0x00040000L
4254 #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE              0x00080000L
4255
4256 #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK           0x00300000L  //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved
4257 #define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT          20
4258
4259 #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE                 0x00400000L
4260 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2      0x00800000L
4261 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4      0x01000000L
4262 #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN            0x02000000L  //When set, Dynamic
4263 #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN        0x04000000L  //When set, Dynamic
4264 #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN              0x08000000L  //When set, This mode is for acceleated 3D mode
4265
4266 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK   0x70000000L  //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks)
4267 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT  28
4268 #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS                0x80000000L
4269
4270 #define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE            0x00000001L
4271 #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT          0x00000002L
4272 #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN           0x00000004L
4273 #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO            0x00000008L
4274 #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE              0x00000010L
4275 #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN       0x00000020L
4276 #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE         0x00000040L  //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption.
4277                                                                       //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback
4278 #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC                0x00000080L
4279 #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN                0x00000100L
4280 #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE               0x00000200L
4281
4282 //ucTableFormatRevision=1
4283 //ucTableContentRevision=1
4284 typedef struct  _ATOM_POWERMODE_INFO
4285 {
4286   ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
4287   ULONG     ulReserved1;                // must set to 0
4288   ULONG     ulReserved2;                // must set to 0
4289   USHORT    usEngineClock;
4290   USHORT    usMemoryClock;
4291   UCHAR     ucVoltageDropIndex;         // index to GPIO table
4292   UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
4293   UCHAR     ucMinTemperature;
4294   UCHAR     ucMaxTemperature;
4295   UCHAR     ucNumPciELanes;             // number of PCIE lanes
4296 }ATOM_POWERMODE_INFO;
4297
4298 //ucTableFormatRevision=2
4299 //ucTableContentRevision=1
4300 typedef struct  _ATOM_POWERMODE_INFO_V2
4301 {
4302   ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
4303   ULONG     ulMiscInfo2;
4304   ULONG     ulEngineClock;
4305   ULONG     ulMemoryClock;
4306   UCHAR     ucVoltageDropIndex;         // index to GPIO table
4307   UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
4308   UCHAR     ucMinTemperature;
4309   UCHAR     ucMaxTemperature;
4310   UCHAR     ucNumPciELanes;             // number of PCIE lanes
4311 }ATOM_POWERMODE_INFO_V2;
4312
4313 //ucTableFormatRevision=2
4314 //ucTableContentRevision=2
4315 typedef struct  _ATOM_POWERMODE_INFO_V3
4316 {
4317   ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
4318   ULONG     ulMiscInfo2;
4319   ULONG     ulEngineClock;
4320   ULONG     ulMemoryClock;
4321   UCHAR     ucVoltageDropIndex;         // index to Core (VDDC) votage table
4322   UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
4323   UCHAR     ucMinTemperature;
4324   UCHAR     ucMaxTemperature;
4325   UCHAR     ucNumPciELanes;             // number of PCIE lanes
4326   UCHAR     ucVDDCI_VoltageDropIndex;   // index to VDDCI votage table
4327 }ATOM_POWERMODE_INFO_V3;
4328
4329
4330 #define ATOM_MAX_NUMBEROF_POWER_BLOCK  8
4331
4332 #define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN            0x01
4333 #define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE         0x02
4334
4335 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63      0x01
4336 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032   0x02
4337 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030   0x03
4338 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649   0x04
4339 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64      0x05
4340 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375    0x06
4341 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512   0x07      // Andigilog
4342
4343
4344 typedef struct  _ATOM_POWERPLAY_INFO
4345 {
4346   ATOM_COMMON_TABLE_HEADER      sHeader;
4347   UCHAR    ucOverdriveThermalController;
4348   UCHAR    ucOverdriveI2cLine;
4349   UCHAR    ucOverdriveIntBitmap;
4350   UCHAR    ucOverdriveControllerAddress;
4351   UCHAR    ucSizeOfPowerModeEntry;
4352   UCHAR    ucNumOfPowerModeEntries;
4353   ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
4354 }ATOM_POWERPLAY_INFO;
4355
4356 typedef struct  _ATOM_POWERPLAY_INFO_V2
4357 {
4358   ATOM_COMMON_TABLE_HEADER      sHeader;
4359   UCHAR    ucOverdriveThermalController;
4360   UCHAR    ucOverdriveI2cLine;
4361   UCHAR    ucOverdriveIntBitmap;
4362   UCHAR    ucOverdriveControllerAddress;
4363   UCHAR    ucSizeOfPowerModeEntry;
4364   UCHAR    ucNumOfPowerModeEntries;
4365   ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
4366 }ATOM_POWERPLAY_INFO_V2;
4367
4368 typedef struct  _ATOM_POWERPLAY_INFO_V3
4369 {
4370   ATOM_COMMON_TABLE_HEADER      sHeader;
4371   UCHAR    ucOverdriveThermalController;
4372   UCHAR    ucOverdriveI2cLine;
4373   UCHAR    ucOverdriveIntBitmap;
4374   UCHAR    ucOverdriveControllerAddress;
4375   UCHAR    ucSizeOfPowerModeEntry;
4376   UCHAR    ucNumOfPowerModeEntries;
4377   ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
4378 }ATOM_POWERPLAY_INFO_V3;
4379
4380
4381
4382 /**************************************************************************/
4383
4384
4385 // Following definitions are for compatiblity issue in different SW components.
4386 #define ATOM_MASTER_DATA_TABLE_REVISION   0x01
4387 #define Object_Info                                                                                             Object_Header
4388 #define AdjustARB_SEQ                                                                                   MC_InitParameter
4389 #define VRAM_GPIO_DetectionInfo                                         VoltageObjectInfo
4390 #define ASIC_VDDCI_Info                   ASIC_ProfilingInfo
4391 #define ASIC_MVDDQ_Info                                                                         MemoryTrainingInfo
4392 #define SS_Info                           PPLL_SS_Info
4393 #define ASIC_MVDDC_Info                   ASIC_InternalSS_Info
4394 #define DispDevicePriorityInfo                                          SaveRestoreInfo
4395 #define DispOutInfo                                                                                             TV_VideoMode
4396
4397
4398 #define ATOM_ENCODER_OBJECT_TABLE         ATOM_OBJECT_TABLE
4399 #define ATOM_CONNECTOR_OBJECT_TABLE       ATOM_OBJECT_TABLE
4400
4401 //New device naming, remove them when both DAL/VBIOS is ready
4402 #define DFP2I_OUTPUT_CONTROL_PARAMETERS    CRT1_OUTPUT_CONTROL_PARAMETERS
4403 #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS
4404
4405 #define DFP1X_OUTPUT_CONTROL_PARAMETERS    CRT1_OUTPUT_CONTROL_PARAMETERS
4406 #define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS
4407
4408 #define DFP1I_OUTPUT_CONTROL_PARAMETERS    DFP1_OUTPUT_CONTROL_PARAMETERS
4409 #define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION
4410
4411 #define ATOM_DEVICE_DFP1I_SUPPORT          ATOM_DEVICE_DFP1_SUPPORT
4412 #define ATOM_DEVICE_DFP1X_SUPPORT          ATOM_DEVICE_DFP2_SUPPORT
4413
4414 #define ATOM_DEVICE_DFP1I_INDEX            ATOM_DEVICE_DFP1_INDEX
4415 #define ATOM_DEVICE_DFP1X_INDEX            ATOM_DEVICE_DFP2_INDEX
4416
4417 #define ATOM_DEVICE_DFP2I_INDEX            0x00000009
4418 #define ATOM_DEVICE_DFP2I_SUPPORT          (0x1L << ATOM_DEVICE_DFP2I_INDEX)
4419
4420 #define ATOM_S0_DFP1I                      ATOM_S0_DFP1
4421 #define ATOM_S0_DFP1X                      ATOM_S0_DFP2
4422
4423 #define ATOM_S0_DFP2I                      0x00200000L
4424 #define ATOM_S0_DFP2Ib2                    0x20
4425
4426 #define ATOM_S2_DFP1I_DPMS_STATE           ATOM_S2_DFP1_DPMS_STATE
4427 #define ATOM_S2_DFP1X_DPMS_STATE           ATOM_S2_DFP2_DPMS_STATE
4428
4429 #define ATOM_S2_DFP2I_DPMS_STATE           0x02000000L
4430 #define ATOM_S2_DFP2I_DPMS_STATEb3         0x02
4431
4432 #define ATOM_S3_DFP2I_ACTIVEb1             0x02
4433
4434 #define ATOM_S3_DFP1I_ACTIVE               ATOM_S3_DFP1_ACTIVE
4435 #define ATOM_S3_DFP1X_ACTIVE               ATOM_S3_DFP2_ACTIVE
4436
4437 #define ATOM_S3_DFP2I_ACTIVE               0x00000200L
4438
4439 #define ATOM_S3_DFP1I_CRTC_ACTIVE          ATOM_S3_DFP1_CRTC_ACTIVE
4440 #define ATOM_S3_DFP1X_CRTC_ACTIVE          ATOM_S3_DFP2_CRTC_ACTIVE
4441 #define ATOM_S3_DFP2I_CRTC_ACTIVE          0x02000000L
4442
4443 #define ATOM_S3_DFP2I_CRTC_ACTIVEb3        0x02
4444 #define ATOM_S5_DOS_REQ_DFP2Ib1            0x02
4445
4446 #define ATOM_S5_DOS_REQ_DFP2I              0x0200
4447 #define ATOM_S6_ACC_REQ_DFP1I              ATOM_S6_ACC_REQ_DFP1
4448 #define ATOM_S6_ACC_REQ_DFP1X              ATOM_S6_ACC_REQ_DFP2
4449
4450 #define ATOM_S6_ACC_REQ_DFP2Ib3            0x02
4451 #define ATOM_S6_ACC_REQ_DFP2I              0x02000000L
4452
4453 #define TMDS1XEncoderControl               DVOEncoderControl
4454 #define DFP1XOutputControl                 DVOOutputControl
4455
4456 #define ExternalDFPOutputControl           DFP1XOutputControl
4457 #define EnableExternalTMDS_Encoder         TMDS1XEncoderControl
4458
4459 #define DFP1IOutputControl                 TMDSAOutputControl
4460 #define DFP2IOutputControl                 LVTMAOutputControl
4461
4462 #define DAC1_ENCODER_CONTROL_PARAMETERS    DAC_ENCODER_CONTROL_PARAMETERS
4463 #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
4464
4465 #define DAC2_ENCODER_CONTROL_PARAMETERS    DAC_ENCODER_CONTROL_PARAMETERS
4466 #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
4467
4468 #define ucDac1Standard  ucDacStandard
4469 #define ucDac2Standard  ucDacStandard
4470
4471 #define TMDS1EncoderControl TMDSAEncoderControl
4472 #define TMDS2EncoderControl LVTMAEncoderControl
4473
4474 #define DFP1OutputControl   TMDSAOutputControl
4475 #define DFP2OutputControl   LVTMAOutputControl
4476 #define CRT1OutputControl   DAC1OutputControl
4477 #define CRT2OutputControl   DAC2OutputControl
4478
4479 //These two lines will be removed for sure in a few days, will follow up with Michael V.
4480 #define EnableLVDS_SS   EnableSpreadSpectrumOnPPLL
4481 #define ENABLE_LVDS_SS_PARAMETERS_V3  ENABLE_SPREAD_SPECTRUM_ON_PPLL
4482
4483 /*********************************************************************************/
4484 #define ATOM_S3_SCALER2_ACTIVE_H          0x00004000L
4485 #define ATOM_S3_SCALER2_ACTIVE_V          0x00008000L
4486 #define ATOM_S6_REQ_SCALER2_H             0x00004000L
4487 #define ATOM_S6_REQ_SCALER2_V             0x00008000L
4488
4489 #define ATOM_S3_SCALER1_ACTIVE_H          ATOM_S3_LCD_FULLEXPANSION_ACTIVE
4490 #define ATOM_S3_SCALER1_ACTIVE_V          ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE
4491
4492 #define ATOM_S6_REQ_SCALER1_H             ATOM_S6_REQ_LCD_EXPANSION_FULL
4493 #define ATOM_S6_REQ_SCALER1_V             ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO
4494 //==========================================================================================
4495
4496 #pragma pack() // BIOS data must use byte aligment
4497
4498 #endif /* _ATOMBIOS_H */