linux-core/ati_pcigart.c

   1 /**
   2  * \file ati_pcigart.c
   3  * ATI PCI GART support
   4  *
   5  * \author Gareth Hughes <gareth@valinux.com>
   6  */
   7
   8 /*
   9  * Created: Wed Dec 13 21:52:19 2000 by gareth@valinux.com
  10  *
  11  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  12  * All Rights Reserved.
  13  *
  14  * Permission is hereby granted, free of charge, to any person obtaining a
  15  * copy of this software and associated documentation files (the "Software"),
  16  * to deal in the Software without restriction, including without limitation
  17  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  18  * and/or sell copies of the Software, and to permit persons to whom the
  19  * Software is furnished to do so, subject to the following conditions:
  20  *
  21  * The above copyright notice and this permission notice (including the next
  22  * paragraph) shall be included in all copies or substantial portions of the
  23  * Software.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  26  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  27  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  28  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  29  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  30  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  31  * DEALINGS IN THE SOFTWARE.
  32  */
  33
  34 #include "drmP.h"
  35
  36 # define ATI_PCIGART_PAGE_SIZE          4096    /**< PCI GART page size */
  37 # define ATI_PCIGART_PAGE_MASK          (~(ATI_PCIGART_PAGE_SIZE-1))
  38
  39 #define ATI_PCIE_WRITE 0x4
  40 #define ATI_PCIE_READ 0x8
  41
  42 static __inline__ void gart_insert_page_into_table(struct drm_ati_pcigart_info *gart_info, dma_addr_t addr, u32 *pci_gart)
  43 {
  44         u32 page_base;
  45
  46         page_base = (u32)addr & ATI_PCIGART_PAGE_MASK;
  47         switch(gart_info->gart_reg_if) {
  48         case DRM_ATI_GART_IGP:
  49                 page_base |= (upper_32_bits(addr) & 0xff) << 4;
  50                 page_base |= 0xc;
  51                 break;
  52         case DRM_ATI_GART_PCIE:
  53                 page_base >>= 8;
  54                 page_base |= (upper_32_bits(addr) & 0xff) << 24;
  55                 page_base |= ATI_PCIE_READ | ATI_PCIE_WRITE;
  56                 break;
  57         default:
  58         case DRM_ATI_GART_PCI:
  59                 break;
  60         }
  61         *pci_gart = cpu_to_le32(page_base);
  62 }
  63
  64 static __inline__ dma_addr_t gart_get_page_from_table(struct drm_ati_pcigart_info *gart_info, u32 *pci_gart)
  65 {
  66         dma_addr_t retval;
  67         switch(gart_info->gart_reg_if) {
  68         case DRM_ATI_GART_IGP:
  69                 retval = (*pci_gart & ATI_PCIGART_PAGE_MASK);
  70                 retval += (((*pci_gart & 0xf0) >> 4) << 16) << 16;
  71                 break;
  72         case DRM_ATI_GART_PCIE:
  73                 retval = (*pci_gart & ~0xc);
  74                 retval <<= 8;
  75                 break;
  76         case DRM_ATI_GART_PCI:
  77                 retval = *pci_gart;
  78                 break;
  79         }
  80
  81         return retval;
  82 }
  83
  84 int drm_ati_alloc_pcigart_table(struct drm_device *dev,
  85                                 struct drm_ati_pcigart_info *gart_info)
  86 {
  87         gart_info->table_handle = drm_pci_alloc(dev, gart_info->table_size,
  88                                                 PAGE_SIZE,
  89                                                 gart_info->table_mask);
  90         if (gart_info->table_handle == NULL)
  91                 return -ENOMEM;
  92
  93         memset(gart_info->table_handle->vaddr, 0, gart_info->table_size);
  94         return 0;
  95 }
  96 EXPORT_SYMBOL(drm_ati_alloc_pcigart_table);
  97
  98 static void drm_ati_free_pcigart_table(struct drm_device *dev,
  99                                        struct drm_ati_pcigart_info *gart_info)
 100 {
 101         drm_pci_free(dev, gart_info->table_handle);
 102         gart_info->table_handle = NULL;
 103 }
 104
 105 int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
 106 {
 107         struct drm_sg_mem *entry = dev->sg;
 108         unsigned long pages;
 109         int i;
 110         int max_pages;
 111
 112         /* we need to support large memory configurations */
 113         if (!entry) {
 114                 return 0;
 115         }
 116
 117         if (gart_info->bus_addr) {
 118
 119                 max_pages = (gart_info->table_size / sizeof(u32));
 120                 pages = (entry->pages <= max_pages)
 121                   ? entry->pages : max_pages;
 122
 123                 for (i = 0; i < pages; i++) {
 124                         if (!entry->busaddr[i])
 125                                 break;
 126                         pci_unmap_page(dev->pdev, entry->busaddr[i],
 127                                          PAGE_SIZE, PCI_DMA_TODEVICE);
 128                 }
 129
 130                 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
 131                         gart_info->bus_addr = 0;
 132         }
 133
 134
 135         if (gart_info->gart_table_location == DRM_ATI_GART_MAIN
 136             && gart_info->table_handle) {
 137
 138                 drm_ati_free_pcigart_table(dev, gart_info);
 139         }
 140
 141         return 1;
 142 }
 143 EXPORT_SYMBOL(drm_ati_pcigart_cleanup);
 144
 145 int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
 146 {
 147         struct drm_sg_mem *entry = dev->sg;
 148         void *address = NULL;
 149         unsigned long pages;
 150         u32 *pci_gart;
 151         dma_addr_t bus_address = 0;
 152         int i, j, ret = 0;
 153         int max_pages;
 154         dma_addr_t entry_addr;
 155
 156
 157         if (gart_info->gart_table_location == DRM_ATI_GART_MAIN && gart_info->table_handle == NULL) {
 158                 DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
 159
 160                 ret = drm_ati_alloc_pcigart_table(dev, gart_info);
 161                 if (ret) {
 162                         DRM_ERROR("cannot allocate PCI GART page!\n");
 163                         goto done;
 164                 }
 165         }
 166
 167         if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
 168                 address = gart_info->table_handle->vaddr;
 169                 bus_address = gart_info->table_handle->busaddr;
 170         } else {
 171                 address = gart_info->addr;
 172                 bus_address = gart_info->bus_addr;
 173         }
 174
 175         if (!entry) {
 176                 DRM_ERROR("no scatter/gather memory!\n");
 177                 goto done;
 178         }
 179
 180         pci_gart = (u32 *) address;
 181
 182         max_pages = (gart_info->table_size / sizeof(u32));
 183         pages = (entry->pages <= max_pages)
 184             ? entry->pages : max_pages;
 185
 186         for (i = 0; i < pages; i++) {
 187                 /* we need to support large memory configurations */
 188                 entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i],
 189                                                  0, PAGE_SIZE, PCI_DMA_TODEVICE);
 190                 if (entry->busaddr[i] == 0) {
 191                         DRM_ERROR("unable to map PCIGART pages!\n");
 192                         drm_ati_pcigart_cleanup(dev, gart_info);
 193                         address = NULL;
 194                         bus_address = 0;
 195                         goto done;
 196                 }
 197
 198                 entry_addr = entry->busaddr[i];
 199                 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
 200                         gart_insert_page_into_table(gart_info, entry_addr, pci_gart);
 201                         pci_gart++;
 202                         entry_addr += ATI_PCIGART_PAGE_SIZE;
 203                 }
 204         }
 205
 206         ret = 1;
 207
 208         mb();
 209
 210       done:
 211         gart_info->addr = address;
 212         gart_info->bus_addr = bus_address;
 213         return ret;
 214 }
 215 EXPORT_SYMBOL(drm_ati_pcigart_init);
 216
 217 static int ati_pcigart_needs_unbind_cache_adjust(struct drm_ttm_backend *backend)
 218 {
 219         return ((backend->flags & DRM_BE_FLAG_BOUND_CACHED) ? 0 : 1);
 220 }
 221
 222 static int ati_pcigart_populate(struct drm_ttm_backend *backend,
 223                                 unsigned long num_pages,
 224                                 struct page **pages,
 225                                 struct page *dummy_read_page)
 226 {
 227         struct ati_pcigart_ttm_backend *atipci_be =
 228                 container_of(backend, struct ati_pcigart_ttm_backend, backend);
 229
 230         atipci_be->pages = pages;
 231         atipci_be->num_pages = num_pages;
 232         atipci_be->populated = 1;
 233         return 0;
 234 }
 235
 236 static int ati_pcigart_bind_ttm(struct drm_ttm_backend *backend,
 237                                 struct drm_bo_mem_reg *bo_mem)
 238 {
 239         struct ati_pcigart_ttm_backend *atipci_be =
 240                 container_of(backend, struct ati_pcigart_ttm_backend, backend);
 241         off_t j;
 242         int i;
 243         struct drm_ati_pcigart_info *info = atipci_be->gart_info;
 244         u32 *pci_gart;
 245         dma_addr_t offset = bo_mem->mm_node->start;
 246         dma_addr_t page_base;
 247
 248         pci_gart = info->addr;
 249
 250         j = offset;
 251         while (j < (offset + atipci_be->num_pages)) {
 252                 if (gart_get_page_from_table(info, pci_gart+j))
 253                         return -EBUSY;
 254                 j++;
 255         }
 256
 257         for (i = 0, j = offset; i < atipci_be->num_pages; i++, j++) {
 258                 struct page *cur_page = atipci_be->pages[i];
 259                 /* write value */
 260                 page_base = page_to_phys(cur_page);
 261                 gart_insert_page_into_table(info, page_base, pci_gart + j);
 262         }
 263
 264         mb();
 265
 266         atipci_be->gart_flush_fn(atipci_be->dev);
 267
 268         atipci_be->bound = 1;
 269         atipci_be->offset = offset;
 270         /* need to traverse table and add entries */
 271         DRM_DEBUG("\n");
 272         return 0;
 273 }
 274
 275 static int ati_pcigart_unbind_ttm(struct drm_ttm_backend *backend)
 276 {
 277         struct ati_pcigart_ttm_backend *atipci_be =
 278                 container_of(backend, struct ati_pcigart_ttm_backend, backend);
 279         struct drm_ati_pcigart_info *info = atipci_be->gart_info;
 280         unsigned long offset = atipci_be->offset;
 281         int i;
 282         off_t j;
 283         u32 *pci_gart = info->addr;
 284
 285         if (atipci_be->bound != 1)
 286                 return -EINVAL;
 287
 288         for (i = 0, j = offset; i < atipci_be->num_pages; i++, j++) {
 289                 *(pci_gart + j) = 0;
 290         }
 291         atipci_be->gart_flush_fn(atipci_be->dev);
 292         atipci_be->bound = 0;
 293         atipci_be->offset = 0;
 294         return 0;
 295 }
 296
 297 static void ati_pcigart_clear_ttm(struct drm_ttm_backend *backend)
 298 {
 299         struct ati_pcigart_ttm_backend *atipci_be =
 300                 container_of(backend, struct ati_pcigart_ttm_backend, backend);
 301
 302         DRM_DEBUG("\n");
 303         if (atipci_be->pages) {
 304                 backend->func->unbind(backend);
 305                 atipci_be->pages = NULL;
 306
 307         }
 308         atipci_be->num_pages = 0;
 309 }
 310
 311 static void ati_pcigart_destroy_ttm(struct drm_ttm_backend *backend)
 312 {
 313         struct ati_pcigart_ttm_backend *atipci_be;
 314         if (backend) {
 315                 DRM_DEBUG("\n");
 316                 atipci_be = container_of(backend, struct ati_pcigart_ttm_backend, backend);
 317                 if (atipci_be) {
 318                         if (atipci_be->pages) {
 319                                 backend->func->clear(backend);
 320                         }
 321                         drm_ctl_free(atipci_be, sizeof(*atipci_be), DRM_MEM_TTM);
 322                 }
 323         }
 324 }
 325
 326 static struct drm_ttm_backend_func ati_pcigart_ttm_backend =
 327 {
 328         .needs_ub_cache_adjust = ati_pcigart_needs_unbind_cache_adjust,
 329         .populate = ati_pcigart_populate,
 330         .clear = ati_pcigart_clear_ttm,
 331         .bind = ati_pcigart_bind_ttm,
 332         .unbind = ati_pcigart_unbind_ttm,
 333         .destroy =  ati_pcigart_destroy_ttm,
 334 };
 335
 336 struct drm_ttm_backend *ati_pcigart_init_ttm(struct drm_device *dev, struct drm_ati_pcigart_info *info, void (*gart_flush_fn)(struct drm_device *dev))
 337 {
 338         struct ati_pcigart_ttm_backend *atipci_be;
 339
 340         atipci_be = drm_ctl_calloc(1, sizeof (*atipci_be), DRM_MEM_TTM);
 341         if (!atipci_be)
 342                 return NULL;
 343
 344         atipci_be->populated = 0;
 345         atipci_be->backend.func = &ati_pcigart_ttm_backend;
 346 //      atipci_be->backend.mem_type = DRM_BO_MEM_TT;
 347         atipci_be->gart_info = info;
 348         atipci_be->gart_flush_fn = gart_flush_fn;
 349         atipci_be->dev = dev;
 350
 351         return &atipci_be->backend;
 352 }
 353 EXPORT_SYMBOL(ati_pcigart_init_ttm);