linux-core/ati_pcigart.c

   1 /**
   2  * \file ati_pcigart.c
   3  * ATI PCI GART support
   4  *
   5  * \author Gareth Hughes <gareth@valinux.com>
   6  */
   7
   8 /*
   9  * Created: Wed Dec 13 21:52:19 2000 by gareth@valinux.com
  10  *
  11  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  12  * All Rights Reserved.
  13  *
  14  * Permission is hereby granted, free of charge, to any person obtaining a
  15  * copy of this software and associated documentation files (the "Software"),
  16  * to deal in the Software without restriction, including without limitation
  17  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  18  * and/or sell copies of the Software, and to permit persons to whom the
  19  * Software is furnished to do so, subject to the following conditions:
  20  *
  21  * The above copyright notice and this permission notice (including the next
  22  * paragraph) shall be included in all copies or substantial portions of the
  23  * Software.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  26  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  27  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  28  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  29  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  30  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  31  * DEALINGS IN THE SOFTWARE.
  32  */
  33
  34 #include "drmP.h"
  35
  36 # define ATI_PCIGART_PAGE_SIZE          4096    /**< PCI GART page size */
  37 # define ATI_PCIGART_PAGE_MASK          (~(ATI_PCIGART_PAGE_SIZE-1))
  38
  39 #define ATI_PCIE_WRITE 0x4
  40 #define ATI_PCIE_READ 0x8
  41
  42 static int drm_ati_alloc_pcigart_table(struct drm_device *dev,
  43                                        struct drm_ati_pcigart_info *gart_info)
  44 {
  45         gart_info->table_handle = drm_pci_alloc(dev, gart_info->table_size,
  46                                                 PAGE_SIZE,
  47                                                 gart_info->table_mask);
  48         if (gart_info->table_handle == NULL)
  49                 return -ENOMEM;
  50
  51         return 0;
  52 }
  53
  54 static void drm_ati_free_pcigart_table(struct drm_device *dev,
  55                                        struct drm_ati_pcigart_info *gart_info)
  56 {
  57         drm_pci_free(dev, gart_info->table_handle);
  58         gart_info->table_handle = NULL;
  59 }
  60
  61 int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
  62 {
  63         struct drm_sg_mem *entry = dev->sg;
  64         unsigned long pages;
  65         int i;
  66         int max_pages;
  67
  68         /* we need to support large memory configurations */
  69         if (!entry) {
  70                 DRM_ERROR("no scatter/gather memory!\n");
  71                 return 0;
  72         }
  73
  74         if (gart_info->bus_addr) {
  75
  76                 max_pages = (gart_info->table_size / sizeof(u32));
  77                 pages = (entry->pages <= max_pages)
  78                   ? entry->pages : max_pages;
  79
  80                 for (i = 0; i < pages; i++) {
  81                         if (!entry->busaddr[i])
  82                                 break;
  83                         pci_unmap_single(dev->pdev, entry->busaddr[i],
  84                                          PAGE_SIZE, PCI_DMA_TODEVICE);
  85                 }
  86
  87                 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
  88                         gart_info->bus_addr = 0;
  89         }
  90
  91
  92         if (gart_info->gart_table_location == DRM_ATI_GART_MAIN
  93             && gart_info->table_handle) {
  94
  95                 drm_ati_free_pcigart_table(dev, gart_info);
  96         }
  97
  98         return 1;
  99 }
 100 EXPORT_SYMBOL(drm_ati_pcigart_cleanup);
 101
 102 int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
 103 {
 104         struct drm_sg_mem *entry = dev->sg;
 105         void *address = NULL;
 106         unsigned long pages;
 107         u32 *pci_gart, page_base;
 108         dma_addr_t bus_address = 0;
 109         int i, j, ret = 0;
 110         int max_pages;
 111         dma_addr_t entry_addr;
 112
 113         if (!entry) {
 114                 DRM_ERROR("no scatter/gather memory!\n");
 115                 goto done;
 116         }
 117
 118         if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
 119                 DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
 120
 121                 ret = drm_ati_alloc_pcigart_table(dev, gart_info);
 122                 if (ret) {
 123                         DRM_ERROR("cannot allocate PCI GART page!\n");
 124                         goto done;
 125                 }
 126
 127                 address = gart_info->table_handle->vaddr;
 128                 bus_address = gart_info->table_handle->busaddr;
 129         } else {
 130                 address = gart_info->addr;
 131                 bus_address = gart_info->bus_addr;
 132                 DRM_DEBUG("PCI: Gart Table: VRAM %08X mapped at %08lX\n",
 133                           bus_address, (unsigned long)address);
 134         }
 135
 136         pci_gart = (u32 *) address;
 137
 138         max_pages = (gart_info->table_size / sizeof(u32));
 139         pages = (entry->pages <= max_pages)
 140             ? entry->pages : max_pages;
 141
 142         memset(pci_gart, 0, max_pages * sizeof(u32));
 143
 144         for (i = 0; i < pages; i++) {
 145                 /* we need to support large memory configurations */
 146                 entry->busaddr[i] = pci_map_single(dev->pdev,
 147                                                    page_address(entry->
 148                                                                 pagelist[i]),
 149                                                    PAGE_SIZE, PCI_DMA_TODEVICE);
 150                 if (entry->busaddr[i] == 0) {
 151                         DRM_ERROR("unable to map PCIGART pages!\n");
 152                         drm_ati_pcigart_cleanup(dev, gart_info);
 153                         address = NULL;
 154                         bus_address = 0;
 155                         goto done;
 156                 }
 157
 158                 entry_addr = entry->busaddr[i];
 159                 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
 160                         page_base = (u32) entry_addr & ATI_PCIGART_PAGE_MASK;
 161                         switch(gart_info->gart_reg_if) {
 162                         case DRM_ATI_GART_IGP:
 163                                 page_base |= (upper_32_bits(entry_addr) & 0xff) << 4;
 164                                 page_base |= 0xc;
 165                                 break;
 166                         case DRM_ATI_GART_PCIE:
 167                                 page_base >>= 8;
 168                                 page_base |= (upper_32_bits(entry_addr) & 0xff) << 24;
 169                                 page_base |= ATI_PCIE_READ | ATI_PCIE_WRITE;
 170                                 break;
 171                         default:
 172                         case DRM_ATI_GART_PCI:
 173                                 break;
 174                         }
 175                         *pci_gart = cpu_to_le32(page_base);
 176                         pci_gart++;
 177                         entry_addr += ATI_PCIGART_PAGE_SIZE;
 178                 }
 179         }
 180
 181         ret = 1;
 182
 183 #if defined(__i386__) || defined(__x86_64__)
 184         wbinvd();
 185 #else
 186         mb();
 187 #endif
 188
 189       done:
 190         gart_info->addr = address;
 191         gart_info->bus_addr = bus_address;
 192         return ret;
 193 }
 194 EXPORT_SYMBOL(drm_ati_pcigart_init);