linux/radeon_state.c

   1 /* radeon_state.c -- State support for Radeon -*- linux-c -*-
   2  *
   3  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *    Gareth Hughes <gareth@valinux.com>
  27  *    Kevin E. Martin <martin@valinux.com>
  28  */
  29
  30 #define __NO_VERSION__
  31 #include "radeon.h"
  32 #include "drmP.h"
  33 #include "radeon_drv.h"
  34 #include "drm.h"
  35 #include <linux/delay.h>
  36
  37
  38 /* ================================================================
  39  * CP hardware state programming functions
  40  */
  41
  42 static inline void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv,
  43                                           drm_clip_rect_t *box )
  44 {
  45         RING_LOCALS;
  46
  47         DRM_DEBUG( "   box:  x1=%d y1=%d  x2=%d y2=%d\n",
  48                    box->x1, box->y1, box->x2, box->y2 );
  49
  50         BEGIN_RING( 4 );
  51
  52         OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) );
  53         OUT_RING( (box->y1 << 16) | box->x1 );
  54
  55         OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) );
  56         OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) );
  57
  58         ADVANCE_RING();
  59 }
  60
  61 static inline void radeon_emit_context( drm_radeon_private_t *dev_priv )
  62 {
  63         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
  64         drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
  65         RING_LOCALS;
  66         DRM_DEBUG( "    %s\n", __FUNCTION__ );
  67
  68         BEGIN_RING( 14 );
  69
  70         OUT_RING( CP_PACKET0( RADEON_PP_MISC, 6 ) );
  71         OUT_RING( ctx->pp_misc );
  72         OUT_RING( ctx->pp_fog_color );
  73         OUT_RING( ctx->re_solid_color );
  74         OUT_RING( ctx->rb3d_blendcntl );
  75         OUT_RING( ctx->rb3d_depthoffset );
  76         OUT_RING( ctx->rb3d_depthpitch );
  77         OUT_RING( ctx->rb3d_zstencilcntl );
  78
  79         OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 2 ) );
  80         OUT_RING( ctx->pp_cntl );
  81         OUT_RING( ctx->rb3d_cntl );
  82         OUT_RING( ctx->rb3d_coloroffset );
  83
  84         OUT_RING( CP_PACKET0( RADEON_RB3D_COLORPITCH, 0 ) );
  85         OUT_RING( ctx->rb3d_colorpitch );
  86
  87         ADVANCE_RING();
  88 }
  89
  90 static inline void radeon_emit_vertfmt( drm_radeon_private_t *dev_priv )
  91 {
  92         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
  93         drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
  94         RING_LOCALS;
  95         DRM_DEBUG( "    %s\n", __FUNCTION__ );
  96
  97         BEGIN_RING( 2 );
  98
  99         OUT_RING( CP_PACKET0( RADEON_SE_COORD_FMT, 0 ) );
 100         OUT_RING( ctx->se_coord_fmt );
 101
 102         ADVANCE_RING();
 103 }
 104
 105 static inline void radeon_emit_line( drm_radeon_private_t *dev_priv )
 106 {
 107         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 108         drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
 109         RING_LOCALS;
 110         DRM_DEBUG( "    %s\n", __FUNCTION__ );
 111
 112         BEGIN_RING( 5 );
 113
 114         OUT_RING( CP_PACKET0( RADEON_RE_LINE_PATTERN, 1 ) );
 115         OUT_RING( ctx->re_line_pattern );
 116         OUT_RING( ctx->re_line_state );
 117
 118         OUT_RING( CP_PACKET0( RADEON_SE_LINE_WIDTH, 0 ) );
 119         OUT_RING( ctx->se_line_width );
 120
 121         ADVANCE_RING();
 122 }
 123
 124 static inline void radeon_emit_bumpmap( drm_radeon_private_t *dev_priv )
 125 {
 126         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 127         drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
 128         RING_LOCALS;
 129         DRM_DEBUG( "    %s\n", __FUNCTION__ );
 130
 131         BEGIN_RING( 5 );
 132
 133         OUT_RING( CP_PACKET0( RADEON_PP_LUM_MATRIX, 0 ) );
 134         OUT_RING( ctx->pp_lum_matrix );
 135
 136         OUT_RING( CP_PACKET0( RADEON_PP_ROT_MATRIX_0, 1 ) );
 137         OUT_RING( ctx->pp_rot_matrix_0 );
 138         OUT_RING( ctx->pp_rot_matrix_1 );
 139
 140         ADVANCE_RING();
 141 }
 142
 143 static inline void radeon_emit_masks( drm_radeon_private_t *dev_priv )
 144 {
 145         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 146         drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
 147         RING_LOCALS;
 148         DRM_DEBUG( "    %s\n", __FUNCTION__ );
 149
 150         BEGIN_RING( 4 );
 151
 152         OUT_RING( CP_PACKET0( RADEON_RB3D_STENCILREFMASK, 2 ) );
 153         OUT_RING( ctx->rb3d_stencilrefmask );
 154         OUT_RING( ctx->rb3d_ropcntl );
 155         OUT_RING( ctx->rb3d_planemask );
 156
 157         ADVANCE_RING();
 158 }
 159
 160 static inline void radeon_emit_viewport( drm_radeon_private_t *dev_priv )
 161 {
 162         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 163         drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
 164         RING_LOCALS;
 165         DRM_DEBUG( "    %s\n", __FUNCTION__ );
 166
 167         BEGIN_RING( 7 );
 168
 169         OUT_RING( CP_PACKET0( RADEON_SE_VPORT_XSCALE, 5 ) );
 170         OUT_RING( ctx->se_vport_xscale );
 171         OUT_RING( ctx->se_vport_xoffset );
 172         OUT_RING( ctx->se_vport_yscale );
 173         OUT_RING( ctx->se_vport_yoffset );
 174         OUT_RING( ctx->se_vport_zscale );
 175         OUT_RING( ctx->se_vport_zoffset );
 176
 177         ADVANCE_RING();
 178 }
 179
 180 static inline void radeon_emit_setup( drm_radeon_private_t *dev_priv )
 181 {
 182         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 183         drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
 184         RING_LOCALS;
 185         DRM_DEBUG( "    %s\n", __FUNCTION__ );
 186
 187         BEGIN_RING( 4 );
 188
 189         OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) );
 190         OUT_RING( ctx->se_cntl );
 191         OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) );
 192         OUT_RING( ctx->se_cntl_status );
 193
 194         ADVANCE_RING();
 195 }
 196
 197 static inline void radeon_emit_tcl( drm_radeon_private_t *dev_priv )
 198 {
 199 #ifdef TCL_ENABLE
 200         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 201         drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
 202         RING_LOCALS;
 203         DRM_DEBUG( "    %s\n", __FUNCTION__ );
 204
 205         BEGIN_RING( 29 );
 206
 207         OUT_RING( CP_PACKET0( RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 27 ) );
 208         OUT_RING( ctx->se_tcl_material_emmissive.red );
 209         OUT_RING( ctx->se_tcl_material_emmissive.green );
 210         OUT_RING( ctx->se_tcl_material_emmissive.blue );
 211         OUT_RING( ctx->se_tcl_material_emmissive.alpha );
 212         OUT_RING( ctx->se_tcl_material_ambient.red );
 213         OUT_RING( ctx->se_tcl_material_ambient.green );
 214         OUT_RING( ctx->se_tcl_material_ambient.blue );
 215         OUT_RING( ctx->se_tcl_material_ambient.alpha );
 216         OUT_RING( ctx->se_tcl_material_diffuse.red );
 217         OUT_RING( ctx->se_tcl_material_diffuse.green );
 218         OUT_RING( ctx->se_tcl_material_diffuse.blue );
 219         OUT_RING( ctx->se_tcl_material_diffuse.alpha );
 220         OUT_RING( ctx->se_tcl_material_specular.red );
 221         OUT_RING( ctx->se_tcl_material_specular.green );
 222         OUT_RING( ctx->se_tcl_material_specular.blue );
 223         OUT_RING( ctx->se_tcl_material_specular.alpha );
 224         OUT_RING( ctx->se_tcl_shininess );
 225         OUT_RING( ctx->se_tcl_output_vtx_fmt );
 226         OUT_RING( ctx->se_tcl_output_vtx_sel );
 227         OUT_RING( ctx->se_tcl_matrix_select_0 );
 228         OUT_RING( ctx->se_tcl_matrix_select_1 );
 229         OUT_RING( ctx->se_tcl_ucp_vert_blend_ctl );
 230         OUT_RING( ctx->se_tcl_texture_proc_ctl );
 231         OUT_RING( ctx->se_tcl_light_model_ctl );
 232         for ( i = 0 ; i < 4 ; i++ ) {
 233                 OUT_RING( ctx->se_tcl_per_light_ctl[i] );
 234         }
 235
 236         ADVANCE_RING();
 237 #else
 238         DRM_ERROR( "TCL not enabled!\n" );
 239 #endif
 240 }
 241
 242 static inline void radeon_emit_misc( drm_radeon_private_t *dev_priv )
 243 {
 244         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 245         drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
 246         RING_LOCALS;
 247         DRM_DEBUG( "    %s\n", __FUNCTION__ );
 248
 249         BEGIN_RING( 2 );
 250
 251         OUT_RING( CP_PACKET0( RADEON_RE_MISC, 0 ) );
 252         OUT_RING( ctx->re_misc );
 253
 254         ADVANCE_RING();
 255 }
 256
 257 static inline void radeon_emit_tex0( drm_radeon_private_t *dev_priv )
 258 {
 259         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 260         drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[0];
 261         RING_LOCALS;
 262         DRM_DEBUG( "    %s: offset=0x%x\n", __FUNCTION__, tex->pp_txoffset );
 263
 264         BEGIN_RING( 9 );
 265
 266         OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) );
 267         OUT_RING( tex->pp_txfilter );
 268         OUT_RING( tex->pp_txformat );
 269         OUT_RING( tex->pp_txoffset );
 270         OUT_RING( tex->pp_txcblend );
 271         OUT_RING( tex->pp_txablend );
 272         OUT_RING( tex->pp_tfactor );
 273
 274         OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) );
 275         OUT_RING( tex->pp_border_color );
 276
 277         ADVANCE_RING();
 278 }
 279
 280 static inline void radeon_emit_tex1( drm_radeon_private_t *dev_priv )
 281 {
 282         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 283         drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[1];
 284         RING_LOCALS;
 285         DRM_DEBUG( "    %s: offset=0x%x\n", __FUNCTION__, tex->pp_txoffset );
 286
 287         BEGIN_RING( 9 );
 288
 289         OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) );
 290         OUT_RING( tex->pp_txfilter );
 291         OUT_RING( tex->pp_txformat );
 292         OUT_RING( tex->pp_txoffset );
 293         OUT_RING( tex->pp_txcblend );
 294         OUT_RING( tex->pp_txablend );
 295         OUT_RING( tex->pp_tfactor );
 296
 297         OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) );
 298         OUT_RING( tex->pp_border_color );
 299
 300         ADVANCE_RING();
 301 }
 302
 303 static inline void radeon_emit_tex2( drm_radeon_private_t *dev_priv )
 304 {
 305         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 306         drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[2];
 307         RING_LOCALS;
 308         DRM_DEBUG( "    %s\n", __FUNCTION__ );
 309
 310         BEGIN_RING( 9 );
 311
 312         OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) );
 313         OUT_RING( tex->pp_txfilter );
 314         OUT_RING( tex->pp_txformat );
 315         OUT_RING( tex->pp_txoffset );
 316         OUT_RING( tex->pp_txcblend );
 317         OUT_RING( tex->pp_txablend );
 318         OUT_RING( tex->pp_tfactor );
 319
 320         OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) );
 321         OUT_RING( tex->pp_border_color );
 322
 323         ADVANCE_RING();
 324 }
 325
 326 static inline void radeon_emit_state( drm_radeon_private_t *dev_priv )
 327 {
 328         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 329         unsigned int dirty = sarea_priv->dirty;
 330
 331         DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty );
 332
 333         if ( dirty & RADEON_UPLOAD_CONTEXT ) {
 334                 radeon_emit_context( dev_priv );
 335                 sarea_priv->dirty &= ~RADEON_UPLOAD_CONTEXT;
 336         }
 337
 338         if ( dirty & RADEON_UPLOAD_VERTFMT ) {
 339                 radeon_emit_vertfmt( dev_priv );
 340                 sarea_priv->dirty &= ~RADEON_UPLOAD_VERTFMT;
 341         }
 342
 343         if ( dirty & RADEON_UPLOAD_LINE ) {
 344                 radeon_emit_line( dev_priv );
 345                 sarea_priv->dirty &= ~RADEON_UPLOAD_LINE;
 346         }
 347
 348         if ( dirty & RADEON_UPLOAD_BUMPMAP ) {
 349                 radeon_emit_bumpmap( dev_priv );
 350                 sarea_priv->dirty &= ~RADEON_UPLOAD_BUMPMAP;
 351         }
 352
 353         if ( dirty & RADEON_UPLOAD_MASKS ) {
 354                 radeon_emit_masks( dev_priv );
 355                 sarea_priv->dirty &= ~RADEON_UPLOAD_MASKS;
 356         }
 357
 358         if ( dirty & RADEON_UPLOAD_VIEWPORT ) {
 359                 radeon_emit_viewport( dev_priv );
 360                 sarea_priv->dirty &= ~RADEON_UPLOAD_VIEWPORT;
 361         }
 362
 363         if ( dirty & RADEON_UPLOAD_SETUP ) {
 364                 radeon_emit_setup( dev_priv );
 365                 sarea_priv->dirty &= ~RADEON_UPLOAD_SETUP;
 366         }
 367
 368         if ( dirty & RADEON_UPLOAD_TCL ) {
 369 #ifdef TCL_ENABLE
 370                 radeon_emit_tcl( dev_priv );
 371 #endif
 372                 sarea_priv->dirty &= ~RADEON_UPLOAD_TCL;
 373         }
 374
 375         if ( dirty & RADEON_UPLOAD_MISC ) {
 376                 radeon_emit_misc( dev_priv );
 377                 sarea_priv->dirty &= ~RADEON_UPLOAD_MISC;
 378         }
 379
 380         if ( dirty & RADEON_UPLOAD_TEX0 ) {
 381                 radeon_emit_tex0( dev_priv );
 382                 sarea_priv->dirty &= ~RADEON_UPLOAD_TEX0;
 383         }
 384
 385         if ( dirty & RADEON_UPLOAD_TEX1 ) {
 386                 radeon_emit_tex1( dev_priv );
 387                 sarea_priv->dirty &= ~RADEON_UPLOAD_TEX1;
 388         }
 389
 390         if ( dirty & RADEON_UPLOAD_TEX2 ) {
 391 #if 0
 392                 radeon_emit_tex2( dev_priv );
 393 #endif
 394                 sarea_priv->dirty &= ~RADEON_UPLOAD_TEX2;
 395         }
 396
 397         sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
 398                                RADEON_UPLOAD_TEX1IMAGES |
 399                                RADEON_UPLOAD_TEX2IMAGES |
 400                                RADEON_REQUIRE_QUIESCENCE);
 401 }
 402
 403
 404 #if RADEON_PERFORMANCE_BOXES
 405 /* ================================================================
 406  * Performance monitoring functions
 407  */
 408
 409 static void radeon_clear_box( drm_radeon_private_t *dev_priv,
 410                               int x, int y, int w, int h,
 411                               int r, int g, int b )
 412 {
 413         u32 pitch, offset;
 414         u32 color;
 415         RING_LOCALS;
 416
 417         switch ( dev_priv->color_fmt ) {
 418         case RADEON_COLOR_FORMAT_RGB565:
 419                 color = (((r & 0xf8) << 8) |
 420                          ((g & 0xfc) << 3) |
 421                          ((b & 0xf8) >> 3));
 422                 break;
 423         case RADEON_COLOR_FORMAT_ARGB8888:
 424         default:
 425                 color = (((0xff) << 24) | (r << 16) | (g <<  8) | b);
 426                 break;
 427         }
 428
 429         offset = dev_priv->back_offset;
 430         pitch = dev_priv->back_pitch >> 3;
 431
 432         BEGIN_RING( 6 );
 433
 434         OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
 435         OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 436                   RADEON_GMC_BRUSH_SOLID_COLOR |
 437                   (dev_priv->color_fmt << 8) |
 438                   RADEON_GMC_SRC_DATATYPE_COLOR |
 439                   RADEON_ROP3_P |
 440                   RADEON_GMC_CLR_CMP_CNTL_DIS );
 441
 442         OUT_RING( (pitch << 22) | (offset >> 5) );
 443         OUT_RING( color );
 444
 445         OUT_RING( (x << 16) | y );
 446         OUT_RING( (w << 16) | h );
 447
 448         ADVANCE_RING();
 449 }
 450
 451 static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv )
 452 {
 453         if ( atomic_read( &dev_priv->idle_count ) == 0 ) {
 454                 radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 );
 455         } else {
 456                 atomic_set( &dev_priv->idle_count, 0 );
 457         }
 458 }
 459
 460 #endif
 461
 462
 463 /* ================================================================
 464  * CP command dispatch functions
 465  */
 466
 467 static void radeon_print_dirty( const char *msg, unsigned int flags )
 468 {
 469         DRM_DEBUG( "%s: (0x%x) %s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
 470                    msg,
 471                    flags,
 472                    (flags & RADEON_UPLOAD_CONTEXT)     ? "context, " : "",
 473                    (flags & RADEON_UPLOAD_VERTFMT)     ? "vertfmt, " : "",
 474                    (flags & RADEON_UPLOAD_LINE)        ? "line, " : "",
 475                    (flags & RADEON_UPLOAD_BUMPMAP)     ? "bumpmap, " : "",
 476                    (flags & RADEON_UPLOAD_MASKS)       ? "masks, " : "",
 477                    (flags & RADEON_UPLOAD_VIEWPORT)    ? "viewport, " : "",
 478                    (flags & RADEON_UPLOAD_SETUP)       ? "setup, " : "",
 479                    (flags & RADEON_UPLOAD_TCL)         ? "tcl, " : "",
 480                    (flags & RADEON_UPLOAD_MISC)        ? "misc, " : "",
 481                    (flags & RADEON_UPLOAD_TEX0)        ? "tex0, " : "",
 482                    (flags & RADEON_UPLOAD_TEX1)        ? "tex1, " : "",
 483                    (flags & RADEON_UPLOAD_TEX2)        ? "tex2, " : "",
 484                    (flags & RADEON_UPLOAD_CLIPRECTS)   ? "cliprects, " : "",
 485                    (flags & RADEON_REQUIRE_QUIESCENCE) ? "quiescence, " : "" );
 486 }
 487
 488 static void radeon_cp_dispatch_clear( drm_device_t *dev,
 489                                       drm_radeon_clear_t *clear,
 490                                       drm_radeon_clear_rect_t *depth_boxes )
 491 {
 492         drm_radeon_private_t *dev_priv = dev->dev_private;
 493         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 494         int nbox = sarea_priv->nbox;
 495         drm_clip_rect_t *pbox = sarea_priv->boxes;
 496         unsigned int flags = clear->flags;
 497         int i;
 498         RING_LOCALS;
 499         DRM_DEBUG( "%s\n", __FUNCTION__ );
 500
 501         radeon_update_ring_snapshot( dev_priv );
 502
 503         if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
 504                 unsigned int tmp = flags;
 505
 506                 flags &= ~(RADEON_FRONT | RADEON_BACK);
 507                 if ( tmp & RADEON_FRONT ) flags |= RADEON_BACK;
 508                 if ( tmp & RADEON_BACK )  flags |= RADEON_FRONT;
 509         }
 510
 511         for ( i = 0 ; i < nbox ; i++ ) {
 512                 int x = pbox[i].x1;
 513                 int y = pbox[i].y1;
 514                 int w = pbox[i].x2 - x;
 515                 int h = pbox[i].y2 - y;
 516
 517                 DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
 518                            x, y, w, h, flags );
 519
 520                 if ( flags & (RADEON_FRONT | RADEON_BACK) ) {
 521                         BEGIN_RING( 4 );
 522
 523                         /* Ensure the 3D stream is idle before doing a
 524                          * 2D fill to clear the front or back buffer.
 525                          */
 526                         RADEON_WAIT_UNTIL_3D_IDLE();
 527
 528                         OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
 529                         OUT_RING( clear->color_mask );
 530
 531                         ADVANCE_RING();
 532
 533                         /* Make sure we restore the 3D state next time.
 534                          */
 535                         dev_priv->sarea_priv->dirty |= (RADEON_UPLOAD_CONTEXT |
 536                                                         RADEON_UPLOAD_MASKS);
 537                 }
 538
 539                 if ( flags & RADEON_FRONT ) {
 540                         BEGIN_RING( 6 );
 541
 542                         OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
 543                         OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 544                                   RADEON_GMC_BRUSH_SOLID_COLOR |
 545                                   (dev_priv->color_fmt << 8) |
 546                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 547                                   RADEON_ROP3_P |
 548                                   RADEON_GMC_CLR_CMP_CNTL_DIS );
 549
 550                         OUT_RING( dev_priv->front_pitch_offset );
 551                         OUT_RING( clear->clear_color );
 552
 553                         OUT_RING( (x << 16) | y );
 554                         OUT_RING( (w << 16) | h );
 555
 556                         ADVANCE_RING();
 557                 }
 558
 559                 if ( flags & RADEON_BACK ) {
 560                         BEGIN_RING( 6 );
 561
 562                         OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
 563                         OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 564                                   RADEON_GMC_BRUSH_SOLID_COLOR |
 565                                   (dev_priv->color_fmt << 8) |
 566                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 567                                   RADEON_ROP3_P |
 568                                   RADEON_GMC_CLR_CMP_CNTL_DIS );
 569
 570                         OUT_RING( dev_priv->back_pitch_offset );
 571                         OUT_RING( clear->clear_color );
 572
 573                         OUT_RING( (x << 16) | y );
 574                         OUT_RING( (w << 16) | h );
 575
 576                         ADVANCE_RING();
 577
 578                 }
 579
 580                 if ( flags & RADEON_DEPTH ) {
 581                         drm_radeon_depth_clear_t *depth_clear =
 582                            &dev_priv->depth_clear;
 583
 584                         if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
 585                                 radeon_emit_state( dev_priv );
 586                         }
 587
 588                         /* FIXME: Render a rectangle to clear the depth
 589                          * buffer.  So much for those "fast Z clears"...
 590                          */
 591                         BEGIN_RING( 23 );
 592
 593                         RADEON_WAIT_UNTIL_2D_IDLE();
 594
 595                         OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) );
 596                         OUT_RING( 0x00000000 );
 597                         OUT_RING( depth_clear->rb3d_cntl );
 598                         OUT_RING( CP_PACKET0( RADEON_RB3D_ZSTENCILCNTL, 0 ) );
 599                         OUT_RING( depth_clear->rb3d_zstencilcntl );
 600                         OUT_RING( CP_PACKET0( RADEON_RB3D_PLANEMASK, 0 ) );
 601                         OUT_RING( 0x00000000 );
 602                         OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) );
 603                         OUT_RING( depth_clear->se_cntl );
 604
 605                         OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 10 ) );
 606                         OUT_RING( RADEON_VTX_Z_PRESENT );
 607                         OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST |
 608                                    RADEON_PRIM_WALK_RING |
 609                                    RADEON_MAOS_ENABLE |
 610                                    RADEON_VTX_FMT_RADEON_MODE |
 611                                    (3 << RADEON_NUM_VERTICES_SHIFT)) );
 612
 613                         OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
 614                         OUT_RING( depth_boxes[i].ui[CLEAR_Y1] );
 615                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 616
 617                         OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
 618                         OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
 619                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 620
 621                         OUT_RING( depth_boxes[i].ui[CLEAR_X2] );
 622                         OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
 623                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 624
 625                         ADVANCE_RING();
 626
 627                         /* Make sure we restore the 3D state next time.
 628                          */
 629                         dev_priv->sarea_priv->dirty |= (RADEON_UPLOAD_CONTEXT |
 630                                                         RADEON_UPLOAD_SETUP |
 631                                                         RADEON_UPLOAD_MASKS);
 632                 }
 633         }
 634
 635         /* Increment the clear counter.  The client-side 3D driver must
 636          * wait on this value before performing the clear ioctl.  We
 637          * need this because the card's so damned fast...
 638          */
 639         dev_priv->sarea_priv->last_clear++;
 640
 641         BEGIN_RING( 4 );
 642
 643         RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear );
 644         RADEON_WAIT_UNTIL_IDLE();
 645
 646         ADVANCE_RING();
 647 }
 648
 649 static void radeon_cp_dispatch_swap( drm_device_t *dev )
 650 {
 651         drm_radeon_private_t *dev_priv = dev->dev_private;
 652         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 653         int nbox = sarea_priv->nbox;
 654         drm_clip_rect_t *pbox = sarea_priv->boxes;
 655         int i;
 656         RING_LOCALS;
 657         DRM_DEBUG( "%s\n", __FUNCTION__ );
 658
 659         radeon_update_ring_snapshot( dev_priv );
 660
 661 #if RADEON_PERFORMANCE_BOXES
 662         /* Do some trivial performance monitoring...
 663          */
 664         radeon_cp_performance_boxes( dev_priv );
 665 #endif
 666
 667         /* Wait for the 3D stream to idle before dispatching the bitblt.
 668          * This will prevent data corruption between the two streams.
 669          */
 670         BEGIN_RING( 2 );
 671
 672         RADEON_WAIT_UNTIL_3D_IDLE();
 673
 674         ADVANCE_RING();
 675
 676         for ( i = 0 ; i < nbox ; i++ ) {
 677                 int x = pbox[i].x1;
 678                 int y = pbox[i].y1;
 679                 int w = pbox[i].x2 - x;
 680                 int h = pbox[i].y2 - y;
 681
 682                 DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n",
 683                            x, y, w, h );
 684
 685                 BEGIN_RING( 7 );
 686
 687                 OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) );
 688                 OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 689                           RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 690                           RADEON_GMC_BRUSH_NONE |
 691                           (dev_priv->color_fmt << 8) |
 692                           RADEON_GMC_SRC_DATATYPE_COLOR |
 693                           RADEON_ROP3_S |
 694                           RADEON_DP_SRC_SOURCE_MEMORY |
 695                           RADEON_GMC_CLR_CMP_CNTL_DIS |
 696                           RADEON_GMC_WR_MSK_DIS );
 697
 698                 OUT_RING( dev_priv->back_pitch_offset );
 699                 OUT_RING( dev_priv->front_pitch_offset );
 700
 701                 OUT_RING( (x << 16) | y );
 702                 OUT_RING( (x << 16) | y );
 703                 OUT_RING( (w << 16) | h );
 704
 705                 ADVANCE_RING();
 706         }
 707
 708         /* Increment the frame counter.  The client-side 3D driver must
 709          * throttle the framerate by waiting for this value before
 710          * performing the swapbuffer ioctl.
 711          */
 712         dev_priv->sarea_priv->last_frame++;
 713
 714         BEGIN_RING( 4 );
 715
 716         RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
 717         RADEON_WAIT_UNTIL_2D_IDLE();
 718
 719         ADVANCE_RING();
 720 }
 721
 722 static void radeon_cp_dispatch_flip( drm_device_t *dev )
 723 {
 724         drm_radeon_private_t *dev_priv = dev->dev_private;
 725         RING_LOCALS;
 726         DRM_DEBUG( "%s: page=%d\n", __FUNCTION__, dev_priv->current_page );
 727
 728         radeon_update_ring_snapshot( dev_priv );
 729
 730 #if RADEON_PERFORMANCE_BOXES
 731         /* Do some trivial performance monitoring...
 732          */
 733         radeon_cp_performance_boxes( dev_priv );
 734 #endif
 735
 736         BEGIN_RING( 6 );
 737
 738         RADEON_WAIT_UNTIL_3D_IDLE();
 739         RADEON_WAIT_UNTIL_PAGE_FLIPPED();
 740
 741         OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET, 0 ) );
 742
 743         if ( dev_priv->current_page == 0 ) {
 744                 OUT_RING( dev_priv->back_offset );
 745                 dev_priv->current_page = 1;
 746         } else {
 747                 OUT_RING( dev_priv->front_offset );
 748                 dev_priv->current_page = 0;
 749         }
 750
 751         ADVANCE_RING();
 752
 753         /* Increment the frame counter.  The client-side 3D driver must
 754          * throttle the framerate by waiting for this value before
 755          * performing the swapbuffer ioctl.
 756          */
 757         dev_priv->sarea_priv->last_frame++;
 758
 759         BEGIN_RING( 2 );
 760
 761         RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
 762
 763         ADVANCE_RING();
 764 }
 765
 766 static void radeon_cp_dispatch_vertex( drm_device_t *dev,
 767                                        drm_buf_t *buf )
 768 {
 769         drm_radeon_private_t *dev_priv = dev->dev_private;
 770         drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
 771         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 772         int format = sarea_priv->vc_format;
 773         int offset = dev_priv->agp_buffers_offset + buf->offset;
 774         int size = buf->used;
 775         int prim = buf_priv->prim;
 776         int i = 0;
 777         RING_LOCALS;
 778         DRM_DEBUG( "%s: nbox=%d\n", __FUNCTION__, sarea_priv->nbox );
 779
 780         radeon_update_ring_snapshot( dev_priv );
 781
 782         if ( 0 )
 783                 radeon_print_dirty( "dispatch_vertex", sarea_priv->dirty );
 784
 785         if ( buf->used ) {
 786                 buf_priv->dispatched = 1;
 787
 788                 if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
 789                         radeon_emit_state( dev_priv );
 790                 }
 791
 792                 do {
 793                         /* Emit the next set of up to three cliprects */
 794                         if ( i < sarea_priv->nbox ) {
 795                                 radeon_emit_clip_rect( dev_priv,
 796                                                        &sarea_priv->boxes[i] );
 797                         }
 798
 799                         /* Emit the vertex buffer rendering commands */
 800                         BEGIN_RING( 5 );
 801
 802                         OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) );
 803                         OUT_RING( offset );
 804                         OUT_RING( size );
 805                         OUT_RING( format );
 806                         OUT_RING( prim | RADEON_PRIM_WALK_LIST |
 807                                   RADEON_COLOR_ORDER_RGBA |
 808                                   RADEON_VTX_FMT_RADEON_MODE |
 809                                   (size << RADEON_NUM_VERTICES_SHIFT) );
 810
 811                         ADVANCE_RING();
 812
 813                         i++;
 814                 } while ( i < sarea_priv->nbox );
 815         }
 816
 817         if ( buf_priv->discard ) {
 818                 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
 819
 820                 /* Emit the vertex buffer age */
 821                 BEGIN_RING( 2 );
 822                 RADEON_DISPATCH_AGE( buf_priv->age );
 823                 ADVANCE_RING();
 824
 825                 buf->pending = 1;
 826                 buf->used = 0;
 827                 /* FIXME: Check dispatched field */
 828                 buf_priv->dispatched = 0;
 829         }
 830
 831         dev_priv->sarea_priv->last_dispatch++;
 832
 833         sarea_priv->dirty &= ~RADEON_UPLOAD_CLIPRECTS;
 834         sarea_priv->nbox = 0;
 835 }
 836
 837
 838 static void radeon_cp_dispatch_indirect( drm_device_t *dev,
 839                                          drm_buf_t *buf,
 840                                          int start, int end )
 841 {
 842         drm_radeon_private_t *dev_priv = dev->dev_private;
 843         drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
 844         RING_LOCALS;
 845         DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n",
 846                    buf->idx, start, end );
 847
 848         radeon_update_ring_snapshot( dev_priv );
 849
 850         if ( start != end ) {
 851                 int offset = (dev_priv->agp_buffers_offset
 852                               + buf->offset + start);
 853                 int dwords = (end - start + 3) / sizeof(u32);
 854
 855                 /* Indirect buffer data must be an even number of
 856                  * dwords, so if we've been given an odd number we must
 857                  * pad the data with a Type-2 CP packet.
 858                  */
 859                 if ( dwords & 1 ) {
 860                         u32 *data = (u32 *)
 861                                 ((char *)dev_priv->buffers->handle
 862                                  + buf->offset + start);
 863                         data[dwords++] = RADEON_CP_PACKET2;
 864                 }
 865
 866                 buf_priv->dispatched = 1;
 867
 868                 /* Fire off the indirect buffer */
 869                 BEGIN_RING( 3 );
 870
 871                 OUT_RING( CP_PACKET0( RADEON_CP_IB_BASE, 1 ) );
 872                 OUT_RING( offset );
 873                 OUT_RING( dwords );
 874
 875                 ADVANCE_RING();
 876         }
 877
 878         if ( buf_priv->discard ) {
 879                 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
 880
 881                 /* Emit the indirect buffer age */
 882                 BEGIN_RING( 2 );
 883                 RADEON_DISPATCH_AGE( buf_priv->age );
 884                 ADVANCE_RING();
 885
 886                 buf->pending = 1;
 887                 buf->used = 0;
 888                 /* FIXME: Check dispatched field */
 889                 buf_priv->dispatched = 0;
 890         }
 891
 892         dev_priv->sarea_priv->last_dispatch++;
 893 }
 894
 895 static void radeon_cp_dispatch_indices( drm_device_t *dev,
 896                                         drm_buf_t *buf,
 897                                         int start, int end,
 898                                         int count )
 899 {
 900         drm_radeon_private_t *dev_priv = dev->dev_private;
 901         drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
 902         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 903         int format = sarea_priv->vc_format;
 904         int offset = dev_priv->agp_buffers_offset;
 905         int prim = buf_priv->prim;
 906         u32 *data;
 907         int dwords;
 908         int i = 0;
 909         RING_LOCALS;
 910         DRM_DEBUG( "indices: s=%d e=%d c=%d\n", start, end, count );
 911
 912         radeon_update_ring_snapshot( dev_priv );
 913
 914         if ( 0 )
 915                 radeon_print_dirty( "dispatch_indices", sarea_priv->dirty );
 916
 917         if ( start != end ) {
 918                 buf_priv->dispatched = 1;
 919
 920                 if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
 921                         radeon_emit_state( dev_priv );
 922                 }
 923
 924                 dwords = (end - start + 3) / sizeof(u32);
 925
 926                 data = (u32 *)((char *)dev_priv->buffers->handle
 927                                + buf->offset + start);
 928
 929                 data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 );
 930
 931                 data[1] = offset;
 932                 data[2] = RADEON_MAX_VB_VERTS;
 933                 data[3] = format;
 934                 data[4] = (prim | RADEON_PRIM_WALK_IND |
 935                            RADEON_COLOR_ORDER_RGBA |
 936                            RADEON_VTX_FMT_RADEON_MODE |
 937                            (count << RADEON_NUM_VERTICES_SHIFT) );
 938
 939                 if ( count & 0x1 ) {
 940                         data[dwords-1] &= 0x0000ffff;
 941                 }
 942
 943                 do {
 944                         /* Emit the next set of up to three cliprects */
 945                         if ( i < sarea_priv->nbox ) {
 946                                 radeon_emit_clip_rect( dev_priv,
 947                                                        &sarea_priv->boxes[i] );
 948                         }
 949
 950                         radeon_cp_dispatch_indirect( dev, buf, start, end );
 951
 952                         i++;
 953                 } while ( i < sarea_priv->nbox );
 954         }
 955
 956         if ( buf_priv->discard ) {
 957                 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
 958
 959                 /* Emit the vertex buffer age */
 960                 BEGIN_RING( 2 );
 961                 RADEON_DISPATCH_AGE( buf_priv->age );
 962                 ADVANCE_RING();
 963
 964                 buf->pending = 1;
 965                 /* FIXME: Check dispatched field */
 966                 buf_priv->dispatched = 0;
 967         }
 968
 969         dev_priv->sarea_priv->last_dispatch++;
 970
 971         sarea_priv->dirty &= ~RADEON_UPLOAD_CLIPRECTS;
 972         sarea_priv->nbox = 0;
 973 }
 974
 975 static int radeon_cp_dispatch_blit( drm_device_t *dev,
 976                                     drm_radeon_blit_t *blit )
 977 {
 978         drm_radeon_private_t *dev_priv = dev->dev_private;
 979         drm_device_dma_t *dma = dev->dma;
 980         drm_buf_t *buf;
 981         drm_radeon_buf_priv_t *buf_priv;
 982         u32 format;
 983         u32 *data;
 984         int dword_shift, dwords;
 985         RING_LOCALS;
 986         DRM_DEBUG( "blit: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
 987                    blit->offset >> 10, blit->pitch, blit->format,
 988                    blit->x, blit->y, blit->width, blit->height );
 989
 990         radeon_update_ring_snapshot( dev_priv );
 991
 992         /* The compiler won't optimize away a division by a variable,
 993          * even if the only legal values are powers of two.  Thus, we'll
 994          * use a shift instead.
 995          */
 996         switch ( blit->format ) {
 997         case RADEON_TXF_32BPP_ARGB8888:
 998         case RADEON_TXF_32BPP_RGBA8888:
 999                 format = RADEON_COLOR_FORMAT_ARGB8888;
1000                 dword_shift = 0;
1001                 break;
1002         case RADEON_TXF_16BPP_AI88:
1003         case RADEON_TXF_16BPP_ARGB1555:
1004         case RADEON_TXF_16BPP_RGB565:
1005         case RADEON_TXF_16BPP_ARGB4444:
1006                 format = RADEON_COLOR_FORMAT_RGB565;
1007                 dword_shift = 1;
1008                 break;
1009         case RADEON_TXF_8BPP_I:
1010         case RADEON_TXF_8BPP_RGB332:
1011                 format = RADEON_COLOR_FORMAT_CI8;
1012                 dword_shift = 2;
1013                 break;
1014         default:
1015                 DRM_ERROR( "invalid blit format %d\n", blit->format );
1016                 return -EINVAL;
1017         }
1018
1019         /* Flush the pixel cache.  This ensures no pixel data gets mixed
1020          * up with the texture data from the host data blit, otherwise
1021          * part of the texture image may be corrupted.
1022          */
1023         BEGIN_RING( 4 );
1024
1025         RADEON_FLUSH_CACHE();
1026         RADEON_WAIT_UNTIL_IDLE();
1027
1028         ADVANCE_RING();
1029
1030         /* Dispatch the indirect buffer.
1031          */
1032         buf = dma->buflist[blit->idx];
1033         buf_priv = buf->dev_private;
1034
1035         if ( buf->pid != current->pid ) {
1036                 DRM_ERROR( "process %d using buffer owned by %d\n",
1037                            current->pid, buf->pid );
1038                 return -EINVAL;
1039         }
1040         if ( buf->pending ) {
1041                 DRM_ERROR( "sending pending buffer %d\n", blit->idx );
1042                 return -EINVAL;
1043         }
1044
1045         buf_priv->discard = 1;
1046
1047         dwords = (blit->width * blit->height) >> dword_shift;
1048         if ( !dwords ) dwords = 1;
1049
1050         data = (u32 *)((char *)dev_priv->buffers->handle + buf->offset);
1051
1052         data[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 );
1053         data[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1054                    RADEON_GMC_BRUSH_NONE |
1055                    (format << 8) |
1056                    RADEON_GMC_SRC_DATATYPE_COLOR |
1057                    RADEON_ROP3_S |
1058                    RADEON_DP_SRC_SOURCE_HOST_DATA |
1059                    RADEON_GMC_CLR_CMP_CNTL_DIS |
1060                    RADEON_GMC_WR_MSK_DIS);
1061
1062         data[2] = (blit->pitch << 22) | (blit->offset >> 10);
1063         data[3] = 0xffffffff;
1064         data[4] = 0xffffffff;
1065         data[5] = (blit->y << 16) | blit->x;
1066         data[6] = (blit->height << 16) | blit->width;
1067         data[7] = dwords;
1068
1069         buf->used = (dwords + 8) * sizeof(u32);
1070
1071         radeon_cp_dispatch_indirect( dev, buf, 0, buf->used );
1072
1073         /* Flush the pixel cache after the blit completes.  This ensures
1074          * the texture data is written out to memory before rendering
1075          * continues.
1076          */
1077         BEGIN_RING( 4 );
1078
1079         RADEON_FLUSH_CACHE();
1080         RADEON_WAIT_UNTIL_2D_IDLE();
1081
1082         ADVANCE_RING();
1083
1084         return 0;
1085 }
1086
1087 static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple )
1088 {
1089         drm_radeon_private_t *dev_priv = dev->dev_private;
1090         int i;
1091         RING_LOCALS;
1092         DRM_DEBUG( "%s\n", __FUNCTION__ );
1093
1094         radeon_update_ring_snapshot( dev_priv );
1095
1096         BEGIN_RING( 35 );
1097
1098         OUT_RING( CP_PACKET0( RADEON_RE_STIPPLE_ADDR, 0 ) );
1099         OUT_RING( 0x00000000 );
1100
1101         OUT_RING( CP_PACKET0_TABLE( RADEON_RE_STIPPLE_DATA, 31 ) );
1102         for ( i = 0 ; i < 32 ; i++ ) {
1103                 OUT_RING( stipple[i] );
1104         }
1105
1106         ADVANCE_RING();
1107 }
1108
1109
1110 /* ================================================================
1111  * IOCTL functions
1112  */
1113
1114 int radeon_cp_clear( struct inode *inode, struct file *filp,
1115                      unsigned int cmd, unsigned long arg )
1116 {
1117         drm_file_t *priv = filp->private_data;
1118         drm_device_t *dev = priv->dev;
1119         drm_radeon_private_t *dev_priv = dev->dev_private;
1120         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1121         drm_radeon_clear_t clear;
1122         drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
1123         DRM_DEBUG( "%s\n", __FUNCTION__ );
1124
1125         if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
1126              dev->lock.pid != current->pid ) {
1127                 DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
1128                 return -EINVAL;
1129         }
1130
1131         if ( copy_from_user( &clear, (drm_radeon_clear_t *)arg,
1132                              sizeof(clear) ) )
1133                 return -EFAULT;
1134
1135
1136         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1137
1138         if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
1139                 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
1140
1141         if ( copy_from_user( &depth_boxes, clear.depth_boxes,
1142                              sarea_priv->nbox * sizeof(depth_boxes[0]) ) )
1143                 return -EFAULT;
1144
1145         radeon_cp_dispatch_clear( dev, &clear, depth_boxes );
1146
1147         return 0;
1148 }
1149
1150 int radeon_cp_swap( struct inode *inode, struct file *filp,
1151                     unsigned int cmd, unsigned long arg )
1152 {
1153         drm_file_t *priv = filp->private_data;
1154         drm_device_t *dev = priv->dev;
1155         drm_radeon_private_t *dev_priv = dev->dev_private;
1156         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1157         DRM_DEBUG( "%s\n", __FUNCTION__ );
1158
1159         if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
1160              dev->lock.pid != current->pid ) {
1161                 DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
1162                 return -EINVAL;
1163         }
1164
1165         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1166
1167         if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
1168                 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
1169
1170         if ( !dev_priv->page_flipping ) {
1171                 radeon_cp_dispatch_swap( dev );
1172                 dev_priv->sarea_priv->dirty |= (RADEON_UPLOAD_CONTEXT |
1173                                                 RADEON_UPLOAD_MASKS);
1174         } else {
1175                 radeon_cp_dispatch_flip( dev );
1176         }
1177
1178         return 0;
1179 }
1180
1181 int radeon_cp_vertex( struct inode *inode, struct file *filp,
1182                       unsigned int cmd, unsigned long arg )
1183 {
1184         drm_file_t *priv = filp->private_data;
1185         drm_device_t *dev = priv->dev;
1186         drm_radeon_private_t *dev_priv = dev->dev_private;
1187         drm_device_dma_t *dma = dev->dma;
1188         drm_buf_t *buf;
1189         drm_radeon_buf_priv_t *buf_priv;
1190         drm_radeon_vertex_t vertex;
1191
1192         if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
1193              dev->lock.pid != current->pid ) {
1194                 DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
1195                 return -EINVAL;
1196         }
1197         if ( !dev_priv || dev_priv->is_pci ) {
1198                 DRM_ERROR( "%s called with a PCI card\n", __FUNCTION__ );
1199                 return -EINVAL;
1200         }
1201
1202         if ( copy_from_user( &vertex, (drm_radeon_vertex_t *)arg,
1203                              sizeof(vertex) ) )
1204                 return -EFAULT;
1205
1206         DRM_DEBUG( "%s: pid=%d index=%d count=%d discard=%d\n",
1207                    __FUNCTION__, current->pid,
1208                    vertex.idx, vertex.count, vertex.discard );
1209
1210         if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
1211                 DRM_ERROR( "buffer index %d (of %d max)\n",
1212                            vertex.idx, dma->buf_count - 1 );
1213                 return -EINVAL;
1214         }
1215         if ( vertex.prim < 0 ||
1216              vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
1217                 DRM_ERROR( "buffer prim %d\n", vertex.prim );
1218                 return -EINVAL;
1219         }
1220
1221         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1222         VB_AGE_TEST_WITH_RETURN( dev_priv );
1223
1224         buf = dma->buflist[vertex.idx];
1225         buf_priv = buf->dev_private;
1226
1227         if ( buf->pid != current->pid ) {
1228                 DRM_ERROR( "process %d using buffer owned by %d\n",
1229                            current->pid, buf->pid );
1230                 return -EINVAL;
1231         }
1232         if ( buf->pending ) {
1233                 DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
1234                 return -EINVAL;
1235         }
1236
1237         buf->used = vertex.count;
1238         buf_priv->prim = vertex.prim;
1239         buf_priv->discard = vertex.discard;
1240
1241         radeon_cp_dispatch_vertex( dev, buf );
1242
1243         return 0;
1244 }
1245
1246 int radeon_cp_indices( struct inode *inode, struct file *filp,
1247                        unsigned int cmd, unsigned long arg )
1248 {
1249         drm_file_t *priv = filp->private_data;
1250         drm_device_t *dev = priv->dev;
1251         drm_radeon_private_t *dev_priv = dev->dev_private;
1252         drm_device_dma_t *dma = dev->dma;
1253         drm_buf_t *buf;
1254         drm_radeon_buf_priv_t *buf_priv;
1255         drm_radeon_indices_t elts;
1256         int count;
1257
1258         if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
1259              dev->lock.pid != current->pid ) {
1260                 DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
1261                 return -EINVAL;
1262         }
1263         if ( !dev_priv || dev_priv->is_pci ) {
1264                 DRM_ERROR( "%s called with a PCI card\n", __FUNCTION__ );
1265                 return -EINVAL;
1266         }
1267
1268         if ( copy_from_user( &elts, (drm_radeon_indices_t *)arg,
1269                              sizeof(elts) ) )
1270                 return -EFAULT;
1271
1272         DRM_DEBUG( "%s: pid=%d index=%d start=%d end=%d discard=%d\n",
1273                    __FUNCTION__, current->pid,
1274                    elts.idx, elts.start, elts.end, elts.discard );
1275
1276         if ( elts.idx < 0 || elts.idx >= dma->buf_count ) {
1277                 DRM_ERROR( "buffer index %d (of %d max)\n",
1278                            elts.idx, dma->buf_count - 1 );
1279                 return -EINVAL;
1280         }
1281         if ( elts.prim < 0 ||
1282              elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
1283                 DRM_ERROR( "buffer prim %d\n", elts.prim );
1284                 return -EINVAL;
1285         }
1286
1287         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1288         VB_AGE_TEST_WITH_RETURN( dev_priv );
1289
1290         buf = dma->buflist[elts.idx];
1291         buf_priv = buf->dev_private;
1292
1293         if ( buf->pid != current->pid ) {
1294                 DRM_ERROR( "process %d using buffer owned by %d\n",
1295                            current->pid, buf->pid );
1296                 return -EINVAL;
1297         }
1298         if ( buf->pending ) {
1299                 DRM_ERROR( "sending pending buffer %d\n", elts.idx );
1300                 return -EINVAL;
1301         }
1302
1303         count = (elts.end - elts.start) / sizeof(u16);
1304         elts.start -= RADEON_INDEX_PRIM_OFFSET;
1305
1306         if ( elts.start & 0x7 ) {
1307                 DRM_ERROR( "misaligned buffer 0x%x\n", elts.start );
1308                 return -EINVAL;
1309         }
1310         if ( elts.start < buf->used ) {
1311                 DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used );
1312                 return -EINVAL;
1313         }
1314
1315         buf->used = elts.end;
1316         buf_priv->prim = elts.prim;
1317         buf_priv->discard = elts.discard;
1318
1319         radeon_cp_dispatch_indices( dev, buf, elts.start, elts.end, count );
1320
1321         return 0;
1322 }
1323
1324 int radeon_cp_blit( struct inode *inode, struct file *filp,
1325                     unsigned int cmd, unsigned long arg )
1326 {
1327         drm_file_t *priv = filp->private_data;
1328         drm_device_t *dev = priv->dev;
1329         drm_radeon_private_t *dev_priv = dev->dev_private;
1330         drm_device_dma_t *dma = dev->dma;
1331         drm_radeon_blit_t blit;
1332
1333         if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
1334              dev->lock.pid != current->pid ) {
1335                 DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
1336                 return -EINVAL;
1337         }
1338
1339         if ( copy_from_user( &blit, (drm_radeon_blit_t *)arg,
1340                              sizeof(blit) ) )
1341                 return -EFAULT;
1342
1343         DRM_DEBUG( "%s: pid=%d index=%d\n",
1344                    __FUNCTION__, current->pid, blit.idx );
1345
1346         if ( blit.idx < 0 || blit.idx > dma->buf_count ) {
1347                 DRM_ERROR( "sending %d buffers (of %d max)\n",
1348                            blit.idx, dma->buf_count );
1349                 return -EINVAL;
1350         }
1351
1352         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1353         VB_AGE_TEST_WITH_RETURN( dev_priv );
1354
1355         return radeon_cp_dispatch_blit( dev, &blit );
1356 }
1357
1358 int radeon_cp_stipple( struct inode *inode, struct file *filp,
1359                        unsigned int cmd, unsigned long arg )
1360 {
1361         drm_file_t *priv = filp->private_data;
1362         drm_device_t *dev = priv->dev;
1363         drm_radeon_private_t *dev_priv = dev->dev_private;
1364         drm_radeon_stipple_t stipple;
1365         u32 mask[32];
1366
1367         if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
1368              dev->lock.pid != current->pid ) {
1369                 DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
1370                 return -EINVAL;
1371         }
1372
1373         if ( copy_from_user( &stipple, (drm_radeon_stipple_t *)arg,
1374                              sizeof(stipple) ) )
1375                 return -EFAULT;
1376
1377         if ( copy_from_user( &mask, stipple.mask,
1378                              32 * sizeof(u32) ) )
1379                 return -EFAULT;
1380
1381         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1382
1383         radeon_cp_dispatch_stipple( dev, mask );
1384
1385         return 0;
1386 }
1387
1388 int radeon_cp_indirect( struct inode *inode, struct file *filp,
1389                         unsigned int cmd, unsigned long arg )
1390 {
1391         drm_file_t *priv = filp->private_data;
1392         drm_device_t *dev = priv->dev;
1393         drm_radeon_private_t *dev_priv = dev->dev_private;
1394         drm_device_dma_t *dma = dev->dma;
1395         drm_buf_t *buf;
1396         drm_radeon_buf_priv_t *buf_priv;
1397         drm_radeon_indirect_t indirect;
1398         RING_LOCALS;
1399
1400         if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
1401              dev->lock.pid != current->pid ) {
1402                 DRM_ERROR( "%s called without lock held\n", __FUNCTION__ );
1403                 return -EINVAL;
1404         }
1405         if ( !dev_priv || dev_priv->is_pci ) {
1406                 DRM_ERROR( "%s called with a PCI card\n", __FUNCTION__ );
1407                 return -EINVAL;
1408         }
1409
1410         if ( copy_from_user( &indirect, (drm_radeon_indirect_t *)arg,
1411                              sizeof(indirect) ) )
1412                 return -EFAULT;
1413
1414         DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n",
1415                    indirect.idx, indirect.start,
1416                    indirect.end, indirect.discard );
1417
1418         if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) {
1419                 DRM_ERROR( "buffer index %d (of %d max)\n",
1420                            indirect.idx, dma->buf_count - 1 );
1421                 return -EINVAL;
1422         }
1423
1424         buf = dma->buflist[indirect.idx];
1425         buf_priv = buf->dev_private;
1426
1427         if ( buf->pid != current->pid ) {
1428                 DRM_ERROR( "process %d using buffer owned by %d\n",
1429                            current->pid, buf->pid );
1430                 return -EINVAL;
1431         }
1432         if ( buf->pending ) {
1433                 DRM_ERROR( "sending pending buffer %d\n", indirect.idx );
1434                 return -EINVAL;
1435         }
1436
1437         if ( indirect.start < buf->used ) {
1438                 DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n",
1439                            indirect.start, buf->used );
1440                 return -EINVAL;
1441         }
1442
1443         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1444         VB_AGE_TEST_WITH_RETURN( dev_priv );
1445
1446         buf->used = indirect.end;
1447         buf_priv->discard = indirect.discard;
1448
1449         /* Wait for the 3D stream to idle before the indirect buffer
1450          * containing 2D acceleration commands is processed.
1451          */
1452         BEGIN_RING( 2 );
1453
1454         RADEON_WAIT_UNTIL_3D_IDLE();
1455
1456         ADVANCE_RING();
1457
1458         /* Dispatch the indirect buffer full of commands from the
1459          * X server.  This is insecure and is thus only available to
1460          * privileged clients.
1461          */
1462         radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end );
1463
1464         return 0;
1465 }