linux/mga_dma.c

   1 /* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*-
   2  * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
   3  *
   4  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
   5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Rickard E. (Rik) Faith <faith@valinux.com>
  29  *    Jeff Hartmann <jhartmann@valinux.com>
  30  *    Keith Whitwell <keithw@valinux.com>
  31  *
  32  * Rewritten by:
  33  *    Gareth Hughes <gareth@valinux.com>
  34  */
  35
  36 #define __NO_VERSION__
  37 #include "mga.h"
  38 #include "drmP.h"
  39 #include "mga_drv.h"
  40
  41 #include <linux/interrupt.h>    /* For task queue support */
  42 #include <linux/delay.h>
  43
  44 #define MGA_DEFAULT_USEC_TIMEOUT        10000
  45
  46
  47 /* ================================================================
  48  * Engine control
  49  */
  50
  51 int mga_do_wait_for_idle( drm_mga_private_t *dev_priv )
  52 {
  53         u32 status = 0;
  54         int i;
  55         DRM_DEBUG( "%s\n", __FUNCTION__ );
  56
  57         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
  58                 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
  59                 if ( status == MGA_ENDPRDMASTS ) {
  60                         MGA_WRITE8( MGA_CRTC_INDEX, 0 );
  61                         return 0;
  62                 }
  63                 udelay( 1 );
  64         }
  65
  66         DRM_DEBUG( "failed! status=0x%08x\n", status );
  67         return -EBUSY;
  68 }
  69
  70 int mga_do_dma_idle( drm_mga_private_t *dev_priv )
  71 {
  72         u32 status = 0;
  73         int i;
  74         DRM_DEBUG( "%s\n", __FUNCTION__ );
  75
  76         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
  77                 status = MGA_READ( MGA_STATUS ) & MGA_DMA_IDLE_MASK;
  78                 if ( status == MGA_ENDPRDMASTS ) return 0;
  79                 udelay( 1 );
  80         }
  81
  82         DRM_DEBUG( "failed! status=0x%08x\n", status );
  83         return -EBUSY;
  84 }
  85
  86 int mga_do_dma_reset( drm_mga_private_t *dev_priv )
  87 {
  88         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
  89         drm_mga_primary_buffer_t *primary = &dev_priv->prim;
  90
  91         DRM_DEBUG( "%s\n", __FUNCTION__ );
  92
  93         /* The primary DMA stream should look like new right about now.
  94          */
  95         primary->tail = 0;
  96         primary->space = primary->size;
  97         primary->last_flush = 0;
  98
  99         sarea_priv->last_wrap = 0;
 100
 101         /* FIXME: Reset counters, buffer ages etc...
 102          */
 103
 104         /* FIXME: What else do we need to reinitialize?  WARP stuff?
 105          */
 106
 107         return 0;
 108 }
 109
 110 int mga_do_engine_reset( drm_mga_private_t *dev_priv )
 111 {
 112         DRM_DEBUG( "%s\n", __FUNCTION__ );
 113
 114         /* Okay, so we've completely screwed up and locked the engine.
 115          * How about we clean up after ourselves?
 116          */
 117         MGA_WRITE( MGA_RST, MGA_SOFTRESET );
 118         udelay( 15 );                           /* Wait at least 10 usecs */
 119         MGA_WRITE( MGA_RST, 0 );
 120
 121         /* Initialize the registers that get clobbered by the soft
 122          * reset.  Many of the core register values survive a reset,
 123          * but the drawing registers are basically all gone.
 124          *
 125          * 3D clients should probably die after calling this.  The X
 126          * server should reset the engine state to known values.
 127          */
 128 #if 0
 129         MGA_WRITE( MGA_PRIMPTR,
 130                    virt_to_bus((void *)dev_priv->prim.status_page) |
 131                    MGA_PRIMPTREN0 |
 132                    MGA_PRIMPTREN1 );
 133 #endif
 134
 135         MGA_WRITE( MGA_ICLEAR, MGA_SOFTRAPICLR );
 136         MGA_WRITE( MGA_IEN,    MGA_SOFTRAPIEN );
 137
 138         /* The primary DMA stream should look like new right about now.
 139          */
 140         mga_do_dma_reset( dev_priv );
 141
 142         /* This bad boy will never fail.
 143          */
 144         return 0;
 145 }
 146
 147
 148 /* ================================================================
 149  * Primary DMA stream
 150  */
 151
 152 void mga_do_dma_flush( drm_mga_private_t *dev_priv )
 153 {
 154         drm_mga_primary_buffer_t *primary = &dev_priv->prim;
 155         u32 head, tail;
 156         DMA_LOCALS;
 157         DRM_DEBUG( "%s:\n", __FUNCTION__ );
 158
 159         if ( primary->tail == primary->last_flush ) {
 160                 DRM_DEBUG( "   bailing out...\n" );
 161                 return;
 162         }
 163
 164         tail = primary->tail + dev_priv->primary->offset;
 165
 166         /* We need to pad the stream between flushes, as the card
 167          * actually (partially?) reads the first of these commands.
 168          * See page 4-16 in the G400 manual, middle of the page or so.
 169          */
 170         BEGIN_DMA( 1 );
 171
 172         DMA_BLOCK( MGA_DMAPAD,  0x00000000,
 173                    MGA_DMAPAD,  0x00000000,
 174                    MGA_DMAPAD,  0x00000000,
 175                    MGA_DMAPAD,  0x00000000 );
 176
 177         ADVANCE_DMA();
 178
 179         primary->last_flush = primary->tail;
 180
 181         head = MGA_READ( MGA_PRIMADDRESS );
 182
 183         if ( head <= tail ) {
 184                 primary->space = primary->size - primary->tail;
 185         } else {
 186                 primary->space = head - tail;
 187         }
 188
 189         DRM_DEBUG( "   head = 0x%06lx\n", head - dev_priv->primary->offset );
 190         DRM_DEBUG( "   tail = 0x%06lx\n", tail - dev_priv->primary->offset );
 191         DRM_DEBUG( "  space = 0x%06x\n", primary->space );
 192
 193         mga_flush_write_combine();
 194         MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER );
 195
 196         DRM_DEBUG( "%s: done.\n", __FUNCTION__ );
 197 }
 198
 199 void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv )
 200 {
 201         drm_mga_primary_buffer_t *primary = &dev_priv->prim;
 202         u32 head, tail;
 203         DMA_LOCALS;
 204         DRM_DEBUG( "%s:\n", __FUNCTION__ );
 205
 206         BEGIN_DMA_WRAP();
 207
 208         DMA_BLOCK( MGA_DMAPAD,  0x00000000,
 209                    MGA_DMAPAD,  0x00000000,
 210                    MGA_DMAPAD,  0x00000000,
 211                    MGA_DWGSYNC, 0x12345678 );
 212
 213         ADVANCE_DMA();
 214
 215         tail = primary->tail + dev_priv->primary->offset;
 216
 217         primary->tail = 0;
 218         primary->last_flush = 0;
 219         primary->last_wrap++;
 220
 221         head = MGA_READ( MGA_PRIMADDRESS );
 222
 223         if ( head == dev_priv->primary->offset ) {
 224                 primary->space = primary->size;
 225         } else {
 226                 primary->space = head - dev_priv->primary->offset;
 227         }
 228
 229         DRM_DEBUG( "   head = 0x%06lx\n",
 230                   head - dev_priv->primary->offset );
 231         DRM_DEBUG( "   tail = 0x%06x\n", primary->tail );
 232         DRM_DEBUG( "   wrap = %d\n", primary->last_wrap );
 233         DRM_DEBUG( "  space = 0x%06x\n", primary->space );
 234
 235         mga_flush_write_combine();
 236         MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER );
 237
 238         DRM_DEBUG( "%s: done.\n", __FUNCTION__ );
 239 }
 240
 241 void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv )
 242 {
 243         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 244         u32 head = dev_priv->primary->offset;
 245         DRM_DEBUG( "%s:\n", __FUNCTION__ );
 246
 247         sarea_priv->last_wrap++;
 248         DRM_DEBUG( "   wrap = %d\n", sarea_priv->last_wrap );
 249
 250         mga_flush_write_combine();
 251         MGA_WRITE( MGA_PRIMADDRESS, head | MGA_DMA_GENERAL );
 252
 253         DRM_DEBUG( "%s: done.\n", __FUNCTION__ );
 254 }
 255
 256
 257 /* ================================================================
 258  * Freelist management
 259  */
 260
 261 #define MGA_BUFFER_USED         ~0
 262 #define MGA_BUFFER_FREE         0
 263
 264 static void mga_freelist_print( drm_device_t *dev )
 265 {
 266         drm_mga_private_t *dev_priv = dev->dev_private;
 267         drm_mga_freelist_t *entry;
 268
 269         DRM_INFO( "\n" );
 270         DRM_INFO( "current dispatch: last=0x%x done=0x%x\n",
 271                   dev_priv->sarea_priv->last_dispatch,
 272                   (unsigned int)(MGA_READ( MGA_PRIMADDRESS ) -
 273                                  dev_priv->primary->offset) );
 274         DRM_INFO( "current freelist:\n" );
 275
 276         for ( entry = dev_priv->head->next ; entry ; entry = entry->next ) {
 277                 DRM_INFO( "   %p   idx=%2d  age=0x%x 0x%06lx\n",
 278                           entry, entry->buf->idx, entry->age.head,
 279                           entry->age.head - dev_priv->primary->offset );
 280         }
 281         DRM_INFO( "\n" );
 282 }
 283
 284 static int mga_freelist_init( drm_device_t *dev )
 285 {
 286         drm_device_dma_t *dma = dev->dma;
 287         drm_mga_private_t *dev_priv = dev->dev_private;
 288         drm_buf_t *buf;
 289         drm_mga_buf_priv_t *buf_priv;
 290         drm_mga_freelist_t *entry;
 291         int i;
 292         DRM_DEBUG( "%s: count=%d\n",
 293                    __FUNCTION__, dma->buf_count );
 294
 295         dev_priv->head = DRM(alloc)( sizeof(drm_mga_freelist_t),
 296                                      DRM_MEM_DRIVER );
 297         if ( dev_priv->head == NULL )
 298                 return -ENOMEM;
 299
 300         memset( dev_priv->head, 0, sizeof(drm_mga_freelist_t) );
 301         SET_AGE( &dev_priv->head->age, MGA_BUFFER_USED, 0 );
 302
 303         for ( i = 0 ; i < dma->buf_count ; i++ ) {
 304                 buf = dma->buflist[i];
 305                 buf_priv = buf->dev_private;
 306
 307                 entry = DRM(alloc)( sizeof(drm_mga_freelist_t),
 308                                     DRM_MEM_DRIVER );
 309                 if ( entry == NULL )
 310                         return -ENOMEM;
 311
 312                 memset( entry, 0, sizeof(drm_mga_freelist_t) );
 313
 314                 entry->next = dev_priv->head->next;
 315                 entry->prev = dev_priv->head;
 316                 SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 );
 317                 entry->buf = buf;
 318
 319                 if ( dev_priv->head->next != NULL )
 320                         dev_priv->head->next->prev = entry;
 321                 if ( entry->next == NULL )
 322                         dev_priv->tail = entry;
 323
 324                 buf_priv->list_entry = entry;
 325                 buf_priv->discard = 0;
 326                 buf_priv->dispatched = 0;
 327
 328                 dev_priv->head->next = entry;
 329         }
 330
 331         return 0;
 332 }
 333
 334 static void mga_freelist_cleanup( drm_device_t *dev )
 335 {
 336         drm_mga_private_t *dev_priv = dev->dev_private;
 337         drm_mga_freelist_t *entry;
 338         drm_mga_freelist_t *next;
 339         DRM_DEBUG( "%s\n", __FUNCTION__ );
 340
 341         entry = dev_priv->head;
 342         while ( entry ) {
 343                 next = entry->next;
 344                 DRM(free)( entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER );
 345                 entry = next;
 346         }
 347
 348         dev_priv->head = dev_priv->tail = NULL;
 349 }
 350
 351 static void mga_freelist_reset( drm_device_t *dev )
 352 {
 353         drm_device_dma_t *dma = dev->dma;
 354         drm_buf_t *buf;
 355         drm_mga_buf_priv_t *buf_priv;
 356         int i;
 357
 358         for ( i = 0 ; i < dma->buf_count ; i++ ) {
 359                 buf = dma->buflist[i];
 360                 buf_priv = buf->dev_private;
 361                 SET_AGE( &buf_priv->list_entry->age,
 362                          MGA_BUFFER_FREE, 0 );
 363         }
 364 }
 365
 366 static drm_buf_t *mga_freelist_get( drm_device_t *dev )
 367 {
 368         drm_mga_private_t *dev_priv = dev->dev_private;
 369         drm_mga_freelist_t *next;
 370         drm_mga_freelist_t *prev;
 371         drm_mga_freelist_t *tail = dev_priv->tail;
 372         u32 head, wrap;
 373         DRM_DEBUG( "%s:\n", __FUNCTION__ );
 374
 375         head = MGA_READ( MGA_PRIMADDRESS );
 376         wrap = dev_priv->sarea_priv->last_wrap;
 377
 378         DRM_DEBUG( "   tail=0x%06lx %d\n",
 379                    tail->age.head ?
 380                    tail->age.head - dev_priv->primary->offset : 0,
 381                    tail->age.wrap );
 382         DRM_DEBUG( "   head=0x%06lx %d\n",
 383                    head - dev_priv->primary->offset, wrap );
 384
 385         if ( TEST_AGE( &tail->age, head, wrap ) ) {
 386                 prev = dev_priv->tail->prev;
 387                 next = dev_priv->tail;
 388                 prev->next = NULL;
 389                 next->prev = next->next = NULL;
 390                 dev_priv->tail = prev;
 391                 SET_AGE( &next->age, MGA_BUFFER_USED, 0 );
 392                 return next->buf;
 393         }
 394
 395         DRM_DEBUG( "returning NULL!\n" );
 396         return NULL;
 397 }
 398
 399 int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf )
 400 {
 401         drm_mga_private_t *dev_priv = dev->dev_private;
 402         drm_mga_buf_priv_t *buf_priv = buf->dev_private;
 403         drm_mga_freelist_t *head, *entry, *prev;
 404
 405         DRM_DEBUG( "%s: age=0x%06lx wrap=%d\n",
 406                    __FUNCTION__,
 407                    buf_priv->list_entry->age.head -
 408                    dev_priv->primary->offset,
 409                    buf_priv->list_entry->age.wrap );
 410
 411         entry = buf_priv->list_entry;
 412         head = dev_priv->head;
 413
 414         if ( buf_priv->list_entry->age.head == MGA_BUFFER_USED ) {
 415                 SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 );
 416                 prev = dev_priv->tail;
 417                 prev->next = entry;
 418                 entry->prev = prev;
 419                 entry->next = NULL;
 420         } else {
 421                 prev = head->next;
 422                 head->next = entry;
 423                 prev->prev = entry;
 424                 entry->prev = head;
 425                 entry->next = prev;
 426         }
 427
 428         return 0;
 429 }
 430
 431
 432 /* ================================================================
 433  * DMA initialization, cleanup
 434  */
 435
 436 static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
 437 {
 438         drm_mga_private_t *dev_priv;
 439         struct list_head *list;
 440         int ret;
 441         DRM_DEBUG( "%s\n", __FUNCTION__ );
 442
 443         dev_priv = DRM(alloc)( sizeof(drm_mga_private_t), DRM_MEM_DRIVER );
 444         if ( !dev_priv )
 445                 return -ENOMEM;
 446         dev->dev_private = (void *)dev_priv;
 447
 448         memset( dev_priv, 0, sizeof(drm_mga_private_t) );
 449
 450         dev_priv->chipset = init->chipset;
 451
 452         dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
 453
 454         if ( init->sgram ) {
 455                 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK;
 456         } else {
 457                 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
 458         }
 459         dev_priv->maccess       = init->maccess;
 460
 461         dev_priv->fb_cpp        = init->fb_cpp;
 462         dev_priv->front_offset  = init->front_offset;
 463         dev_priv->front_pitch   = init->front_pitch;
 464         dev_priv->back_offset   = init->back_offset;
 465         dev_priv->back_pitch    = init->back_pitch;
 466
 467         dev_priv->depth_cpp     = init->depth_cpp;
 468         dev_priv->depth_offset  = init->depth_offset;
 469         dev_priv->depth_pitch   = init->depth_pitch;
 470
 471         list_for_each(list, &dev->maplist->head) {
 472                 drm_map_list_t *r_list = (drm_map_list_t *)list;
 473                 if( r_list->map &&
 474                     r_list->map->type == _DRM_SHM &&
 475                     r_list->map->flags & _DRM_CONTAINS_LOCK ) {
 476                         dev_priv->sarea = r_list->map;
 477                         break;
 478                 }
 479         }
 480
 481         DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
 482         DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
 483         DRM_FIND_MAP( dev_priv->status, init->status_offset );
 484
 485         DRM_FIND_MAP( dev_priv->warp, init->warp_offset );
 486         DRM_FIND_MAP( dev_priv->primary, init->primary_offset );
 487         DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
 488
 489         dev_priv->sarea_priv =
 490                 (drm_mga_sarea_t *)((u8 *)dev_priv->sarea->handle +
 491                                     init->sarea_priv_offset);
 492
 493         DRM_IOREMAP( dev_priv->warp );
 494         DRM_IOREMAP( dev_priv->primary );
 495         DRM_IOREMAP( dev_priv->buffers );
 496
 497         ret = mga_warp_install_microcode( dev );
 498         if ( ret < 0 ) {
 499                 DRM_ERROR( "failed to install WARP ucode!\n" );
 500                 mga_do_cleanup_dma( dev );
 501                 return ret;
 502         }
 503
 504         ret = mga_warp_init( dev );
 505         if ( ret < 0 ) {
 506                 DRM_ERROR( "failed to init WARP engine!\n" );
 507                 mga_do_cleanup_dma( dev );
 508                 return ret;
 509         }
 510
 511         dev_priv->prim.status = (u32 *)dev_priv->status->handle;
 512
 513         mga_do_wait_for_idle( dev_priv );
 514
 515         /* Init the primary DMA registers.
 516          */
 517         MGA_WRITE( MGA_PRIMADDRESS,
 518                    dev_priv->primary->offset | MGA_DMA_GENERAL );
 519
 520         MGA_WRITE( MGA_PRIMPTR,
 521                    virt_to_bus((void *)dev_priv->prim.status) |
 522                    MGA_PRIMPTREN0 |     /* Soft trap, SECEND, SETUPEND */
 523                    MGA_PRIMPTREN1 );    /* DWGSYNC */
 524
 525         dev_priv->prim.start = (u8 *)dev_priv->primary->handle;
 526         dev_priv->prim.end = ((u8 *)dev_priv->primary->handle
 527                               + dev_priv->primary->size);
 528         dev_priv->prim.size = dev_priv->primary->size;
 529
 530         dev_priv->prim.tail = 0;
 531         dev_priv->prim.space = dev_priv->prim.size;
 532
 533         dev_priv->prim.last_flush = 0;
 534         dev_priv->prim.last_wrap = 0;
 535
 536         dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE;
 537
 538         spin_lock_init( &dev_priv->prim.list_lock );
 539
 540         dev_priv->prim.status[0] = dev_priv->primary->offset;
 541         dev_priv->prim.status[1] = 0;
 542
 543         dev_priv->sarea_priv->last_wrap = 0;
 544         dev_priv->sarea_priv->last_frame.head = 0;
 545         dev_priv->sarea_priv->last_frame.wrap = 0;
 546
 547         if ( mga_freelist_init( dev ) < 0 ) {
 548                 DRM_ERROR( "could not initialize freelist\n" );
 549                 mga_do_cleanup_dma( dev );
 550                 return -ENOMEM;
 551         }
 552
 553         return 0;
 554 }
 555
 556 int mga_do_cleanup_dma( drm_device_t *dev )
 557 {
 558         DRM_DEBUG( "%s\n", __FUNCTION__ );
 559
 560         if ( dev->dev_private ) {
 561                 drm_mga_private_t *dev_priv = dev->dev_private;
 562
 563                 DRM_IOREMAPFREE( dev_priv->warp );
 564                 DRM_IOREMAPFREE( dev_priv->primary );
 565                 DRM_IOREMAPFREE( dev_priv->buffers );
 566
 567                 if ( dev_priv->head != NULL ) {
 568                         mga_freelist_cleanup( dev );
 569                 }
 570
 571                 DRM(free)( dev->dev_private, sizeof(drm_mga_private_t),
 572                            DRM_MEM_DRIVER );
 573                 dev->dev_private = NULL;
 574         }
 575
 576         return 0;
 577 }
 578
 579 int mga_dma_init( struct inode *inode, struct file *filp,
 580                   unsigned int cmd, unsigned long arg )
 581 {
 582         drm_file_t *priv = filp->private_data;
 583         drm_device_t *dev = priv->dev;
 584         drm_mga_init_t init;
 585
 586         if ( copy_from_user( &init, (drm_mga_init_t *)arg, sizeof(init) ) )
 587                 return -EFAULT;
 588
 589         switch ( init.func ) {
 590         case MGA_INIT_DMA:
 591                 return mga_do_init_dma( dev, &init );
 592         case MGA_CLEANUP_DMA:
 593                 return mga_do_cleanup_dma( dev );
 594         }
 595
 596         return -EINVAL;
 597 }
 598
 599
 600 /* ================================================================
 601  * Primary DMA stream management
 602  */
 603
 604 int mga_dma_flush( struct inode *inode, struct file *filp,
 605                    unsigned int cmd, unsigned long arg )
 606 {
 607         drm_file_t *priv = filp->private_data;
 608         drm_device_t *dev = priv->dev;
 609         drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
 610         drm_lock_t lock;
 611
 612         LOCK_TEST_WITH_RETURN( dev );
 613
 614         if ( copy_from_user( &lock, (drm_lock_t *)arg, sizeof(lock) ) )
 615                 return -EFAULT;
 616
 617         DRM_DEBUG( "%s: %s%s%s\n",
 618                    __FUNCTION__,
 619                    (lock.flags & _DRM_LOCK_FLUSH) ?     "flush, " : "",
 620                    (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
 621                    (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "" );
 622
 623         WRAP_TEST_WITH_RETURN( dev_priv );
 624
 625 #if 0
 626         if ( lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL) ) {
 627                 mga_do_dma_flush( dev_priv );
 628         }
 629 #endif
 630         if ( lock.flags & _DRM_LOCK_QUIESCENT ) {
 631                 return mga_do_wait_for_idle( dev_priv );
 632         } else {
 633                 return 0;
 634         }
 635 }
 636
 637 int mga_dma_reset( struct inode *inode, struct file *filp,
 638                    unsigned int cmd, unsigned long arg )
 639 {
 640         drm_file_t *priv = filp->private_data;
 641         drm_device_t *dev = priv->dev;
 642         drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
 643
 644         LOCK_TEST_WITH_RETURN( dev );
 645
 646         return mga_do_dma_reset( dev_priv );
 647 }
 648
 649
 650 /* ================================================================
 651  * DMA buffer management
 652  */
 653
 654 static int mga_dma_get_buffers( drm_device_t *dev, drm_dma_t *d )
 655 {
 656         drm_buf_t *buf;
 657         int i;
 658
 659         for ( i = d->granted_count ; i < d->request_count ; i++ ) {
 660                 buf = mga_freelist_get( dev );
 661                 if ( !buf ) return -EAGAIN;
 662
 663                 buf->pid = current->pid;
 664
 665                 if ( copy_to_user( &d->request_indices[i],
 666                                    &buf->idx, sizeof(buf->idx) ) )
 667                         return -EFAULT;
 668                 if ( copy_to_user( &d->request_sizes[i],
 669                                    &buf->total, sizeof(buf->total) ) )
 670                         return -EFAULT;
 671
 672                 d->granted_count++;
 673         }
 674         return 0;
 675 }
 676
 677 int mga_dma_buffers( struct inode *inode, struct file *filp,
 678                      unsigned int cmd, unsigned long arg )
 679 {
 680         drm_file_t *priv = filp->private_data;
 681         drm_device_t *dev = priv->dev;
 682         drm_device_dma_t *dma = dev->dma;
 683         drm_dma_t d;
 684         int ret = 0;
 685
 686         LOCK_TEST_WITH_RETURN( dev );
 687
 688         if ( copy_from_user( &d, (drm_dma_t *)arg, sizeof(d) ) )
 689                 return -EFAULT;
 690
 691         /* Please don't send us buffers.
 692          */
 693         if ( d.send_count != 0 ) {
 694                 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
 695                            current->pid, d.send_count );
 696                 return -EINVAL;
 697         }
 698
 699         /* We'll send you buffers.
 700          */
 701         if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
 702                 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
 703                            current->pid, d.request_count, dma->buf_count );
 704                 return -EINVAL;
 705         }
 706
 707         d.granted_count = 0;
 708
 709         if ( d.request_count ) {
 710                 ret = mga_dma_get_buffers( dev, &d );
 711         }
 712
 713         if ( copy_to_user( (drm_dma_t *)arg, &d, sizeof(d) ) )
 714                 return -EFAULT;
 715
 716         return ret;
 717 }