1 /* drm.h -- Header for Direct Rendering Manager -*- linux-c -*-
2 * Created: Mon Jan 4 10:05:05 1999 by faith@precisioninsight.com
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 * Rickard E. (Rik) Faith <faith@valinux.com>
31 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic cmpxchg.
38 #include <asm/ioctl.h> /* For _IO* macros */
40 #define DRM_PROC_DEVICES "/proc/devices"
41 #define DRM_PROC_MISC "/proc/misc"
42 #define DRM_PROC_DRM "/proc/drm"
43 #define DRM_DEV_DRM "/dev/drm"
44 #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
49 #define DRM_NAME "drm" /* Name in kernel, /dev, and /proc */
50 #define DRM_MIN_ORDER 5 /* At least 2^5 bytes = 32 bytes */
51 #define DRM_MAX_ORDER 22 /* Up to 2^22 bytes = 4MB */
52 #define DRM_RAM_PERCENT 10 /* How much system ram can we lock? */
54 #define _DRM_LOCK_HELD 0x80000000 /* Hardware lock is held */
55 #define _DRM_LOCK_CONT 0x40000000 /* Hardware lock is contended */
56 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
57 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
58 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
60 typedef unsigned long drm_handle_t;
61 typedef unsigned int drm_context_t;
62 typedef unsigned int drm_drawable_t;
63 typedef unsigned int drm_magic_t;
65 /* Warning: If you change this structure, make sure you change
66 * XF86DRIClipRectRec in the server as well */
68 typedef struct drm_clip_rect {
75 /* Seperate include files for the i810/mga/r128 specific structures */
80 typedef struct drm_version {
81 int version_major; /* Major version */
82 int version_minor; /* Minor version */
83 int version_patchlevel;/* Patch level */
84 size_t name_len; /* Length of name buffer */
85 char *name; /* Name of driver */
86 size_t date_len; /* Length of date buffer */
87 char *date; /* User-space buffer to hold date */
88 size_t desc_len; /* Length of desc buffer */
89 char *desc; /* User-space buffer to hold desc */
92 typedef struct drm_unique {
93 size_t unique_len; /* Length of unique */
94 char *unique; /* Unique name for driver instantiation */
97 typedef struct drm_list {
98 int count; /* Length of user-space structures */
99 drm_version_t *version;
102 typedef struct drm_block {
106 typedef struct drm_control {
116 typedef enum drm_map_type {
117 _DRM_FRAME_BUFFER = 0, /* WC (no caching), no core dump */
118 _DRM_REGISTERS = 1, /* no caching, no core dump */
119 _DRM_SHM = 2, /* shared, cached */
120 _DRM_AGP = 3 /* AGP/GART */
123 typedef enum drm_map_flags {
124 _DRM_RESTRICTED = 0x01, /* Cannot be mapped to user-virtual */
125 _DRM_READ_ONLY = 0x02,
126 _DRM_LOCKED = 0x04, /* shared, cached, locked */
127 _DRM_KERNEL = 0x08, /* kernel requires access */
128 _DRM_WRITE_COMBINING = 0x10, /* use write-combining if available */
129 _DRM_CONTAINS_LOCK = 0x20 /* SHM page that contains lock */
132 typedef struct drm_map {
133 unsigned long offset; /* Requested physical address (0 for SAREA)*/
134 unsigned long size; /* Requested physical size (bytes) */
135 drm_map_type_t type; /* Type of memory to map */
136 drm_map_flags_t flags; /* Flags */
137 void *handle; /* User-space: "Handle" to pass to mmap */
138 /* Kernel-space: kernel-virtual address */
139 int mtrr; /* MTRR slot used */
143 typedef enum drm_lock_flags {
144 _DRM_LOCK_READY = 0x01, /* Wait until hardware is ready for DMA */
145 _DRM_LOCK_QUIESCENT = 0x02, /* Wait until hardware quiescent */
146 _DRM_LOCK_FLUSH = 0x04, /* Flush this context's DMA queue first */
147 _DRM_LOCK_FLUSH_ALL = 0x08, /* Flush all DMA queues first */
148 /* These *HALT* flags aren't supported yet
149 -- they will be used to support the
150 full-screen DGA-like mode. */
151 _DRM_HALT_ALL_QUEUES = 0x10, /* Halt all current and future queues */
152 _DRM_HALT_CUR_QUEUES = 0x20 /* Halt all current queues */
155 typedef struct drm_lock {
157 drm_lock_flags_t flags;
160 typedef enum drm_dma_flags { /* These values *MUST* match xf86drm.h */
161 /* Flags for DMA buffer dispatch */
162 _DRM_DMA_BLOCK = 0x01, /* Block until buffer dispatched.
163 Note, the buffer may not yet have
164 been processed by the hardware --
165 getting a hardware lock with the
166 hardware quiescent will ensure
167 that the buffer has been
169 _DRM_DMA_WHILE_LOCKED = 0x02, /* Dispatch while lock held */
170 _DRM_DMA_PRIORITY = 0x04, /* High priority dispatch */
172 /* Flags for DMA buffer request */
173 _DRM_DMA_WAIT = 0x10, /* Wait for free buffers */
174 _DRM_DMA_SMALLER_OK = 0x20, /* Smaller-than-requested buffers ok */
175 _DRM_DMA_LARGER_OK = 0x40 /* Larger-than-requested buffers ok */
178 typedef struct drm_buf_desc {
179 int count; /* Number of buffers of this size */
180 int size; /* Size in bytes */
181 int low_mark; /* Low water mark */
182 int high_mark; /* High water mark */
184 _DRM_PAGE_ALIGN = 0x01, /* Align on page boundaries for DMA */
185 _DRM_AGP_BUFFER = 0x02 /* Buffer is in agp space */
187 unsigned long agp_start; /* Start address of where the agp buffers
188 * are in the agp aperture */
191 typedef struct drm_buf_info {
192 int count; /* Entries in list */
193 drm_buf_desc_t *list;
196 typedef struct drm_buf_free {
201 typedef struct drm_buf_pub {
202 int idx; /* Index into master buflist */
203 int total; /* Buffer size */
204 int used; /* Amount of buffer in use (for DMA) */
205 void *address; /* Address of buffer */
208 typedef struct drm_buf_map {
209 int count; /* Length of buflist */
210 void *virtual; /* Mmaped area in user-virtual */
211 drm_buf_pub_t *list; /* Buffer information */
214 typedef struct drm_dma {
215 /* Indices here refer to the offset into
216 buflist in drm_buf_get_t. */
217 int context; /* Context handle */
218 int send_count; /* Number of buffers to send */
219 int *send_indices; /* List of handles to buffers */
220 int *send_sizes; /* Lengths of data to send */
221 drm_dma_flags_t flags; /* Flags */
222 int request_count; /* Number of buffers requested */
223 int request_size; /* Desired size for buffers */
224 int *request_indices; /* Buffer information */
226 int granted_count; /* Number of buffers granted */
230 _DRM_CONTEXT_PRESERVED = 0x01,
231 _DRM_CONTEXT_2DONLY = 0x02
234 typedef struct drm_ctx {
235 drm_context_t handle;
236 drm_ctx_flags_t flags;
239 typedef struct drm_ctx_res {
244 typedef struct drm_draw {
245 drm_drawable_t handle;
248 typedef struct drm_auth {
252 typedef struct drm_irq_busid {
259 typedef struct drm_agp_mode {
263 /* For drm_agp_alloc -- allocated a buffer */
264 typedef struct drm_agp_buffer {
265 unsigned long size; /* In bytes -- will round to page boundary */
266 unsigned long handle; /* Used for BIND/UNBIND ioctls */
267 unsigned long type; /* Type of memory to allocate */
268 unsigned long physical; /* Physical used by i810 */
271 /* For drm_agp_bind */
272 typedef struct drm_agp_binding {
273 unsigned long handle; /* From drm_agp_buffer */
274 unsigned long offset; /* In bytes -- will round to page boundary */
277 typedef struct drm_agp_info {
278 int agp_version_major;
279 int agp_version_minor;
281 unsigned long aperture_base; /* physical address */
282 unsigned long aperture_size; /* bytes */
283 unsigned long memory_allowed; /* bytes */
284 unsigned long memory_used;
286 /* PCI information */
287 unsigned short id_vendor;
288 unsigned short id_device;
291 #define DRM_IOCTL_BASE 'd'
292 #define DRM_IOCTL_NR(n) _IOC_NR(n)
293 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
294 #define DRM_IOR(nr,size) _IOR(DRM_IOCTL_BASE,nr,size)
295 #define DRM_IOW(nr,size) _IOW(DRM_IOCTL_BASE,nr,size)
296 #define DRM_IOWR(nr,size) _IOWR(DRM_IOCTL_BASE,nr,size)
299 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
300 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
301 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
302 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
304 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
305 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
306 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
307 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
308 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
309 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
310 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
311 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
312 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
313 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
314 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
316 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
317 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
318 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
319 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
320 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
321 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
322 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
323 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
324 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
325 #define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
326 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
327 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
328 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
330 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
331 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
332 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
333 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
334 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
335 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
336 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
337 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
339 /* Mga specific ioctls */
340 #define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t)
341 #define DRM_IOCTL_MGA_SWAP DRM_IOW( 0x41, drm_mga_swap_t)
342 #define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x42, drm_mga_clear_t)
343 #define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x43, drm_mga_iload_t)
344 #define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x44, drm_mga_vertex_t)
345 #define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x45, drm_lock_t )
346 #define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t)
348 /* I810 specific ioctls */
349 #define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t)
350 #define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t)
351 #define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t)
352 #define DRM_IOCTL_I810_FLUSH DRM_IO ( 0x43)
353 #define DRM_IOCTL_I810_GETAGE DRM_IO ( 0x44)
354 #define DRM_IOCTL_I810_GETBUF DRM_IOW( 0x45, drm_i810_dma_t)
355 #define DRM_IOCTL_I810_SWAP DRM_IO ( 0x46)
357 /* Rage 128 specific ioctls */
358 #define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
359 #define DRM_IOCTL_R128_RESET DRM_IO( 0x41)
360 #define DRM_IOCTL_R128_FLUSH DRM_IO( 0x42)
361 #define DRM_IOCTL_R128_IDLE DRM_IO( 0x43)
362 #define DRM_IOCTL_R128_PACKET DRM_IOW( 0x44, drm_r128_packet_t)
363 #define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x45, drm_r128_vertex_t)