2 * This file has been modified for the cdrkit suite.
4 * The behaviour and appearence of the program code below can differ to a major
5 * extent from the version distributed by the original author(s).
7 * For details, see Changelog file distributed with the cdrkit package. If you
8 * received this file from another source then ask the distributing person for
9 * a log of modifications.
13 /* @(#)scsireg.h 1.31 04/09/04 Copyright 1987 J. Schilling */
15 * usefull definitions for dealing with CCS SCSI - devices
17 * Copyright (c) 1987 J. Schilling
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License version 2
22 * as published by the Free Software Foundation.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License along with
30 * this program; see the file COPYING. If not, write to the Free Software
31 * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 #ifndef _SCG_SCSIREG_H
35 #define _SCG_SCSIREG_H
44 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
47 Ucbit type : 5; /* 0 */
48 Ucbit qualifier : 3; /* 0 */
50 Ucbit type_modifier : 7; /* 1 */
51 Ucbit removable : 1; /* 1 */
53 Ucbit ansi_version : 3; /* 2 */
54 Ucbit ecma_version : 3; /* 2 */
55 Ucbit iso_version : 2; /* 2 */
57 Ucbit data_format : 4; /* 3 */
58 Ucbit res3_54 : 2; /* 3 */
59 Ucbit termiop : 1; /* 3 */
60 Ucbit aenc : 1; /* 3 */
62 Ucbit add_len : 8; /* 4 */
63 Ucbit sense_len : 8; /* 5 */ /* only Emulex ??? */
64 Ucbit res2 : 8; /* 6 */
66 Ucbit softreset : 1; /* 7 */
73 Ucbit reladr : 1; /* 7 */
75 char vendor_info[8]; /* 8 */
76 char prod_ident[16]; /* 16 */
77 char prod_revision[4]; /* 32 */
79 char vendor_uniq[20]; /* 36 */
80 char reserved[40]; /* 56 */
84 #else /* Motorola byteorder */
87 Ucbit qualifier : 3; /* 0 */
88 Ucbit type : 5; /* 0 */
90 Ucbit removable : 1; /* 1 */
91 Ucbit type_modifier : 7; /* 1 */
93 Ucbit iso_version : 2; /* 2 */
94 Ucbit ecma_version : 3;
95 Ucbit ansi_version : 3; /* 2 */
97 Ucbit aenc : 1; /* 3 */
100 Ucbit data_format : 4; /* 3 */
102 Ucbit add_len : 8; /* 4 */
103 Ucbit sense_len : 8; /* 5 */ /* only Emulex ??? */
104 Ucbit res2 : 8; /* 6 */
105 Ucbit reladr : 1; /* 7 */
113 char vendor_info[8]; /* 8 */
114 char prod_ident[16]; /* 16 */
115 char prod_revision[4]; /* 32 */
117 char vendor_uniq[20]; /* 36 */
118 char reserved[40]; /* 56 */
123 #ifdef __SCG_COMPAT__
124 #define info vendor_info
125 #define ident prod_ident
126 #define revision prod_revision
129 /* Peripheral Device Qualifier */
131 #define INQ_DEV_PRESENT 0x00 /* Physical device present */
132 #define INQ_DEV_NOTPR 0x01 /* Physical device not present */
133 #define INQ_DEV_RES 0x02 /* Reserved */
134 #define INQ_DEV_NOTSUP 0x03 /* Logical unit not supported */
136 /* Peripheral Device Type */
138 #define INQ_DASD 0x00 /* Direct-access device (disk) */
139 #define INQ_SEQD 0x01 /* Sequential-access device (tape) */
140 #define INQ_PRTD 0x02 /* Printer device */
141 #define INQ_PROCD 0x03 /* Processor device */
142 #define INQ_OPTD 0x04 /* Write once device (optical disk) */
143 #define INQ_WORM 0x04 /* Write once device (optical disk) */
144 #define INQ_ROMD 0x05 /* CD-ROM device */
145 #define INQ_SCAN 0x06 /* Scanner device */
146 #define INQ_OMEM 0x07 /* Optical Memory device */
147 #define INQ_JUKE 0x08 /* Medium Changer device (jukebox) */
148 #define INQ_COMM 0x09 /* Communications device */
149 #define INQ_IT8_1 0x0A /* IT8 */
150 #define INQ_IT8_2 0x0B /* IT8 */
151 #define INQ_STARR 0x0C /* Storage array device */
152 #define INQ_ENCL 0x0D /* Enclosure services device */
153 #define INQ_SDAD 0x0E /* Simplyfied direct-access device */
154 #define INQ_OCRW 0x0F /* Optical card reader/writer device */
155 #define INQ_BRIDGE 0x10 /* Bridging expander device */
156 #define INQ_OSD 0x11 /* Object based storage device */
157 #define INQ_ADC 0x12 /* Automation/Drive interface */
158 #define INQ_WELLKNOWN 0x1E /* Well known logical unit */
159 #define INQ_NODEV 0x1F /* Unknown or no device */
160 #define INQ_NOTPR 0x1F /* Logical unit not present (SCSI-1) */
162 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
164 struct scsi_mode_header {
165 Ucbit sense_data_len : 8;
170 Ucbit write_prot : 1;
174 #else /* Motorola byteorder */
176 struct scsi_mode_header {
177 Ucbit sense_data_len : 8;
179 Ucbit write_prot : 1;
187 struct scsi_modesel_header {
188 Ucbit sense_data_len : 8;
194 struct scsi_mode_blockdesc {
201 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
203 struct acb_mode_data {
207 Uchar start_red_wcurrent[2];
208 Uchar start_precomp[2];
213 Ucbit fixed_media : 1;
218 #else /* Motorola byteorder */
220 struct acb_mode_data {
224 Uchar start_red_wcurrent[2];
225 Uchar start_precomp[2];
229 Ucbit fixed_media : 1;
236 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
238 struct scsi_mode_page_header {
246 * This is a hack that allows mode pages without
247 * any further bitfileds to be defined bitorder independent.
254 #else /* Motorola byteorder */
256 struct scsi_mode_page_header {
264 * This is a hack that allows mode pages without
265 * any further bitfileds to be defined bitorder independent.
274 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
276 struct scsi_mode_page_01 { /* Error recovery Parameters */
277 MP_P_CODE; /* parsave & pagecode */
278 Uchar p_len; /* 0x0A = 12 Bytes */
279 Ucbit disa_correction : 1; /* Byte 2 */
280 Ucbit term_on_rec_err : 1;
281 Ucbit report_rec_err : 1;
282 Ucbit en_early_corr : 1;
283 Ucbit read_continuous : 1;
284 Ucbit tranfer_block : 1;
285 Ucbit en_auto_reall_r : 1;
286 Ucbit en_auto_reall_w : 1; /* Byte 2 */
287 Uchar rd_retry_count; /* Byte 3 */
288 Uchar correction_span;
289 char head_offset_count;
290 char data_strobe_offset;
292 Uchar wr_retry_count;
294 Uchar recov_timelim[2];
297 #else /* Motorola byteorder */
299 struct scsi_mode_page_01 { /* Error recovery Parameters */
300 MP_P_CODE; /* parsave & pagecode */
301 Uchar p_len; /* 0x0A = 12 Bytes */
302 Ucbit en_auto_reall_w : 1; /* Byte 2 */
303 Ucbit en_auto_reall_r : 1;
304 Ucbit tranfer_block : 1;
305 Ucbit read_continuous : 1;
306 Ucbit en_early_corr : 1;
307 Ucbit report_rec_err : 1;
308 Ucbit term_on_rec_err : 1;
309 Ucbit disa_correction : 1; /* Byte 2 */
310 Uchar rd_retry_count; /* Byte 3 */
311 Uchar correction_span;
312 char head_offset_count;
313 char data_strobe_offset;
315 Uchar wr_retry_count;
317 Uchar recov_timelim[2];
322 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
324 struct scsi_mode_page_02 { /* Device dis/re connect Parameters */
325 MP_P_CODE; /* parsave & pagecode */
326 Uchar p_len; /* 0x0E = 16 Bytes */
327 Uchar buf_full_ratio;
328 Uchar buf_empt_ratio;
329 Uchar bus_inact_limit[2];
330 Uchar disc_time_limit[2];
331 Uchar conn_time_limit[2];
332 Uchar max_burst_size[2]; /* Start SCSI-2 */
333 Ucbit data_tr_dis_ctl : 2;
338 #else /* Motorola byteorder */
340 struct scsi_mode_page_02 { /* Device dis/re connect Parameters */
341 MP_P_CODE; /* parsave & pagecode */
342 Uchar p_len; /* 0x0E = 16 Bytes */
343 Uchar buf_full_ratio;
344 Uchar buf_empt_ratio;
345 Uchar bus_inact_limit[2];
346 Uchar disc_time_limit[2];
347 Uchar conn_time_limit[2];
348 Uchar max_burst_size[2]; /* Start SCSI-2 */
350 Ucbit data_tr_dis_ctl : 2;
355 #define DTDC_DATADONE 0x01 /*
356 * Target may not disconnect once
357 * data transfer is started until
358 * all data successfully transferred.
361 #define DTDC_CMDDONE 0x03 /*
362 * Target may not disconnect once
363 * data transfer is started until
368 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
370 struct scsi_mode_page_03 { /* Direct access format Paramters */
371 MP_P_CODE; /* parsave & pagecode */
372 Uchar p_len; /* 0x16 = 24 Bytes */
373 Uchar trk_per_zone[2];
374 Uchar alt_sec_per_zone[2];
375 Uchar alt_trk_per_zone[2];
376 Uchar alt_trk_per_vol[2];
377 Uchar sect_per_trk[2];
378 Uchar bytes_per_phys_sect[2];
383 Ucbit inhibit_save : 1;
384 Ucbit fmt_by_surface : 1;
391 #else /* Motorola byteorder */
393 struct scsi_mode_page_03 { /* Direct access format Paramters */
394 MP_P_CODE; /* parsave & pagecode */
395 Uchar p_len; /* 0x16 = 24 Bytes */
396 Uchar trk_per_zone[2];
397 Uchar alt_sec_per_zone[2];
398 Uchar alt_trk_per_zone[2];
399 Uchar alt_trk_per_vol[2];
400 Uchar sect_per_trk[2];
401 Uchar bytes_per_phys_sect[2];
408 Ucbit fmt_by_surface : 1;
409 Ucbit inhibit_save : 1;
415 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
417 struct scsi_mode_page_04 { /* Rigid disk Geometry Parameters */
418 MP_P_CODE; /* parsave & pagecode */
419 Uchar p_len; /* 0x16 = 24 Bytes */
422 Uchar start_precomp[3];
423 Uchar start_red_wcurrent[3];
425 Uchar landing_zone[3];
426 Ucbit rot_pos_locking : 2; /* Start SCSI-2 */
427 Ucbit : 6; /* Start SCSI-2 */
428 Uchar rotational_off;
430 Uchar rotation_rate[2];
434 #else /* Motorola byteorder */
436 struct scsi_mode_page_04 { /* Rigid disk Geometry Parameters */
437 MP_P_CODE; /* parsave & pagecode */
438 Uchar p_len; /* 0x16 = 24 Bytes */
441 Uchar start_precomp[3];
442 Uchar start_red_wcurrent[3];
444 Uchar landing_zone[3];
445 Ucbit : 6; /* Start SCSI-2 */
446 Ucbit rot_pos_locking : 2; /* Start SCSI-2 */
447 Uchar rotational_off;
449 Uchar rotation_rate[2];
454 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
456 struct scsi_mode_page_05 { /* Flexible disk Parameters */
457 MP_P_CODE; /* parsave & pagecode */
458 Uchar p_len; /* 0x1E = 32 Bytes */
459 Uchar transfer_rate[2];
462 Uchar bytes_per_phys_sect[2];
464 Uchar start_precomp[2];
465 Uchar start_red_wcurrent[2];
467 Uchar step_pulse_width;
468 Uchar head_settle_delay[2];
469 Uchar motor_on_delay;
470 Uchar motor_off_delay;
477 Uchar write_compensation;
478 Uchar head_load_delay;
479 Uchar head_unload_delay;
481 Ucbit pin_34_use : 4;
484 Uchar rotation_rate[2];
488 #else /* Motorola byteorder */
490 struct scsi_mode_page_05 { /* Flexible disk Parameters */
491 MP_P_CODE; /* parsave & pagecode */
492 Uchar p_len; /* 0x1E = 32 Bytes */
493 Uchar transfer_rate[2];
496 Uchar bytes_per_phys_sect[2];
498 Uchar start_precomp[2];
499 Uchar start_red_wcurrent[2];
501 Uchar step_pulse_width;
502 Uchar head_settle_delay[2];
503 Uchar motor_on_delay;
504 Uchar motor_off_delay;
511 Uchar write_compensation;
512 Uchar head_load_delay;
513 Uchar head_unload_delay;
514 Ucbit pin_34_use : 4;
518 Uchar rotation_rate[2];
523 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
525 struct scsi_mode_page_07 { /* Verify Error recovery */
526 MP_P_CODE; /* parsave & pagecode */
527 Uchar p_len; /* 0x0A = 12 Bytes */
528 Ucbit disa_correction : 1; /* Byte 2 */
529 Ucbit term_on_rec_err : 1;
530 Ucbit report_rec_err : 1;
531 Ucbit en_early_corr : 1;
532 Ucbit res : 4; /* Byte 2 */
533 Uchar ve_retry_count; /* Byte 3 */
534 Uchar ve_correction_span;
535 char res2[5]; /* Byte 5 */
536 Uchar ve_recov_timelim[2]; /* Byte 10 */
539 #else /* Motorola byteorder */
541 struct scsi_mode_page_07 { /* Verify Error recovery */
542 MP_P_CODE; /* parsave & pagecode */
543 Uchar p_len; /* 0x0A = 12 Bytes */
544 Ucbit res : 4; /* Byte 2 */
545 Ucbit en_early_corr : 1;
546 Ucbit report_rec_err : 1;
547 Ucbit term_on_rec_err : 1;
548 Ucbit disa_correction : 1; /* Byte 2 */
549 Uchar ve_retry_count; /* Byte 3 */
550 Uchar ve_correction_span;
551 char res2[5]; /* Byte 5 */
552 Uchar ve_recov_timelim[2]; /* Byte 10 */
556 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
558 struct scsi_mode_page_08 { /* Caching Parameters */
559 MP_P_CODE; /* parsave & pagecode */
560 Uchar p_len; /* 0x0A = 12 Bytes */
561 Ucbit disa_rd_cache : 1; /* Byte 2 */
562 Ucbit muliple_fact : 1;
563 Ucbit en_wt_cache : 1;
564 Ucbit res : 5; /* Byte 2 */
565 Ucbit wt_ret_pri : 4; /* Byte 3 */
566 Ucbit demand_rd_ret_pri: 4; /* Byte 3 */
567 Uchar disa_pref_tr_len[2]; /* Byte 4 */
568 Uchar min_pref[2]; /* Byte 6 */
569 Uchar max_pref[2]; /* Byte 8 */
570 Uchar max_pref_ceiling[2]; /* Byte 10 */
573 #else /* Motorola byteorder */
575 struct scsi_mode_page_08 { /* Caching Parameters */
576 MP_P_CODE; /* parsave & pagecode */
577 Uchar p_len; /* 0x0A = 12 Bytes */
578 Ucbit res : 5; /* Byte 2 */
579 Ucbit en_wt_cache : 1;
580 Ucbit muliple_fact : 1;
581 Ucbit disa_rd_cache : 1; /* Byte 2 */
582 Ucbit demand_rd_ret_pri: 4; /* Byte 3 */
583 Ucbit wt_ret_pri : 4;
584 Uchar disa_pref_tr_len[2]; /* Byte 4 */
585 Uchar min_pref[2]; /* Byte 6 */
586 Uchar max_pref[2]; /* Byte 8 */
587 Uchar max_pref_ceiling[2]; /* Byte 10 */
591 struct scsi_mode_page_09 { /* Peripheral device Parameters */
592 MP_P_CODE; /* parsave & pagecode */
593 Uchar p_len; /* >= 0x06 = 8 Bytes */
594 Uchar interface_id[2]; /* Byte 2 */
595 Uchar res[4]; /* Byte 4 */
596 Uchar vendor_specific[1]; /* Byte 8 */
599 #define PDEV_SCSI 0x0000 /* scsi interface */
600 #define PDEV_SMD 0x0001 /* SMD interface */
601 #define PDEV_ESDI 0x0002 /* ESDI interface */
602 #define PDEV_IPI2 0x0003 /* IPI-2 interface */
603 #define PDEV_IPI3 0x0004 /* IPI-3 interface */
605 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
607 struct scsi_mode_page_0A { /* Common device Control Parameters */
608 MP_P_CODE; /* parsave & pagecode */
609 Uchar p_len; /* 0x06 = 8 Bytes */
610 Ucbit rep_log_exeption: 1; /* Byte 2 */
611 Ucbit res : 7; /* Byte 2 */
612 Ucbit dis_queuing : 1; /* Byte 3 */
613 Ucbit queuing_err_man : 1;
615 Ucbit queue_alg_mod : 4; /* Byte 3 */
616 Ucbit EAENP : 1; /* Byte 4 */
620 Ucbit en_ext_cont_all : 1; /* Byte 4 */
622 Uchar ready_aen_hold_per[2]; /* Byte 6 */
625 #else /* Motorola byteorder */
627 struct scsi_mode_page_0A { /* Common device Control Parameters */
628 MP_P_CODE; /* parsave & pagecode */
629 Uchar p_len; /* 0x06 = 8 Bytes */
630 Ucbit res : 7; /* Byte 2 */
631 Ucbit rep_log_exeption: 1; /* Byte 2 */
632 Ucbit queue_alg_mod : 4; /* Byte 3 */
634 Ucbit queuing_err_man : 1;
635 Ucbit dis_queuing : 1; /* Byte 3 */
636 Ucbit en_ext_cont_all : 1; /* Byte 4 */
640 Ucbit EAENP : 1; /* Byte 4 */
642 Uchar ready_aen_hold_per[2]; /* Byte 6 */
646 #define CTRL_QMOD_RESTRICT 0x0
647 #define CTRL_QMOD_UNRESTRICT 0x1
650 struct scsi_mode_page_0B { /* Medium Types Supported Parameters */
651 MP_P_CODE; /* parsave & pagecode */
652 Uchar p_len; /* 0x06 = 8 Bytes */
653 Uchar res[2]; /* Byte 2 */
654 Uchar medium_one_supp; /* Byte 4 */
655 Uchar medium_two_supp; /* Byte 5 */
656 Uchar medium_three_supp; /* Byte 6 */
657 Uchar medium_four_supp; /* Byte 7 */
660 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
662 struct scsi_mode_page_0C { /* Notch & Partition Parameters */
663 MP_P_CODE; /* parsave & pagecode */
664 Uchar p_len; /* 0x16 = 24 Bytes */
665 Ucbit res : 6; /* Byte 2 */
666 Ucbit logical_notch : 1;
667 Ucbit notched_drive : 1; /* Byte 2 */
668 Uchar res2; /* Byte 3 */
669 Uchar max_notches[2]; /* Byte 4 */
670 Uchar active_notch[2]; /* Byte 6 */
671 Uchar starting_boundary[4]; /* Byte 8 */
672 Uchar ending_boundary[4]; /* Byte 12 */
673 Uchar pages_notched[8]; /* Byte 16 */
676 #else /* Motorola byteorder */
678 struct scsi_mode_page_0C { /* Notch & Partition Parameters */
679 MP_P_CODE; /* parsave & pagecode */
680 Uchar p_len; /* 0x16 = 24 Bytes */
681 Ucbit notched_drive : 1; /* Byte 2 */
682 Ucbit logical_notch : 1;
683 Ucbit res : 6; /* Byte 2 */
684 Uchar res2; /* Byte 3 */
685 Uchar max_notches[2]; /* Byte 4 */
686 Uchar active_notch[2]; /* Byte 6 */
687 Uchar starting_boundary[4]; /* Byte 8 */
688 Uchar ending_boundary[4]; /* Byte 12 */
689 Uchar pages_notched[8]; /* Byte 16 */
693 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
695 struct scsi_mode_page_0D { /* CD-ROM Parameters */
696 MP_P_CODE; /* parsave & pagecode */
697 Uchar p_len; /* 0x06 = 8 Bytes */
698 Uchar res; /* Byte 2 */
699 Ucbit inact_timer_mult: 4; /* Byte 3 */
700 Ucbit res2 : 4; /* Byte 3 */
701 Uchar s_un_per_m_un[2]; /* Byte 4 */
702 Uchar f_un_per_s_un[2]; /* Byte 6 */
705 #else /* Motorola byteorder */
707 struct scsi_mode_page_0D { /* CD-ROM Parameters */
708 MP_P_CODE; /* parsave & pagecode */
709 Uchar p_len; /* 0x06 = 8 Bytes */
710 Uchar res; /* Byte 2 */
711 Ucbit res2 : 4; /* Byte 3 */
712 Ucbit inact_timer_mult: 4; /* Byte 3 */
713 Uchar s_un_per_m_un[2]; /* Byte 4 */
714 Uchar f_un_per_s_un[2]; /* Byte 6 */
718 struct sony_mode_page_20 { /* Sony Format Mode Parameters */
719 MP_P_CODE; /* parsave & pagecode */
720 Uchar p_len; /* 0x0A = 12 Bytes */
723 #define num_bands user_band_size /* Gilt bei Type 1 */
724 Uchar user_band_size[4]; /* Gilt bei Type 0 */
725 Uchar spare_band_size[2];
729 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
731 struct toshiba_mode_page_20 { /* Toshiba Speed Control Parameters */
732 MP_P_CODE; /* parsave & pagecode */
733 Uchar p_len; /* 0x01 = 3 Bytes */
738 #else /* Motorola byteorder */
740 struct toshiba_mode_page_20 { /* Toshiba Speed Control Parameters */
741 MP_P_CODE; /* parsave & pagecode */
742 Uchar p_len; /* 0x01 = 3 Bytes */
748 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
750 struct ccs_mode_page_38 { /* CCS Caching Parameters */
751 MP_P_CODE; /* parsave & pagecode */
752 Uchar p_len; /* 0x0E = 14 Bytes */
754 Ucbit cache_table_size: 4; /* Byte 3 */
757 Ucbit wr_index_en : 1;
758 Ucbit res : 1; /* Byte 3 */
759 Uchar threshold; /* Byte 4 Prefetch threshold */
760 Uchar max_prefetch; /* Byte 5 Max. prefetch */
761 Uchar max_multiplier; /* Byte 6 Max. prefetch multiplier */
762 Uchar min_prefetch; /* Byte 7 Min. prefetch */
763 Uchar min_multiplier; /* Byte 8 Min. prefetch multiplier */
764 Uchar res3[8]; /* Byte 9 */
767 #else /* Motorola byteorder */
769 struct ccs_mode_page_38 { /* CCS Caching Parameters */
770 MP_P_CODE; /* parsave & pagecode */
771 Uchar p_len; /* 0x0E = 14 Bytes */
773 Ucbit res : 1; /* Byte 3 */
774 Ucbit wr_index_en : 1;
777 Ucbit cache_table_size: 4; /* Byte 3 */
778 Uchar threshold; /* Byte 4 Prefetch threshold */
779 Uchar max_prefetch; /* Byte 5 Max. prefetch */
780 Uchar max_multiplier; /* Byte 6 Max. prefetch multiplier */
781 Uchar min_prefetch; /* Byte 7 Min. prefetch */
782 Uchar min_multiplier; /* Byte 8 Min. prefetch multiplier */
783 Uchar res3[8]; /* Byte 9 */
787 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
789 struct cd_mode_page_05 { /* write parameters */
790 MP_P_CODE; /* parsave & pagecode */
791 Uchar p_len; /* 0x32 = 50 Bytes */
792 Ucbit write_type : 4; /* Session write type (PACKET/TAO...)*/
793 Ucbit test_write : 1; /* Do not actually write data */
794 Ucbit LS_V : 1; /* Link size valid */
795 Ucbit BUFE : 1; /* Enable Bufunderrun free rec. */
797 Ucbit track_mode : 4; /* Track mode (Q-sub control nibble) */
798 Ucbit copy : 1; /* 1st higher gen of copy prot track ~*/
799 Ucbit fp : 1; /* Fixed packed (if in packet mode) */
800 Ucbit multi_session : 2; /* Multi session write type */
801 Ucbit dbtype : 4; /* Data block type */
802 Ucbit res_4 : 4; /* Reserved */
803 Uchar link_size; /* Link Size (default is 7) */
804 Uchar res_6; /* Reserved */
805 Ucbit host_appl_code : 6; /* Host application code of disk */
806 Ucbit res_7 : 2; /* Reserved */
807 Uchar session_format; /* Session format (DA/CDI/XA) */
808 Uchar res_9; /* Reserved */
809 Uchar packet_size[4]; /* # of user datablocks/fixed packet */
810 Uchar audio_pause_len[2]; /* # of blocks where index is zero */
811 Uchar media_cat_number[16]; /* Media catalog Number (MCN) */
812 Uchar ISRC[14]; /* ISRC for this track */
814 Uchar vendor_uniq[4];
817 #else /* Motorola byteorder */
819 struct cd_mode_page_05 { /* write parameters */
820 MP_P_CODE; /* parsave & pagecode */
821 Uchar p_len; /* 0x32 = 50 Bytes */
823 Ucbit BUFE : 1; /* Enable Bufunderrun free rec. */
824 Ucbit LS_V : 1; /* Link size valid */
825 Ucbit test_write : 1; /* Do not actually write data */
826 Ucbit write_type : 4; /* Session write type (PACKET/TAO...)*/
827 Ucbit multi_session : 2; /* Multi session write type */
828 Ucbit fp : 1; /* Fixed packed (if in packet mode) */
829 Ucbit copy : 1; /* 1st higher gen of copy prot track */
830 Ucbit track_mode : 4; /* Track mode (Q-sub control nibble) */
831 Ucbit res_4 : 4; /* Reserved */
832 Ucbit dbtype : 4; /* Data block type */
833 Uchar link_size; /* Link Size (default is 7) */
834 Uchar res_6; /* Reserved */
835 Ucbit res_7 : 2; /* Reserved */
836 Ucbit host_appl_code : 6; /* Host application code of disk */
837 Uchar session_format; /* Session format (DA/CDI/XA) */
838 Uchar res_9; /* Reserved */
839 Uchar packet_size[4]; /* # of user datablocks/fixed packet */
840 Uchar audio_pause_len[2]; /* # of blocks where index is zero */
841 Uchar media_cat_number[16]; /* Media catalog Number (MCN) */
842 Uchar ISRC[14]; /* ISRC for this track */
844 Uchar vendor_uniq[4];
849 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
851 struct cd_wr_speed_performance {
852 Uchar res0; /* Reserved */
853 Ucbit rot_ctl_sel : 2; /* Rotational control selected */
854 Ucbit res_1_27 : 6; /* Reserved */
855 Uchar wr_speed_supp[2]; /* Supported write speed */
858 struct cd_mode_page_2A { /* CD Cap / mech status */
859 MP_P_CODE; /* parsave & pagecode */
860 Uchar p_len; /* 0x14 = 20 Bytes (MMC) */
861 /* 0x18 = 24 Bytes (MMC-2) */
862 /* 0x1C >= 28 Bytes (MMC-3) */
863 Ucbit cd_r_read : 1; /* Reads CD-R media */
864 Ucbit cd_rw_read : 1; /* Reads CD-RW media */
865 Ucbit method2 : 1; /* Reads fixed packet method2 media */
866 Ucbit dvd_rom_read : 1; /* Reads DVD ROM media */
867 Ucbit dvd_r_read : 1; /* Reads DVD-R media */
868 Ucbit dvd_ram_read : 1; /* Reads DVD-RAM media */
869 Ucbit res_2_67 : 2; /* Reserved */
870 Ucbit cd_r_write : 1; /* Supports writing CD-R media */
871 Ucbit cd_rw_write : 1; /* Supports writing CD-RW media */
872 Ucbit test_write : 1; /* Supports emulation write */
873 Ucbit res_3_3 : 1; /* Reserved */
874 Ucbit dvd_r_write : 1; /* Supports writing DVD-R media */
875 Ucbit dvd_ram_write : 1; /* Supports writing DVD-RAM media */
876 Ucbit res_3_67 : 2; /* Reserved */
877 Ucbit audio_play : 1; /* Supports Audio play operation */
878 Ucbit composite : 1; /* Deliveres composite A/V stream */
879 Ucbit digital_port_2 : 1; /* Supports digital output on port 2 */
880 Ucbit digital_port_1 : 1; /* Supports digital output on port 1 */
881 Ucbit mode_2_form_1 : 1; /* Reads Mode-2 form 1 media (XA) */
882 Ucbit mode_2_form_2 : 1; /* Reads Mode-2 form 2 media */
883 Ucbit multi_session : 1; /* Reads multi-session media */
884 Ucbit BUF : 1; /* Supports Buffer under. free rec. */
885 Ucbit cd_da_supported : 1; /* Reads audio data with READ CD cmd */
886 Ucbit cd_da_accurate : 1; /* READ CD data stream is accurate */
887 Ucbit rw_supported : 1; /* Reads R-W sub channel information */
888 Ucbit rw_deint_corr : 1; /* Reads de-interleved R-W sub chan */
889 Ucbit c2_pointers : 1; /* Supports C2 error pointers */
890 Ucbit ISRC : 1; /* Reads ISRC information */
891 Ucbit UPC : 1; /* Reads media catalog number (UPC) */
892 Ucbit read_bar_code : 1; /* Supports reading bar codes */
893 Ucbit lock : 1; /* PREVENT/ALLOW may lock media */
894 Ucbit lock_state : 1; /* Lock state 0=unlocked 1=locked */
895 Ucbit prevent_jumper : 1; /* State of prev/allow jumper 0=pres */
896 Ucbit eject : 1; /* Ejects disc/cartr with STOP LoEj */
897 Ucbit res_6_4 : 1; /* Reserved */
898 Ucbit loading_type : 3; /* Loading mechanism type */
899 Ucbit sep_chan_vol : 1; /* Vol controls each channel separat */
900 Ucbit sep_chan_mute : 1; /* Mute controls each channel separat*/
901 Ucbit disk_present_rep: 1; /* Changer supports disk present rep */
902 Ucbit sw_slot_sel : 1; /* Load empty slot in changer */
903 Ucbit side_change : 1; /* Side change capable */
904 Ucbit pw_in_lead_in : 1; /* Reads raw P-W sucode from lead in */
905 Ucbit res_7 : 2; /* Reserved */
906 Uchar max_read_speed[2]; /* Max. read speed in KB/s */
907 Uchar num_vol_levels[2]; /* # of supported volume levels */
908 Uchar buffer_size[2]; /* Buffer size for the data in KB */
909 Uchar cur_read_speed[2]; /* Current read speed in KB/s */
910 Uchar res_16; /* Reserved */
911 Ucbit res_17_0 : 1; /* Reserved */
912 Ucbit BCK : 1; /* Data valid on falling edge of BCK */
913 Ucbit RCK : 1; /* Set: HIGH high LRCK=left channel */
914 Ucbit LSBF : 1; /* Set: LSB first Clear: MSB first */
915 Ucbit length : 2; /* 0=32BCKs 1=16BCKs 2=24BCKs 3=24I2c*/
916 Ucbit res_17 : 2; /* Reserved */
917 Uchar max_write_speed[2]; /* Max. write speed supported in KB/s*/
918 Uchar cur_write_speed[2]; /* Current write speed in KB/s */
920 /* Byte 22 ... Only in MMC-2 */
921 Uchar copy_man_rev[2]; /* Copy management revision supported*/
922 Uchar res_24; /* Reserved */
923 Uchar res_25; /* Reserved */
925 /* Byte 26 ... Only in MMC-3 */
926 Uchar res_26; /* Reserved */
927 Ucbit res_27_27 : 6; /* Reserved */
928 Ucbit rot_ctl_sel : 2; /* Rotational control selected */
929 Uchar v3_cur_write_speed[2]; /* Current write speed in KB/s */
930 Uchar num_wr_speed_des[2]; /* # of wr speed perf descr. tables */
931 struct cd_wr_speed_performance
932 wr_speed_des[1]; /* wr speed performance descriptor */
933 /* Actually more (num_wr_speed_des) */
936 #else /* Motorola byteorder */
938 struct cd_wr_speed_performance {
939 Uchar res0; /* Reserved */
940 Ucbit res_1_27 : 6; /* Reserved */
941 Ucbit rot_ctl_sel : 2; /* Rotational control selected */
942 Uchar wr_speed_supp[2]; /* Supported write speed */
945 struct cd_mode_page_2A { /* CD Cap / mech status */
946 MP_P_CODE; /* parsave & pagecode */
947 Uchar p_len; /* 0x14 = 20 Bytes (MMC) */
948 /* 0x18 = 24 Bytes (MMC-2) */
949 /* 0x1C >= 28 Bytes (MMC-3) */
950 Ucbit res_2_67 : 2; /* Reserved */
951 Ucbit dvd_ram_read : 1; /* Reads DVD-RAM media */
952 Ucbit dvd_r_read : 1; /* Reads DVD-R media */
953 Ucbit dvd_rom_read : 1; /* Reads DVD ROM media */
954 Ucbit method2 : 1; /* Reads fixed packet method2 media */
955 Ucbit cd_rw_read : 1; /* Reads CD-RW media */
956 Ucbit cd_r_read : 1; /* Reads CD-R media */
957 Ucbit res_3_67 : 2; /* Reserved */
958 Ucbit dvd_ram_write : 1; /* Supports writing DVD-RAM media */
959 Ucbit dvd_r_write : 1; /* Supports writing DVD-R media */
960 Ucbit res_3_3 : 1; /* Reserved */
961 Ucbit test_write : 1; /* Supports emulation write */
962 Ucbit cd_rw_write : 1; /* Supports writing CD-RW media */
963 Ucbit cd_r_write : 1; /* Supports writing CD-R media */
964 Ucbit BUF : 1; /* Supports Buffer under. free rec. */
965 Ucbit multi_session : 1; /* Reads multi-session media */
966 Ucbit mode_2_form_2 : 1; /* Reads Mode-2 form 2 media */
967 Ucbit mode_2_form_1 : 1; /* Reads Mode-2 form 1 media (XA) */
968 Ucbit digital_port_1 : 1; /* Supports digital output on port 1 */
969 Ucbit digital_port_2 : 1; /* Supports digital output on port 2 */
970 Ucbit composite : 1; /* Deliveres composite A/V stream */
971 Ucbit audio_play : 1; /* Supports Audio play operation */
972 Ucbit read_bar_code : 1; /* Supports reading bar codes */
973 Ucbit UPC : 1; /* Reads media catalog number (UPC) */
974 Ucbit ISRC : 1; /* Reads ISRC information */
975 Ucbit c2_pointers : 1; /* Supports C2 error pointers */
976 Ucbit rw_deint_corr : 1; /* Reads de-interleved R-W sub chan */
977 Ucbit rw_supported : 1; /* Reads R-W sub channel information */
978 Ucbit cd_da_accurate : 1; /* READ CD data stream is accurate */
979 Ucbit cd_da_supported : 1; /* Reads audio data with READ CD cmd */
980 Ucbit loading_type : 3; /* Loading mechanism type */
981 Ucbit res_6_4 : 1; /* Reserved */
982 Ucbit eject : 1; /* Ejects disc/cartr with STOP LoEj */
983 Ucbit prevent_jumper : 1; /* State of prev/allow jumper 0=pres */
984 Ucbit lock_state : 1; /* Lock state 0=unlocked 1=locked */
985 Ucbit lock : 1; /* PREVENT/ALLOW may lock media */
986 Ucbit res_7 : 2; /* Reserved */
987 Ucbit pw_in_lead_in : 1; /* Reads raw P-W sucode from lead in */
988 Ucbit side_change : 1; /* Side change capable */
989 Ucbit sw_slot_sel : 1; /* Load empty slot in changer */
990 Ucbit disk_present_rep: 1; /* Changer supports disk present rep */
991 Ucbit sep_chan_mute : 1; /* Mute controls each channel separat*/
992 Ucbit sep_chan_vol : 1; /* Vol controls each channel separat */
993 Uchar max_read_speed[2]; /* Max. read speed in KB/s */
994 Uchar num_vol_levels[2]; /* # of supported volume levels */
995 Uchar buffer_size[2]; /* Buffer size for the data in KB */
996 Uchar cur_read_speed[2]; /* Current read speed in KB/s */
997 Uchar res_16; /* Reserved */
998 Ucbit res_17 : 2; /* Reserved */
999 Ucbit length : 2; /* 0=32BCKs 1=16BCKs 2=24BCKs 3=24I2c*/
1000 Ucbit LSBF : 1; /* Set: LSB first Clear: MSB first */
1001 Ucbit RCK : 1; /* Set: HIGH high LRCK=left channel */
1002 Ucbit BCK : 1; /* Data valid on falling edge of BCK */
1003 Ucbit res_17_0 : 1; /* Reserved */
1004 Uchar max_write_speed[2]; /* Max. write speed supported in KB/s*/
1005 Uchar cur_write_speed[2]; /* Current write speed in KB/s */
1007 /* Byte 22 ... Only in MMC-2 */
1008 Uchar copy_man_rev[2]; /* Copy management revision supported*/
1009 Uchar res_24; /* Reserved */
1010 Uchar res_25; /* Reserved */
1012 /* Byte 26 ... Only in MMC-3 */
1013 Uchar res_26; /* Reserved */
1014 Ucbit res_27_27 : 6; /* Reserved */
1015 Ucbit rot_ctl_sel : 2; /* Rotational control selected */
1016 Uchar v3_cur_write_speed[2]; /* Current write speed in KB/s */
1017 Uchar num_wr_speed_des[2]; /* # of wr speed perf descr. tables */
1018 struct cd_wr_speed_performance
1019 wr_speed_des[1]; /* wr speed performance descriptor */
1020 /* Actually more (num_wr_speed_des) */
1029 #define LT_CHANGER_IND 4
1030 #define LT_CHANGER_CART 5
1035 struct scsi_mode_data {
1036 struct scsi_mode_header header;
1037 struct scsi_mode_blockdesc blockdesc;
1039 struct acb_mode_data acb;
1040 struct scsi_mode_page_01 page1;
1041 struct scsi_mode_page_02 page2;
1042 struct scsi_mode_page_03 page3;
1043 struct scsi_mode_page_04 page4;
1044 struct scsi_mode_page_05 page5;
1045 struct scsi_mode_page_07 page7;
1046 struct scsi_mode_page_08 page8;
1047 struct scsi_mode_page_09 page9;
1048 struct scsi_mode_page_0A pageA;
1049 struct scsi_mode_page_0B pageB;
1050 struct scsi_mode_page_0C pageC;
1051 struct scsi_mode_page_0D pageD;
1052 struct sony_mode_page_20 sony20;
1053 struct toshiba_mode_page_20 toshiba20;
1054 struct ccs_mode_page_38 ccs38;
1058 struct scsi_capacity {
1059 Int32_t c_baddr; /* must convert byteorder!! */
1060 Int32_t c_bsize; /* must convert byteorder!! */
1063 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
1065 struct scsi_def_header {
1074 #else /* Motorola byteorder */
1076 struct scsi_def_header {
1087 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
1089 struct scsi_format_header {
1090 Ucbit res : 8; /* Adaptec 5500: 1 --> format track */
1091 Ucbit vu : 1; /* Vendor Unique */
1092 Ucbit immed : 1; /* Return Immediately from Format */
1093 Ucbit tryout : 1; /* Check if format parameters OK */
1094 Ucbit ipattern : 1; /* Init patter descriptor present */
1095 Ucbit serr : 1; /* Stop on error */
1096 Ucbit dcert : 1; /* Disable certification */
1097 Ucbit dmdl : 1; /* Disable manufacturer defect list */
1098 Ucbit enable : 1; /* Enable to use the next 3 bits */
1099 Uchar length[2]; /* Length of following list in bytes*/
1102 #else /* Motorola byteorder */
1104 struct scsi_format_header {
1105 Ucbit res : 8; /* Adaptec 5500: 1 --> format track */
1106 Ucbit enable : 1; /* Enable to use the next 3 bits */
1107 Ucbit dmdl : 1; /* Disable manufacturer defect list */
1108 Ucbit dcert : 1; /* Disable certification */
1109 Ucbit serr : 1; /* Stop on error */
1110 Ucbit ipattern : 1; /* Init patter descriptor present */
1111 Ucbit tryout : 1; /* Check if format parameters OK */
1112 Ucbit immed : 1; /* Return Immediately from Format */
1113 Ucbit vu : 1; /* Vendor Unique */
1114 Uchar length[2]; /* Length of following list in bytes*/
1118 struct scsi_def_bfi {
1124 struct scsi_def_phys {
1130 struct scsi_def_list {
1131 struct scsi_def_header hd;
1133 Uchar list_block[1][4];
1134 struct scsi_def_bfi list_bfi[1];
1135 struct scsi_def_phys list_phys[1];
1139 struct scsi_format_data {
1140 struct scsi_format_header hd;
1142 Uchar list_block[1][4];
1143 struct scsi_def_bfi list_bfi[1];
1144 struct scsi_def_phys list_phys[1];
1148 #define def_block def_list.list_block
1149 #define def_bfi def_list.list_bfi
1150 #define def_phys def_list.list_phys
1152 #define SC_DEF_BLOCK 0
1153 #define SC_DEF_BFI 4
1154 #define SC_DEF_PHYS 5
1156 #define SC_DEF_RES 7
1158 struct scsi_format_cap_header {
1159 Uchar res[3]; /* Reserved */
1160 Uchar len; /* Len (a multiple of 8) */
1163 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
1165 struct scsi_format_cap_desc {
1166 Uchar nblock[4]; /* Number of blocks */
1167 Ucbit desc_type : 2; /* Descriptor type */
1168 Ucbit fmt_type : 6; /* Format Taype */
1169 Uchar blen[3]; /* Logical block length */
1172 #else /* Motorola byteorder */
1174 struct scsi_format_cap_desc {
1175 Uchar nblock[4]; /* Number of blocks */
1176 Ucbit fmt_type : 6; /* Format Taype */
1177 Ucbit desc_type : 2; /* Descriptor type */
1178 Uchar blen[3]; /* Logical block length */
1183 * Defines for 'fmt_type'.
1185 #define FCAP_TYPE_DVDPLUS_FULL 0x26 /* DVD+RW Full Format */
1188 * Defines for 'desc_type'.
1189 * In case of FCAP_DESC_RES, the descriptor is a formatted capacity descriptor
1190 * and the 'blen' field is type dependent.
1191 * For all other cases, this is the Current/Maximum Capacity descriptor and
1192 * the value of 'fmt_type' is reserved and must be zero.
1194 #define FCAP_DESC_RES 0 /* Reserved */
1195 #define FCAP_DESC_UNFORM 1 /* Unformatted Media */
1196 #define FCAP_DESC_FORM 2 /* Formatted Media */
1197 #define FCAP_DESC_NOMEDIA 3 /* No Media */
1199 struct scsi_cap_data {
1200 struct scsi_format_cap_header hd;
1201 struct scsi_format_cap_desc list[1];
1205 struct scsi_send_diag_cmd {
1211 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */
1213 struct scsi_sector_header {
1223 #else /* Motorola byteorder */
1225 struct scsi_sector_header {
1240 #endif /* _SCG_SCSIREG_H */