3 * Copyright 2012 Samsung Electronics S.LSI Co. LTD
5 * Licensed under the Apache License, Version 2.0 (the "License")
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
9 * http://www.apache.org/licenses/LICENSE-2.0
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
19 * @file csc_linear_to_tiled_interleave_crop_neon.s
20 * @brief SEC_OMX specific define
21 * @author ShinWon Lee (shinwon.lee@samsung.com)
28 * Converts tiled data to linear
29 * Crops left, top, right, buttom
30 * 1. Y of NV12T to Y of YUV420P
31 * 2. Y of NV12T to Y of YUV420S
32 * 3. UV of NV12T to UV of YUV420S
35 * Y or UV plane address of YUV420[out]
38 * Y or UV plane address of NV12T[in]
43 * @param yuv420_height
44 * Y: Height of YUV420, UV: Height/2 of YUV420[in]
47 * Crop size of left. It should be even.
50 * Crop size of top. It should be even.
53 * Crop size of right. It should be even.
56 * Crop size of buttom. It should be even.
61 .global csc_linear_to_tiled_interleave_crop_neon
62 .type csc_linear_to_tiled_interleave_crop_neon, %function
63 csc_linear_to_tiled_interleave_crop_neon:
81 stmfd sp!, {r4-r12,r14} @ backup registers
83 ldr r4, [sp, #40] @ load linear_y_size to r4
85 ldr r10, [sp, #48] @ r10 = top
86 ldr r14, [sp, #56] @ r14 = buttom
87 ldr r11, [sp, #44] @ r11 = left
88 ldr r12, [sp, #52] @ r12 = right
90 sub r10, r4, r10 @ aligned_y_size = ((yuv420_height-top-buttom)>>5)<<5
93 sub r11, r3, r11 @ aligned_x_size = ((yuv420_width-left-right)>>6)<<6
105 ldr r12, [sp, #48] @ r12 = top
106 ldr r8, [sp, #44] @ r8 = left
108 mov r11, r3, asr #1 @ temp1 = (yuv420_width/2)*(i+top)
111 add r11, r11, r5, asr #1 @ temp1 = temp1+j/2
112 add r11, r11, r8, asr #1 @ temp1 = temp1+left/2
114 mov r12, r3, asr #1 @ temp2 = yuv420_width/2
115 sub r12, r12, #16 @ temp2 = yuv420_width-16
117 add r8, r1, r11 @ linear_addr = linear_src_u+temp1
118 add r11, r2, r11 @ temp1 = linear_src_v+temp1
119 add r7, r0, r7 @ tiled_addr = tiled_dest+tiled_addr
122 vld1.8 {q0}, [r8]! @ load {linear_src_u, 32}
123 vld1.8 {q2}, [r8], r12
125 vld1.8 {q4}, [r8]! @ load {linear_src_u+(linear_x_size/2)*1, 32}
126 vld1.8 {q6}, [r8], r12
128 vld1.8 {q8}, [r8]! @ load {linear_src_u+(linear_x_size/2)*2, 32}
129 vld1.8 {q10}, [r8], r12
130 pld [r11, r3, asr #1]
131 vld1.8 {q12}, [r8]! @ load {linear_src_u+(linear_x_size/2)*3, 32}
132 vld1.8 {q14}, [r8], r12
134 vld1.8 {q1}, [r11]! @ load {linear_src_v, 32}
135 vld1.8 {q3}, [r11], r12
137 vld1.8 {q5}, [r11]! @ load {linear_src_v+(linear_x_size/2)*1, 32}
138 vld1.8 {q7}, [r11], r12
140 vld1.8 {q9}, [r11]! @ load {linear_src_v+(linear_x_size/2)*2, 32}
141 vld1.8 {q11}, [r11], r12
143 vld1.8 {q13}, [r11]! @ load {linear_src_v+(linear_x_size/2)*3, 32}
144 vld1.8 {q15}, [r11], r12
145 vst2.8 {q0, q1}, [r7]! @ store {tiled_addr}
146 vst2.8 {q2, q3}, [r7]!
147 vst2.8 {q4, q5}, [r7]! @ store {tiled_addr+64*1}
148 vst2.8 {q6, q7}, [r7]!
149 vst2.8 {q8, q9}, [r7]! @ store {tiled_addr+64*2}
150 vst2.8 {q10, q11}, [r7]!
151 vst2.8 {q12, q13}, [r7]! @ store {tiled_addr+64*3}
152 vst2.8 {q14, q15}, [r7]!
155 vld1.8 {q0}, [r8]! @ load {linear_src_u+(linear_x_size/2)*4, 32}
156 vld1.8 {q2}, [r8], r12
158 vld1.8 {q4}, [r8]! @ load {linear_src_u+(linear_x_size/2)*5, 32}
159 vld1.8 {q6}, [r8], r12
161 vld1.8 {q8}, [r8]! @ load {linear_src_u+(linear_x_size/2)*6, 32}
162 vld1.8 {q10}, [r8], r12
163 pld [r11, r3, asr #1]
164 vld1.8 {q12}, [r8]! @ load {linear_src_u+(linear_x_size/2)*7, 32}
165 vld1.8 {q14}, [r8], r12
167 vld1.8 {q1}, [r11]! @ load {linear_src_v+(linear_x_size/2)*4, 32}
168 vld1.8 {q3}, [r11], r12
170 vld1.8 {q5}, [r11]! @ load {linear_src_v+(linear_x_size/2)*5, 32}
171 vld1.8 {q7}, [r11], r12
173 vld1.8 {q9}, [r11]! @ load {linear_src_v+(linear_x_size/2)*6, 32}
174 vld1.8 {q11}, [r11], r12
176 vld1.8 {q13}, [r11]! @ load {linear_src_v+(linear_x_size/2)*7, 32}
177 vld1.8 {q15}, [r11], r12
178 vst2.8 {q0, q1}, [r7]! @ store {tiled_addr+64*4}
179 vst2.8 {q2, q3}, [r7]!
180 vst2.8 {q4, q5}, [r7]! @ store {tiled_addr+64*5}
181 vst2.8 {q6, q7}, [r7]!
182 vst2.8 {q8, q9}, [r7]! @ store {tiled_addr+64*6}
183 vst2.8 {q10, q11}, [r7]!
184 vst2.8 {q12, q13}, [r7]! @ store {tiled_addr+64*7}
185 vst2.8 {q14, q15}, [r7]!
188 vld1.8 {q0}, [r8]! @ load {linear_src_u+(linear_x_size/2)*8, 32}
189 vld1.8 {q2}, [r8], r12
191 vld1.8 {q4}, [r8]! @ load {linear_src_u+(linear_x_size/2)*9, 32}
192 vld1.8 {q6}, [r8], r12
194 vld1.8 {q8}, [r8]! @ load {linear_src_u+(linear_x_size/2)*10, 32}
195 vld1.8 {q10}, [r8], r12
196 pld [r11, r3, asr #1]
197 vld1.8 {q12}, [r8]! @ load {linear_src_u+(linear_x_size/2)*11, 32}
198 vld1.8 {q14}, [r8], r12
200 vld1.8 {q1}, [r11]! @ load {linear_src_v+(linear_x_size/2)*8, 32}
201 vld1.8 {q3}, [r11], r12
203 vld1.8 {q5}, [r11]! @ load {linear_src_v+(linear_x_size/2)*9, 32}
204 vld1.8 {q7}, [r11], r12
206 vld1.8 {q9}, [r11]! @ load {linear_src_v+(linear_x_size/2)*10, 32}
207 vld1.8 {q11}, [r11], r12
209 vld1.8 {q13}, [r11]! @ load {linear_src_v+(linear_x_size/2)*11, 32}
210 vld1.8 {q15}, [r11], r12
211 vst2.8 {q0, q1}, [r7]! @ store {tiled_addr+64*8}
212 vst2.8 {q2, q3}, [r7]!
213 vst2.8 {q4, q5}, [r7]! @ store {tiled_addr+64*9}
214 vst2.8 {q6, q7}, [r7]!
215 vst2.8 {q8, q9}, [r7]! @ store {tiled_addr+64*10}
216 vst2.8 {q10, q11}, [r7]!
217 vst2.8 {q12, q13}, [r7]! @ store {tiled_addr+64*11}
218 vst2.8 {q14, q15}, [r7]!
221 vld1.8 {q0}, [r8]! @ load {linear_src_u+(linear_x_size/2)*12, 32}
222 vld1.8 {q2}, [r8], r12
224 vld1.8 {q4}, [r8]! @ load {linear_src_u+(linear_x_size/2)*13, 32}
225 vld1.8 {q6}, [r8], r12
227 vld1.8 {q8}, [r8]! @ load {linear_src_u+(linear_x_size/2)*14, 32}
228 vld1.8 {q10}, [r8], r12
229 pld [r11, r3, asr #1]
230 vld1.8 {q12}, [r8]! @ load {linear_src_u+(linear_x_size/2)*15, 32}
231 vld1.8 {q14}, [r8], r12
233 vld1.8 {q1}, [r11]! @ load {linear_src_v+(linear_x_size/2)*12, 32}
234 vld1.8 {q3}, [r11], r12
236 vld1.8 {q5}, [r11]! @ load {linear_src_v+(linear_x_size/2)*13, 32}
237 vld1.8 {q7}, [r11], r12
239 vld1.8 {q9}, [r11]! @ load {linear_src_v+(linear_x_size/2)*14, 32}
240 vld1.8 {q11}, [r11], r12
242 vld1.8 {q13}, [r11]! @ load {linear_src_v+(linear_x_size/2)*15, 32}
243 vld1.8 {q15}, [r11], r12
244 vst2.8 {q0, q1}, [r7]! @ store {tiled_addr+64*12}
245 vst2.8 {q2, q3}, [r7]!
246 vst2.8 {q4, q5}, [r7]! @ store {tiled_addr+64*13}
247 vst2.8 {q6, q7}, [r7]!
248 vst2.8 {q8, q9}, [r7]! @ store {tiled_addr+64*14}
249 vst2.8 {q10, q11}, [r7]!
250 vst2.8 {q12, q13}, [r7]! @ store {tiled_addr+64*15}
251 vst2.8 {q14, q15}, [r7]!
254 vld1.8 {q0}, [r8]! @ load {linear_src_u+(linear_x_size/2)*16, 32}
255 vld1.8 {q2}, [r8], r12
257 vld1.8 {q4}, [r8]! @ load {linear_src_u+(linear_x_size/2)*17, 32}
258 vld1.8 {q6}, [r8], r12
260 vld1.8 {q8}, [r8]! @ load {linear_src_u+(linear_x_size/2)*18, 32}
261 vld1.8 {q10}, [r8], r12
262 pld [r11, r3, asr #1]
263 vld1.8 {q12}, [r8]! @ load {linear_src_u+(linear_x_size/2)*19, 32}
264 vld1.8 {q14}, [r8], r12
266 vld1.8 {q1}, [r11]! @ load {linear_src_v+(linear_x_size/2)*16, 32}
267 vld1.8 {q3}, [r11], r12
269 vld1.8 {q5}, [r11]! @ load {linear_src_v+(linear_x_size/2)*17, 32}
270 vld1.8 {q7}, [r11], r12
272 vld1.8 {q9}, [r11]! @ load {linear_src_v+(linear_x_size/2)*18, 32}
273 vld1.8 {q11}, [r11], r12
275 vld1.8 {q13}, [r11]! @ load {linear_src_v+(linear_x_size/2)*19, 32}
276 vld1.8 {q15}, [r11], r12
277 vst2.8 {q0, q1}, [r7]! @ store {tiled_addr+64*16}
278 vst2.8 {q2, q3}, [r7]!
279 vst2.8 {q4, q5}, [r7]! @ store {tiled_addr+64*17}
280 vst2.8 {q6, q7}, [r7]!
281 vst2.8 {q8, q9}, [r7]! @ store {tiled_addr+64*18}
282 vst2.8 {q10, q11}, [r7]!
283 vst2.8 {q12, q13}, [r7]! @ store {tiled_addr+64*19}
284 vst2.8 {q14, q15}, [r7]!
287 vld1.8 {q0}, [r8]! @ load {linear_src_u+(linear_x_size/2)*20, 32}
288 vld1.8 {q2}, [r8], r12
290 vld1.8 {q4}, [r8]! @ load {linear_src_u+(linear_x_size/2)*21, 32}
291 vld1.8 {q6}, [r8], r12
293 vld1.8 {q8}, [r8]! @ load {linear_src_u+(linear_x_size/2)*22, 32}
294 vld1.8 {q10}, [r8], r12
295 pld [r11, r3, asr #1]
296 vld1.8 {q12}, [r8]! @ load {linear_src_u+(linear_x_size/2)*23, 32}
297 vld1.8 {q14}, [r8], r12
299 vld1.8 {q1}, [r11]! @ load {linear_src_v+(linear_x_size/2)*20, 32}
300 vld1.8 {q3}, [r11], r12
302 vld1.8 {q5}, [r11]! @ load {linear_src_v+(linear_x_size/2)*21, 32}
303 vld1.8 {q7}, [r11], r12
305 vld1.8 {q9}, [r11]! @ load {linear_src_v+(linear_x_size/2)*22, 32}
306 vld1.8 {q11}, [r11], r12
308 vld1.8 {q13}, [r11]! @ load {linear_src_v+(linear_x_size/2)*23, 32}
309 vld1.8 {q15}, [r11], r12
310 vst2.8 {q0, q1}, [r7]! @ store {tiled_addr+64*20}
311 vst2.8 {q2, q3}, [r7]!
312 vst2.8 {q4, q5}, [r7]! @ store {tiled_addr+64*21}
313 vst2.8 {q6, q7}, [r7]!
314 vst2.8 {q8, q9}, [r7]! @ store {tiled_addr+64*22}
315 vst2.8 {q10, q11}, [r7]!
316 vst2.8 {q12, q13}, [r7]! @ store {tiled_addr+64*23}
317 vst2.8 {q14, q15}, [r7]!
320 vld1.8 {q0}, [r8]! @ load {linear_src_u+(linear_x_size/2)*24, 32}
321 vld1.8 {q2}, [r8], r12
323 vld1.8 {q4}, [r8]! @ load {linear_src_u+(linear_x_size/2)*25, 32}
324 vld1.8 {q6}, [r8], r12
326 vld1.8 {q8}, [r8]! @ load {linear_src_u+(linear_x_size/2)*26, 32}
327 vld1.8 {q10}, [r8], r12
328 pld [r11, r3, asr #1]
329 vld1.8 {q12}, [r8]! @ load {linear_src_u+(linear_x_size/2)*27, 32}
330 vld1.8 {q14}, [r8], r12
332 vld1.8 {q1}, [r11]! @ load {linear_src_v+(linear_x_size/2)*24, 32}
333 vld1.8 {q3}, [r11], r12
335 vld1.8 {q5}, [r11]! @ load {linear_src_v+(linear_x_size/2)*25, 32}
336 vld1.8 {q7}, [r11], r12
338 vld1.8 {q9}, [r11]! @ load {linear_src_v+(linear_x_size/2)*26, 32}
339 vld1.8 {q11}, [r11], r12
341 vld1.8 {q13}, [r11]! @ load {linear_src_v+(linear_x_size/2)*27, 32}
342 vld1.8 {q15}, [r11], r12
343 vst2.8 {q0, q1}, [r7]! @ store {tiled_addr+64*24}
344 vst2.8 {q2, q3}, [r7]!
345 vst2.8 {q4, q5}, [r7]! @ store {tiled_addr+64*25}
346 vst2.8 {q6, q7}, [r7]!
347 vst2.8 {q8, q9}, [r7]! @ store {tiled_addr+64*26}
348 vst2.8 {q10, q11}, [r7]!
349 vst2.8 {q12, q13}, [r7]! @ store {tiled_addr+64*27}
350 vst2.8 {q14, q15}, [r7]!
353 vld1.8 {q0}, [r8]! @ load {linear_src_u+(linear_x_size/2)*28, 32}
354 vld1.8 {q2}, [r8], r12
356 vld1.8 {q4}, [r8]! @ load {linear_src_u+(linear_x_size/2)*29, 32}
357 vld1.8 {q6}, [r8], r12
359 vld1.8 {q8}, [r8]! @ load {linear_src_u+(linear_x_size/2)*30, 32}
360 vld1.8 {q10}, [r8], r12
361 pld [r11, r3, asr #1]
362 vld1.8 {q12}, [r8]! @ load {linear_src_u+(linear_x_size/2)*31, 32}
363 vld1.8 {q14}, [r8], r12
365 vld1.8 {q1}, [r11]! @ load {linear_src_v+(linear_x_size/2)*28, 32}
366 vld1.8 {q3}, [r11], r12
368 vld1.8 {q5}, [r11]! @ load {linear_src_v+(linear_x_size/2)*29, 32}
369 vld1.8 {q7}, [r11], r12
370 vld1.8 {q9}, [r11]! @ load {linear_src_v+(linear_x_size/2)*30, 32}
371 vld1.8 {q11}, [r11], r12
372 vld1.8 {q13}, [r11]! @ load {linear_src_v+(linear_x_size/2)*31, 32}
373 vld1.8 {q15}, [r11], r12
374 vst2.8 {q0, q1}, [r7]! @ store {tiled_addr+64*28}
375 vst2.8 {q2, q3}, [r7]!
376 vst2.8 {q4, q5}, [r7]! @ store {tiled_addr+64*29}
377 vst2.8 {q6, q7}, [r7]!
378 vst2.8 {q8, q9}, [r7]! @ store {tiled_addr+64*30}
379 vst2.8 {q10, q11}, [r7]!
380 vst2.8 {q12, q13}, [r7]! @ store {tiled_addr+64*31}
381 vst2.8 {q14, q15}, [r7]!
383 add r5, r5, #64 @ j = j+64
384 cmp r5, r9 @ j<aligned_x_size
385 blt LOOP_ALIGNED_X_SIZE
387 add r6, r6, #32 @ i = i+32
388 cmp r6, r10 @ i<aligned_y_size
389 blt LOOP_ALIGNED_Y_SIZE
392 beq LOOP_LINEAR_Y_SIZE_2_START
394 LOOP_LINEAR_Y_SIZE_1:
397 LOOP_ALIGNED_X_SIZE_1:
401 ldr r12, [sp, #48] @ r12 = top
402 ldr r8, [sp, #44] @ r8 = left
404 mov r11, r3, asr #1 @ temp1 = (yuv420_width/2)*(i+top)
407 add r11, r11, r5, asr #1 @ temp1 = temp1+j/2
408 add r11, r11, r8, asr #1 @ temp1 = temp1+left/2
410 add r8, r1, r11 @ linear_addr = linear_src_u+temp1
411 add r11, r2, r11 @ temp1 = linear_src_v+temp1
412 add r7, r0, r7 @ tiled_addr = tiled_dest+tiled_addr
413 and r14, r6, #0x1F @ temp3 = i&0x1F@
414 mov r14, r14, lsl #6 @ temp3 = temp3*64
415 add r7, r7, r14 @ tiled_addr = tiled_addr+temp3
417 vld1.8 {q0}, [r8]! @ load {linear_src_u, 32}
419 vld1.8 {q1}, [r11]! @ load {linear_src_v, 32}
421 vst2.8 {q0, q1}, [r7]! @ store {tiled_addr}
422 vst2.8 {q2, q3}, [r7]!
424 add r5, r5, #64 @ j = j+64
425 cmp r5, r9 @ j<aligned_x_size
426 blt LOOP_ALIGNED_X_SIZE_1
428 ldr r12, [sp, #48] @ r12 = top
429 ldr r8, [sp, #56] @ r8 = buttom
430 add r6, r6, #1 @ i = i+1
433 cmp r6, r12 @ i<(yuv420_height-top-buttom)
434 blt LOOP_LINEAR_Y_SIZE_1
436 LOOP_LINEAR_Y_SIZE_2_START:
441 LOOP_LINEAR_Y_SIZE_2:
443 mov r5, r9 @ j = aligned_x_size
444 LOOP_LINEAR_X_SIZE_2:
448 ldr r12, [sp, #48] @ r12 = top
449 ldr r8, [sp, #44] @ r8 = left
451 mov r11, r3, asr #1 @ temp1 = (yuv420_width/2)*(i+top)
454 add r11, r11, r5, asr #1 @ temp1 = temp1+j/2
455 add r11, r11, r8, asr #1 @ temp1 = temp1+left/2
457 mov r12, r3, asr #1 @ temp2 = linear_x_size/2
458 sub r12, r12, #1 @ temp2 = linear_x_size-1
460 add r8, r1, r11 @ linear_addr = linear_src_u+temp1
461 add r11, r2, r11 @ temp1 = linear_src_v+temp1
462 add r7, r0, r7 @ tiled_addr = tiled_dest+tiled_addr
463 and r14, r6, #0x1F @ temp3 = i&0x1F@
464 mov r14, r14, lsl #6 @ temp3 = temp3*64
465 add r7, r7, r14 @ tiled_addr = tiled_addr+temp3
466 and r14, r5, #0x3F @ temp3 = j&0x3F
467 add r7, r7, r14 @ tiled_addr = tiled_addr+temp3
475 ldr r12, [sp, #44] @ r12 = left
476 ldr r8, [sp, #52] @ r8 = right
477 add r5, r5, #2 @ j = j+2
480 cmp r5, r12 @ j<(yuv420_width-left-right)
481 blt LOOP_LINEAR_X_SIZE_2
483 ldr r12, [sp, #48] @ r12 = top
484 ldr r8, [sp, #56] @ r8 = buttom
485 add r6, r6, #1 @ i = i+1
488 cmp r6, r12 @ i<(yuv420_height-top-buttom)
489 blt LOOP_LINEAR_Y_SIZE_2
492 ldmfd sp!, {r4-r12,r15} @ restore registers
497 mov r12, r6, asr #5 @ temp2 = i>>5
498 mov r11, r5, asr #6 @ temp1 = j>>6
500 and r14, r12, #0x1 @ if (temp2 & 0x1)
502 bne GET_TILED_OFFSET_EVEN_FORMULA_1
504 GET_TILED_OFFSET_ODD_FORMULA:
506 ldr r7, [sp, #48] @ r7 = left , (r14 was pushed to stack)
507 ldr r8, [sp, #56] @ r8 = right , (r14 was pushed to stack)
510 add r14, r14, #127 @ temp3 = (((yuv420_width-left-right)+127)>>7)<<7
511 bic r14, r14, #0x7F @ temp3 = (temp3 >>7)<<7
512 mov r14, r14, asr #6 @ temp3 = temp3>>6
513 sub r7, r12, #1 @ tiled_addr = temp2-1
514 mul r7, r7, r14 @ tiled_addr = tiled_addr*temp3
515 add r7, r7, r11 @ tiled_addr = tiled_addr+temp1
516 add r7, r7, #2 @ tiled_addr = tiled_addr+2
517 bic r14, r11, #0x3 @ temp3 = (temp1>>2)<<2
518 add r7, r7, r14 @ tiled_addr = tiled_addr+temp3
519 mov r7, r7, lsl #11 @ tiled_addr = tiled_addr<<11
520 b GET_TILED_OFFSET_RETURN
522 GET_TILED_OFFSET_EVEN_FORMULA_1:
523 ldr r7, [sp, #52] @ r7 = top, (r14 was pushed to stack)
524 ldr r8, [sp, #60] @ r8 = buttom, (r14 was pushed to stack)
527 add r14, r14, #31 @ temp3 = (((yuv420_height-top-buttom)+31)>>5)<<5
528 bic r14, r14, #0x1F @ temp3 = (temp3>>5)<<5
529 sub r14, r14, #32 @ temp3 = temp3 - 32
530 cmp r6, r14 @ if (i<(temp3-32)) {
531 bge GET_TILED_OFFSET_EVEN_FORMULA_2
532 add r14, r11, #2 @ temp3 = temp1+2
533 bic r14, r14, #3 @ temp3 = (temp3>>2)<<2
534 add r7, r11, r14 @ tiled_addr = temp1+temp3
535 ldr r8, [sp, #48] @ r8 = left, (r14 was pushed to stack)
537 ldr r8, [sp, #56] @ r8 = right, (r14 was pushed to stack)
539 add r14, r14, #127 @ temp3 = (((yuv420_width-left-right)+127)>>7)<<7
540 bic r14, r14, #0x7F @ temp3 = (temp3>>7)<<7
541 mov r14, r14, asr #6 @ temp3 = temp3>>6
542 mul r12, r12, r14 @ tiled_y_index = tiled_y_index*temp3
543 add r7, r7, r12 @ tiled_addr = tiled_addr+tiled_y_index
544 mov r7, r7, lsl #11 @
545 b GET_TILED_OFFSET_RETURN
547 GET_TILED_OFFSET_EVEN_FORMULA_2:
548 ldr r8, [sp, #48] @ r8 = left, (r14 was pushed to stack)
550 ldr r8, [sp, #56] @ r8 = right, (r14 was pushed to stack)
552 add r14, r14, #127 @ temp3 = (((yuv420_width-left-right)+127)>>7)<<7
553 bic r14, r14, #0x7F @ temp3 = (temp3>>7)<<7
554 mov r14, r14, asr #6 @ temp3 = temp3>>6
555 mul r7, r12, r14 @ tiled_addr = temp2*temp3
556 add r7, r7, r11 @ tiled_addr = tiled_addr+temp3
557 mov r7, r7, lsl #11 @ tiled_addr = tiled_addr<<11@
559 GET_TILED_OFFSET_RETURN:
560 ldmfd sp!, {r15} @ restore registers