1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
49 #include <sys/ioctl.h>
52 #include <sys/types.h>
55 #include "libdrm_lists.h"
56 #include "intel_atomic.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
69 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
71 struct drm_intel_gem_bo_bucket {
76 /* Only cache objects up to 64MB. Bigger than that, and the rounding of the
77 * size makes many operations fail that wouldn't otherwise.
79 #define DRM_INTEL_GEM_BO_BUCKETS 14
80 typedef struct _drm_intel_bufmgr_gem {
81 drm_intel_bufmgr bufmgr;
89 struct drm_i915_gem_exec_object *exec_objects;
90 drm_intel_bo **exec_bos;
94 /** Array of lists of cached gem objects of power-of-two sizes */
95 struct drm_intel_gem_bo_bucket cache_bucket[DRM_INTEL_GEM_BO_BUCKETS];
101 } drm_intel_bufmgr_gem;
103 struct _drm_intel_bo_gem {
111 * Kenel-assigned global name for this object
113 unsigned int global_name;
116 * Index of the buffer within the validation list while preparing a
117 * batchbuffer execution.
122 * Current tiling mode
124 uint32_t tiling_mode;
125 uint32_t swizzle_mode;
129 /** Array passed to the DRM containing relocation information. */
130 struct drm_i915_gem_relocation_entry *relocs;
131 /** Array of bos corresponding to relocs[i].target_handle */
132 drm_intel_bo **reloc_target_bo;
133 /** Number of entries in relocs */
135 /** Mapped address for the buffer, saved across map/unmap cycles */
137 /** GTT virtual address for the buffer, saved across map/unmap cycles */
144 * Boolean of whether this BO and its children have been included in
145 * the current drm_intel_bufmgr_check_aperture_space() total.
147 char included_in_check_aperture;
150 * Boolean of whether this buffer has been used as a relocation
151 * target and had its size accounted for, and thus can't have any
152 * further relocations added to it.
154 char used_as_reloc_target;
157 * Boolean of whether this buffer can be re-used
162 * Size in bytes of this buffer and its relocation descendents.
164 * Used to avoid costly tree walking in
165 * drm_intel_bufmgr_check_aperture in the common case.
170 * Number of potential fence registers required by this buffer and its
173 int reloc_tree_fences;
177 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
180 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
183 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
184 uint32_t * swizzle_mode);
187 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
190 static void drm_intel_gem_bo_unreference_locked(drm_intel_bo *bo);
192 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
194 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
197 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
198 uint32_t *tiling_mode)
200 unsigned long min_size, max_size;
203 if (*tiling_mode == I915_TILING_NONE)
206 /* 965+ just need multiples of page size for tiling */
207 if (IS_I965G(bufmgr_gem))
208 return ROUND_UP_TO(size, 4096);
210 /* Older chips need powers of two, of at least 512k or 1M */
211 if (IS_I9XX(bufmgr_gem)) {
212 min_size = 1024*1024;
213 max_size = 128*1024*1024;
216 max_size = 64*1024*1024;
219 if (size > max_size) {
220 *tiling_mode = I915_TILING_NONE;
224 for (i = min_size; i < size; i <<= 1)
231 * Round a given pitch up to the minimum required for X tiling on a
232 * given chip. We use 512 as the minimum to allow for a later tiling
236 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
237 unsigned long pitch, uint32_t tiling_mode)
239 unsigned long tile_width = 512;
242 if (tiling_mode == I915_TILING_NONE)
243 return ROUND_UP_TO(pitch, tile_width);
245 /* 965 is flexible */
246 if (IS_I965G(bufmgr_gem))
247 return ROUND_UP_TO(pitch, tile_width);
249 /* Pre-965 needs power of two tile width */
250 for (i = tile_width; i < pitch; i <<= 1)
256 static struct drm_intel_gem_bo_bucket *
257 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
262 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
263 struct drm_intel_gem_bo_bucket *bucket =
264 &bufmgr_gem->cache_bucket[i];
265 if (bucket->size >= size) {
274 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
278 for (i = 0; i < bufmgr_gem->exec_count; i++) {
279 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
280 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
282 if (bo_gem->relocs == NULL) {
283 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
288 for (j = 0; j < bo_gem->reloc_count; j++) {
289 drm_intel_bo *target_bo = bo_gem->reloc_target_bo[j];
290 drm_intel_bo_gem *target_gem =
291 (drm_intel_bo_gem *) target_bo;
293 DBG("%2d: %d (%s)@0x%08llx -> "
294 "%d (%s)@0x%08lx + 0x%08x\n",
296 bo_gem->gem_handle, bo_gem->name,
297 (unsigned long long)bo_gem->relocs[j].offset,
298 target_gem->gem_handle,
301 bo_gem->relocs[j].delta);
307 drm_intel_gem_bo_reference(drm_intel_bo *bo)
309 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
311 assert(atomic_read(&bo_gem->refcount) > 0);
312 atomic_inc(&bo_gem->refcount);
316 * Adds the given buffer to the list of buffers to be validated (moved into the
317 * appropriate memory type) with the next batch submission.
319 * If a buffer is validated multiple times in a batch submission, it ends up
320 * with the intersection of the memory type flags and the union of the
324 drm_intel_add_validate_buffer(drm_intel_bo *bo)
326 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
327 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
330 if (bo_gem->validate_index != -1)
333 /* Extend the array of validation entries as necessary. */
334 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
335 int new_size = bufmgr_gem->exec_size * 2;
340 bufmgr_gem->exec_objects =
341 realloc(bufmgr_gem->exec_objects,
342 sizeof(*bufmgr_gem->exec_objects) * new_size);
343 bufmgr_gem->exec_bos =
344 realloc(bufmgr_gem->exec_bos,
345 sizeof(*bufmgr_gem->exec_bos) * new_size);
346 bufmgr_gem->exec_size = new_size;
349 index = bufmgr_gem->exec_count;
350 bo_gem->validate_index = index;
351 /* Fill in array entry */
352 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
353 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
354 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
355 bufmgr_gem->exec_objects[index].alignment = 0;
356 bufmgr_gem->exec_objects[index].offset = 0;
357 bufmgr_gem->exec_bos[index] = bo;
358 drm_intel_gem_bo_reference(bo);
359 bufmgr_gem->exec_count++;
362 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
366 drm_intel_setup_reloc_list(drm_intel_bo *bo)
368 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
369 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
370 unsigned int max_relocs = bufmgr_gem->max_relocs;
372 if (bo->size / 4 < max_relocs)
373 max_relocs = bo->size / 4;
375 bo_gem->relocs = malloc(max_relocs *
376 sizeof(struct drm_i915_gem_relocation_entry));
377 bo_gem->reloc_target_bo = malloc(max_relocs * sizeof(drm_intel_bo *));
383 drm_intel_gem_bo_busy(drm_intel_bo *bo)
385 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
386 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
387 struct drm_i915_gem_busy busy;
390 memset(&busy, 0, sizeof(busy));
391 busy.handle = bo_gem->gem_handle;
393 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
395 return (ret == 0 && busy.busy);
399 drm_intel_gem_bo_madvise(drm_intel_bufmgr_gem *bufmgr_gem,
400 drm_intel_bo_gem *bo_gem, int state)
402 struct drm_i915_gem_madvise madv;
404 madv.handle = bo_gem->gem_handle;
407 ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
409 return madv.retained;
412 /* drop the oldest entries that have been purged by the kernel */
414 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
415 struct drm_intel_gem_bo_bucket *bucket)
417 while (!DRMLISTEMPTY(&bucket->head)) {
418 drm_intel_bo_gem *bo_gem;
420 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
421 bucket->head.next, head);
422 if (drm_intel_gem_bo_madvise
423 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
426 DRMLISTDEL(&bo_gem->head);
427 drm_intel_gem_bo_free(&bo_gem->bo);
431 static drm_intel_bo *
432 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
437 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
438 drm_intel_bo_gem *bo_gem;
439 unsigned int page_size = getpagesize();
441 struct drm_intel_gem_bo_bucket *bucket;
442 int alloc_from_cache;
443 unsigned long bo_size;
446 if (flags & BO_ALLOC_FOR_RENDER)
449 /* Round the allocated size up to a power of two number of pages. */
450 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
452 /* If we don't have caching at this size, don't actually round the
455 if (bucket == NULL) {
457 if (bo_size < page_size)
460 bo_size = bucket->size;
463 pthread_mutex_lock(&bufmgr_gem->lock);
464 /* Get a buffer out of the cache if available */
466 alloc_from_cache = 0;
467 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
469 /* Allocate new render-target BOs from the tail (MRU)
470 * of the list, as it will likely be hot in the GPU
471 * cache and in the aperture for us.
473 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
474 bucket->head.prev, head);
475 DRMLISTDEL(&bo_gem->head);
476 alloc_from_cache = 1;
478 /* For non-render-target BOs (where we're probably
479 * going to map it first thing in order to fill it
480 * with data), check if the last BO in the cache is
481 * unbusy, and only reuse in that case. Otherwise,
482 * allocating a new buffer is probably faster than
483 * waiting for the GPU to finish.
485 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
486 bucket->head.next, head);
487 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
488 alloc_from_cache = 1;
489 DRMLISTDEL(&bo_gem->head);
493 if (alloc_from_cache) {
494 if (!drm_intel_gem_bo_madvise
495 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
496 drm_intel_gem_bo_free(&bo_gem->bo);
497 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
503 pthread_mutex_unlock(&bufmgr_gem->lock);
505 if (!alloc_from_cache) {
506 struct drm_i915_gem_create create;
508 bo_gem = calloc(1, sizeof(*bo_gem));
512 bo_gem->bo.size = bo_size;
513 memset(&create, 0, sizeof(create));
514 create.size = bo_size;
516 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CREATE, &create);
517 bo_gem->gem_handle = create.handle;
518 bo_gem->bo.handle = bo_gem->gem_handle;
523 bo_gem->bo.bufmgr = bufmgr;
527 atomic_set(&bo_gem->refcount, 1);
528 bo_gem->validate_index = -1;
529 bo_gem->reloc_tree_size = bo_gem->bo.size;
530 bo_gem->reloc_tree_fences = 0;
531 bo_gem->used_as_reloc_target = 0;
532 bo_gem->tiling_mode = I915_TILING_NONE;
533 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
534 bo_gem->reusable = 1;
536 DBG("bo_create: buf %d (%s) %ldb\n",
537 bo_gem->gem_handle, bo_gem->name, size);
542 static drm_intel_bo *
543 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
546 unsigned int alignment)
548 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
549 BO_ALLOC_FOR_RENDER);
552 static drm_intel_bo *
553 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
556 unsigned int alignment)
558 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0);
561 static drm_intel_bo *
562 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
563 int x, int y, int cpp, uint32_t *tiling_mode,
564 unsigned long *pitch, unsigned long flags)
566 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
568 unsigned long size, stride, aligned_y = y;
571 if (*tiling_mode == I915_TILING_NONE)
572 aligned_y = ALIGN(y, 2);
573 else if (*tiling_mode == I915_TILING_X)
574 aligned_y = ALIGN(y, 8);
575 else if (*tiling_mode == I915_TILING_Y)
576 aligned_y = ALIGN(y, 32);
579 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, *tiling_mode);
580 size = stride * aligned_y;
581 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
583 bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags);
587 ret = drm_intel_gem_bo_set_tiling(bo, tiling_mode, stride);
589 drm_intel_gem_bo_unreference(bo);
599 * Returns a drm_intel_bo wrapping the given buffer object handle.
601 * This can be used when one application needs to pass a buffer object
605 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
609 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
610 drm_intel_bo_gem *bo_gem;
612 struct drm_gem_open open_arg;
613 struct drm_i915_gem_get_tiling get_tiling;
615 bo_gem = calloc(1, sizeof(*bo_gem));
619 memset(&open_arg, 0, sizeof(open_arg));
620 open_arg.name = handle;
621 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_OPEN, &open_arg);
623 fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
624 name, handle, strerror(errno));
628 bo_gem->bo.size = open_arg.size;
629 bo_gem->bo.offset = 0;
630 bo_gem->bo.virtual = NULL;
631 bo_gem->bo.bufmgr = bufmgr;
633 atomic_set(&bo_gem->refcount, 1);
634 bo_gem->validate_index = -1;
635 bo_gem->gem_handle = open_arg.handle;
636 bo_gem->global_name = handle;
637 bo_gem->reusable = 0;
639 memset(&get_tiling, 0, sizeof(get_tiling));
640 get_tiling.handle = bo_gem->gem_handle;
641 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
643 drm_intel_gem_bo_unreference(&bo_gem->bo);
646 bo_gem->tiling_mode = get_tiling.tiling_mode;
647 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
648 if (bo_gem->tiling_mode == I915_TILING_NONE)
649 bo_gem->reloc_tree_fences = 0;
651 bo_gem->reloc_tree_fences = 1;
653 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
659 drm_intel_gem_bo_free(drm_intel_bo *bo)
661 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
662 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
663 struct drm_gem_close close;
666 if (bo_gem->mem_virtual)
667 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
668 if (bo_gem->gtt_virtual)
669 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
671 free(bo_gem->reloc_target_bo);
672 free(bo_gem->relocs);
674 /* Close this object */
675 memset(&close, 0, sizeof(close));
676 close.handle = bo_gem->gem_handle;
677 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
680 "DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
681 bo_gem->gem_handle, bo_gem->name, strerror(errno));
686 /** Frees all cached buffers significantly older than @time. */
688 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
692 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
693 struct drm_intel_gem_bo_bucket *bucket =
694 &bufmgr_gem->cache_bucket[i];
696 while (!DRMLISTEMPTY(&bucket->head)) {
697 drm_intel_bo_gem *bo_gem;
699 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
700 bucket->head.next, head);
701 if (time - bo_gem->free_time <= 1)
704 DRMLISTDEL(&bo_gem->head);
706 drm_intel_gem_bo_free(&bo_gem->bo);
711 static void drm_intel_gem_bo_unreference_final(drm_intel_bo *bo)
713 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
714 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
715 struct drm_intel_gem_bo_bucket *bucket;
716 uint32_t tiling_mode;
718 if (bo_gem->relocs != NULL) {
721 /* Unreference all the target buffers */
722 for (i = 0; i < bo_gem->reloc_count; i++)
723 drm_intel_gem_bo_unreference_locked(bo_gem->
727 DBG("bo_unreference final: %d (%s)\n",
728 bo_gem->gem_handle, bo_gem->name);
730 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
731 /* Put the buffer into our internal cache for reuse if we can. */
732 tiling_mode = I915_TILING_NONE;
733 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
734 drm_intel_gem_bo_set_tiling(bo, &tiling_mode, 0) == 0) {
735 struct timespec time;
737 clock_gettime(CLOCK_MONOTONIC, &time);
738 bo_gem->free_time = time.tv_sec;
741 bo_gem->validate_index = -1;
742 bo_gem->reloc_count = 0;
744 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
746 drm_intel_gem_bo_madvise(bufmgr_gem, bo_gem,
748 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
750 drm_intel_gem_bo_free(bo);
754 static void drm_intel_gem_bo_unreference_locked(drm_intel_bo *bo)
756 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
758 assert(atomic_read(&bo_gem->refcount) > 0);
759 if (atomic_dec_and_test(&bo_gem->refcount))
760 drm_intel_gem_bo_unreference_final(bo);
763 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
765 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
767 assert(atomic_read(&bo_gem->refcount) > 0);
768 if (atomic_dec_and_test(&bo_gem->refcount)) {
769 drm_intel_bufmgr_gem *bufmgr_gem =
770 (drm_intel_bufmgr_gem *) bo->bufmgr;
771 pthread_mutex_lock(&bufmgr_gem->lock);
772 drm_intel_gem_bo_unreference_final(bo);
773 pthread_mutex_unlock(&bufmgr_gem->lock);
777 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
779 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
780 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
781 struct drm_i915_gem_set_domain set_domain;
784 pthread_mutex_lock(&bufmgr_gem->lock);
786 /* Allow recursive mapping. Mesa may recursively map buffers with
787 * nested display loops.
789 if (!bo_gem->mem_virtual) {
790 struct drm_i915_gem_mmap mmap_arg;
792 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
794 memset(&mmap_arg, 0, sizeof(mmap_arg));
795 mmap_arg.handle = bo_gem->gem_handle;
797 mmap_arg.size = bo->size;
798 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MMAP, &mmap_arg);
801 "%s:%d: Error mapping buffer %d (%s): %s .\n",
802 __FILE__, __LINE__, bo_gem->gem_handle,
803 bo_gem->name, strerror(errno));
804 pthread_mutex_unlock(&bufmgr_gem->lock);
807 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
809 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
810 bo_gem->mem_virtual);
811 bo->virtual = bo_gem->mem_virtual;
813 set_domain.handle = bo_gem->gem_handle;
814 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
816 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
818 set_domain.write_domain = 0;
820 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN,
822 } while (ret == -1 && errno == EINTR);
824 fprintf(stderr, "%s:%d: Error setting to CPU domain %d: %s\n",
825 __FILE__, __LINE__, bo_gem->gem_handle,
827 pthread_mutex_unlock(&bufmgr_gem->lock);
831 pthread_mutex_unlock(&bufmgr_gem->lock);
836 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
838 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
839 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
840 struct drm_i915_gem_set_domain set_domain;
843 pthread_mutex_lock(&bufmgr_gem->lock);
845 /* Get a mapping of the buffer if we haven't before. */
846 if (bo_gem->gtt_virtual == NULL) {
847 struct drm_i915_gem_mmap_gtt mmap_arg;
849 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
852 memset(&mmap_arg, 0, sizeof(mmap_arg));
853 mmap_arg.handle = bo_gem->gem_handle;
855 /* Get the fake offset back... */
856 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MMAP_GTT,
860 "%s:%d: Error preparing buffer map %d (%s): %s .\n",
862 bo_gem->gem_handle, bo_gem->name,
864 pthread_mutex_unlock(&bufmgr_gem->lock);
869 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
870 MAP_SHARED, bufmgr_gem->fd,
872 if (bo_gem->gtt_virtual == MAP_FAILED) {
874 "%s:%d: Error mapping buffer %d (%s): %s .\n",
876 bo_gem->gem_handle, bo_gem->name,
878 pthread_mutex_unlock(&bufmgr_gem->lock);
883 bo->virtual = bo_gem->gtt_virtual;
885 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
886 bo_gem->gtt_virtual);
888 /* Now move it to the GTT domain so that the CPU caches are flushed */
889 set_domain.handle = bo_gem->gem_handle;
890 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
891 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
893 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN,
895 } while (ret == -1 && errno == EINTR);
898 fprintf(stderr, "%s:%d: Error setting domain %d: %s\n",
899 __FILE__, __LINE__, bo_gem->gem_handle,
903 pthread_mutex_unlock(&bufmgr_gem->lock);
908 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
910 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
911 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
917 assert(bo_gem->gtt_virtual != NULL);
919 pthread_mutex_lock(&bufmgr_gem->lock);
921 pthread_mutex_unlock(&bufmgr_gem->lock);
926 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
928 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
929 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
930 struct drm_i915_gem_sw_finish sw_finish;
936 assert(bo_gem->mem_virtual != NULL);
938 pthread_mutex_lock(&bufmgr_gem->lock);
940 /* Cause a flush to happen if the buffer's pinned for scanout, so the
941 * results show up in a timely manner.
943 sw_finish.handle = bo_gem->gem_handle;
945 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SW_FINISH,
947 } while (ret == -1 && errno == EINTR);
950 pthread_mutex_unlock(&bufmgr_gem->lock);
955 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
956 unsigned long size, const void *data)
958 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
959 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
960 struct drm_i915_gem_pwrite pwrite;
963 memset(&pwrite, 0, sizeof(pwrite));
964 pwrite.handle = bo_gem->gem_handle;
965 pwrite.offset = offset;
967 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
969 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_PWRITE, &pwrite);
970 } while (ret == -1 && errno == EINTR);
973 "%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
974 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
975 (int)size, strerror(errno));
981 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
983 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
984 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
987 get_pipe_from_crtc_id.crtc_id = crtc_id;
988 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
989 &get_pipe_from_crtc_id);
991 /* We return -1 here to signal that we don't
992 * know which pipe is associated with this crtc.
993 * This lets the caller know that this information
994 * isn't available; using the wrong pipe for
995 * vblank waiting can cause the chipset to lock up
1000 return get_pipe_from_crtc_id.pipe;
1004 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1005 unsigned long size, void *data)
1007 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1008 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1009 struct drm_i915_gem_pread pread;
1012 memset(&pread, 0, sizeof(pread));
1013 pread.handle = bo_gem->gem_handle;
1014 pread.offset = offset;
1016 pread.data_ptr = (uint64_t) (uintptr_t) data;
1018 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_PREAD, &pread);
1019 } while (ret == -1 && errno == EINTR);
1022 "%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1023 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1024 (int)size, strerror(errno));
1029 /** Waits for all GPU rendering to the object to have completed. */
1031 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1033 drm_intel_gem_bo_start_gtt_access(bo, 0);
1037 * Sets the object to the GTT read and possibly write domain, used by the X
1038 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1040 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1041 * can do tiled pixmaps this way.
1044 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1046 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1047 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1048 struct drm_i915_gem_set_domain set_domain;
1051 set_domain.handle = bo_gem->gem_handle;
1052 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1053 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1055 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN,
1057 } while (ret == -1 && errno == EINTR);
1060 "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1061 __FILE__, __LINE__, bo_gem->gem_handle,
1062 set_domain.read_domains, set_domain.write_domain,
1068 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1070 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1073 free(bufmgr_gem->exec_objects);
1074 free(bufmgr_gem->exec_bos);
1076 pthread_mutex_destroy(&bufmgr_gem->lock);
1078 /* Free any cached buffer objects we were going to reuse */
1079 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
1080 struct drm_intel_gem_bo_bucket *bucket =
1081 &bufmgr_gem->cache_bucket[i];
1082 drm_intel_bo_gem *bo_gem;
1084 while (!DRMLISTEMPTY(&bucket->head)) {
1085 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1086 bucket->head.next, head);
1087 DRMLISTDEL(&bo_gem->head);
1089 drm_intel_gem_bo_free(&bo_gem->bo);
1097 * Adds the target buffer to the validation list and adds the relocation
1098 * to the reloc_buffer's relocation list.
1100 * The relocation entry at the given offset must already contain the
1101 * precomputed relocation value, because the kernel will optimize out
1102 * the relocation entry write when the buffer hasn't moved from the
1103 * last known offset in target_bo.
1106 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1107 drm_intel_bo *target_bo, uint32_t target_offset,
1108 uint32_t read_domains, uint32_t write_domain)
1110 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1111 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1112 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1114 pthread_mutex_lock(&bufmgr_gem->lock);
1116 /* Create a new relocation list if needed */
1117 if (bo_gem->relocs == NULL)
1118 drm_intel_setup_reloc_list(bo);
1120 /* Check overflow */
1121 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1124 assert(offset <= bo->size - 4);
1125 assert((write_domain & (write_domain - 1)) == 0);
1127 /* Make sure that we're not adding a reloc to something whose size has
1128 * already been accounted for.
1130 assert(!bo_gem->used_as_reloc_target);
1131 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1132 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1134 /* Flag the target to disallow further relocations in it. */
1135 target_bo_gem->used_as_reloc_target = 1;
1137 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1138 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1139 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1140 target_bo_gem->gem_handle;
1141 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1142 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1143 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1145 bo_gem->reloc_target_bo[bo_gem->reloc_count] = target_bo;
1146 drm_intel_gem_bo_reference(target_bo);
1148 bo_gem->reloc_count++;
1150 pthread_mutex_unlock(&bufmgr_gem->lock);
1156 * Walk the tree of relocations rooted at BO and accumulate the list of
1157 * validations to be performed and update the relocation buffers with
1158 * index values into the validation list.
1161 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1163 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1166 if (bo_gem->relocs == NULL)
1169 for (i = 0; i < bo_gem->reloc_count; i++) {
1170 drm_intel_bo *target_bo = bo_gem->reloc_target_bo[i];
1172 /* Continue walking the tree depth-first. */
1173 drm_intel_gem_bo_process_reloc(target_bo);
1175 /* Add the target to the validate list */
1176 drm_intel_add_validate_buffer(target_bo);
1181 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1185 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1186 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1187 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1189 /* Update the buffer offset */
1190 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1191 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1192 bo_gem->gem_handle, bo_gem->name, bo->offset,
1193 (unsigned long long)bufmgr_gem->exec_objects[i].
1195 bo->offset = bufmgr_gem->exec_objects[i].offset;
1201 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1202 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1204 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1205 struct drm_i915_gem_execbuffer execbuf;
1208 pthread_mutex_lock(&bufmgr_gem->lock);
1209 /* Update indices and set up the validate list. */
1210 drm_intel_gem_bo_process_reloc(bo);
1212 /* Add the batch buffer to the validation list. There are no
1213 * relocations pointing to it.
1215 drm_intel_add_validate_buffer(bo);
1217 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1218 execbuf.buffer_count = bufmgr_gem->exec_count;
1219 execbuf.batch_start_offset = 0;
1220 execbuf.batch_len = used;
1221 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1222 execbuf.num_cliprects = num_cliprects;
1227 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_EXECBUFFER,
1229 } while (ret != 0 && errno == EAGAIN);
1231 if (ret != 0 && errno == ENOMEM) {
1233 "Execbuffer fails to pin. "
1234 "Estimate: %u. Actual: %u. Available: %u\n",
1235 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1238 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1241 (unsigned int)bufmgr_gem->gtt_size);
1243 drm_intel_update_buffer_offsets(bufmgr_gem);
1245 if (bufmgr_gem->bufmgr.debug)
1246 drm_intel_gem_dump_validation_list(bufmgr_gem);
1248 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1249 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1250 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1252 /* Disconnect the buffer from the validate list */
1253 bo_gem->validate_index = -1;
1254 drm_intel_gem_bo_unreference_locked(bo);
1255 bufmgr_gem->exec_bos[i] = NULL;
1257 bufmgr_gem->exec_count = 0;
1258 pthread_mutex_unlock(&bufmgr_gem->lock);
1264 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1266 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1267 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1268 struct drm_i915_gem_pin pin;
1271 memset(&pin, 0, sizeof(pin));
1272 pin.handle = bo_gem->gem_handle;
1273 pin.alignment = alignment;
1276 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_PIN, &pin);
1277 } while (ret == -1 && errno == EINTR);
1282 bo->offset = pin.offset;
1287 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1289 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1290 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1291 struct drm_i915_gem_unpin unpin;
1294 memset(&unpin, 0, sizeof(unpin));
1295 unpin.handle = bo_gem->gem_handle;
1297 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1305 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1308 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1309 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1310 struct drm_i915_gem_set_tiling set_tiling;
1313 if (bo_gem->global_name == 0 && *tiling_mode == bo_gem->tiling_mode)
1316 /* If we're going from non-tiling to tiling, bump fence count */
1317 if (bo_gem->tiling_mode == I915_TILING_NONE)
1318 bo_gem->reloc_tree_fences++;
1320 memset(&set_tiling, 0, sizeof(set_tiling));
1321 set_tiling.handle = bo_gem->gem_handle;
1322 set_tiling.tiling_mode = *tiling_mode;
1323 set_tiling.stride = stride;
1325 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_TILING, &set_tiling);
1327 *tiling_mode = bo_gem->tiling_mode;
1330 bo_gem->tiling_mode = set_tiling.tiling_mode;
1331 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1333 /* If we're going from tiling to non-tiling, drop fence count */
1334 if (bo_gem->tiling_mode == I915_TILING_NONE)
1335 bo_gem->reloc_tree_fences--;
1337 *tiling_mode = bo_gem->tiling_mode;
1342 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1343 uint32_t * swizzle_mode)
1345 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1347 *tiling_mode = bo_gem->tiling_mode;
1348 *swizzle_mode = bo_gem->swizzle_mode;
1353 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1355 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1356 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1357 struct drm_gem_flink flink;
1360 if (!bo_gem->global_name) {
1361 memset(&flink, 0, sizeof(flink));
1362 flink.handle = bo_gem->gem_handle;
1364 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1367 bo_gem->global_name = flink.name;
1368 bo_gem->reusable = 0;
1371 *name = bo_gem->global_name;
1376 * Enables unlimited caching of buffer objects for reuse.
1378 * This is potentially very memory expensive, as the cache at each bucket
1379 * size is only bounded by how many buffers of that size we've managed to have
1380 * in flight at once.
1383 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1385 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1387 bufmgr_gem->bo_reuse = 1;
1391 * Return the additional aperture space required by the tree of buffer objects
1395 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1397 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1401 if (bo == NULL || bo_gem->included_in_check_aperture)
1405 bo_gem->included_in_check_aperture = 1;
1407 for (i = 0; i < bo_gem->reloc_count; i++)
1409 drm_intel_gem_bo_get_aperture_space(bo_gem->
1410 reloc_target_bo[i]);
1416 * Count the number of buffers in this list that need a fence reg
1418 * If the count is greater than the number of available regs, we'll have
1419 * to ask the caller to resubmit a batch with fewer tiled buffers.
1421 * This function over-counts if the same buffer is used multiple times.
1424 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1427 unsigned int total = 0;
1429 for (i = 0; i < count; i++) {
1430 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1435 total += bo_gem->reloc_tree_fences;
1441 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1442 * for the next drm_intel_bufmgr_check_aperture_space() call.
1445 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1447 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1450 if (bo == NULL || !bo_gem->included_in_check_aperture)
1453 bo_gem->included_in_check_aperture = 0;
1455 for (i = 0; i < bo_gem->reloc_count; i++)
1456 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1457 reloc_target_bo[i]);
1461 * Return a conservative estimate for the amount of aperture required
1462 * for a collection of buffers. This may double-count some buffers.
1465 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1468 unsigned int total = 0;
1470 for (i = 0; i < count; i++) {
1471 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1473 total += bo_gem->reloc_tree_size;
1479 * Return the amount of aperture needed for a collection of buffers.
1480 * This avoids double counting any buffers, at the cost of looking
1481 * at every buffer in the set.
1484 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1487 unsigned int total = 0;
1489 for (i = 0; i < count; i++) {
1490 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1491 /* For the first buffer object in the array, we get an
1492 * accurate count back for its reloc_tree size (since nothing
1493 * had been flagged as being counted yet). We can save that
1494 * value out as a more conservative reloc_tree_size that
1495 * avoids double-counting target buffers. Since the first
1496 * buffer happens to usually be the batch buffer in our
1497 * callers, this can pull us back from doing the tree
1498 * walk on every new batch emit.
1501 drm_intel_bo_gem *bo_gem =
1502 (drm_intel_bo_gem *) bo_array[i];
1503 bo_gem->reloc_tree_size = total;
1507 for (i = 0; i < count; i++)
1508 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1513 * Return -1 if the batchbuffer should be flushed before attempting to
1514 * emit rendering referencing the buffers pointed to by bo_array.
1516 * This is required because if we try to emit a batchbuffer with relocations
1517 * to a tree of buffers that won't simultaneously fit in the aperture,
1518 * the rendering will return an error at a point where the software is not
1519 * prepared to recover from it.
1521 * However, we also want to emit the batchbuffer significantly before we reach
1522 * the limit, as a series of batchbuffers each of which references buffers
1523 * covering almost all of the aperture means that at each emit we end up
1524 * waiting to evict a buffer from the last rendering, and we get synchronous
1525 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1526 * get better parallelism.
1529 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1531 drm_intel_bufmgr_gem *bufmgr_gem =
1532 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1533 unsigned int total = 0;
1534 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1537 /* Check for fence reg constraints if necessary */
1538 if (bufmgr_gem->available_fences) {
1539 total_fences = drm_intel_gem_total_fences(bo_array, count);
1540 if (total_fences > bufmgr_gem->available_fences)
1544 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1546 if (total > threshold)
1547 total = drm_intel_gem_compute_batch_space(bo_array, count);
1549 if (total > threshold) {
1550 DBG("check_space: overflowed available aperture, "
1552 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1555 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
1556 (int)bufmgr_gem->gtt_size / 1024);
1562 * Disable buffer reuse for objects which are shared with the kernel
1563 * as scanout buffers
1566 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1568 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1570 bo_gem->reusable = 0;
1575 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1576 * for the next drm_intel_bufmgr_check_aperture_space() call.
1579 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1581 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1584 if (bo == NULL || target_bo == NULL)
1587 for (i = 0; i < bo_gem->reloc_count; i++) {
1588 if (bo_gem->reloc_target_bo[i] == target_bo)
1590 if (drm_intel_gem_bo_references(bo_gem->reloc_target_bo[i],
1599 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1600 * and manage map buffer objections.
1602 * \param fd File descriptor of the opened DRM device.
1605 drm_intel_bufmgr_gem_init(int fd, int batch_size)
1607 drm_intel_bufmgr_gem *bufmgr_gem;
1608 struct drm_i915_gem_get_aperture aperture;
1609 drm_i915_getparam_t gp;
1613 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
1614 bufmgr_gem->fd = fd;
1616 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
1621 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
1624 bufmgr_gem->gtt_size = aperture.aper_available_size;
1626 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
1628 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
1629 fprintf(stderr, "Assuming %dkB available aperture size.\n"
1630 "May lead to reduced performance or incorrect "
1632 (int)bufmgr_gem->gtt_size / 1024);
1635 gp.param = I915_PARAM_CHIPSET_ID;
1636 gp.value = &bufmgr_gem->pci_device;
1637 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1639 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
1640 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
1643 if (!IS_I965G(bufmgr_gem)) {
1644 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
1645 gp.value = &bufmgr_gem->available_fences;
1646 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1648 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
1650 fprintf(stderr, "param: %d, val: %d\n", gp.param,
1652 bufmgr_gem->available_fences = 0;
1656 /* Let's go with one relocation per every 2 dwords (but round down a bit
1657 * since a power of two will mean an extra page allocation for the reloc
1660 * Every 4 was too few for the blender benchmark.
1662 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
1664 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
1665 bufmgr_gem->bufmgr.bo_alloc_for_render =
1666 drm_intel_gem_bo_alloc_for_render;
1667 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
1668 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
1669 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
1670 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
1671 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
1672 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
1673 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
1674 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
1675 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
1676 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
1677 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
1678 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
1679 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
1680 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
1681 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
1682 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
1683 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
1684 bufmgr_gem->bufmgr.debug = 0;
1685 bufmgr_gem->bufmgr.check_aperture_space =
1686 drm_intel_gem_check_aperture_space;
1687 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
1688 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
1689 drm_intel_gem_get_pipe_from_crtc_id;
1690 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
1692 /* Initialize the linked lists for BO reuse cache. */
1693 for (i = 0, size = 4096; i < DRM_INTEL_GEM_BO_BUCKETS; i++, size *= 2) {
1694 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
1695 bufmgr_gem->cache_bucket[i].size = size;
1698 return &bufmgr_gem->bufmgr;