1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
49 #include <sys/ioctl.h>
52 #include <sys/types.h>
55 #include "libdrm_lists.h"
56 #include "intel_atomic.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
69 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
71 struct drm_intel_gem_bo_bucket {
76 /* Only cache objects up to 64MB. Bigger than that, and the rounding of the
77 * size makes many operations fail that wouldn't otherwise.
79 #define DRM_INTEL_GEM_BO_BUCKETS 14
80 typedef struct _drm_intel_bufmgr_gem {
81 drm_intel_bufmgr bufmgr;
89 struct drm_i915_gem_exec_object *exec_objects;
90 drm_intel_bo **exec_bos;
94 /** Array of lists of cached gem objects of power-of-two sizes */
95 struct drm_intel_gem_bo_bucket cache_bucket[DRM_INTEL_GEM_BO_BUCKETS];
101 } drm_intel_bufmgr_gem;
103 struct _drm_intel_bo_gem {
107 /** Boolean whether the mmap ioctl has been called for this buffer yet. */
112 * Kenel-assigned global name for this object
114 unsigned int global_name;
117 * Index of the buffer within the validation list while preparing a
118 * batchbuffer execution.
123 * Current tiling mode
125 uint32_t tiling_mode;
126 uint32_t swizzle_mode;
130 /** Array passed to the DRM containing relocation information. */
131 struct drm_i915_gem_relocation_entry *relocs;
132 /** Array of bos corresponding to relocs[i].target_handle */
133 drm_intel_bo **reloc_target_bo;
134 /** Number of entries in relocs */
136 /** Mapped address for the buffer, saved across map/unmap cycles */
138 /** GTT virtual address for the buffer, saved across map/unmap cycles */
145 * Boolean of whether this BO and its children have been included in
146 * the current drm_intel_bufmgr_check_aperture_space() total.
148 char included_in_check_aperture;
151 * Boolean of whether this buffer has been used as a relocation
152 * target and had its size accounted for, and thus can't have any
153 * further relocations added to it.
155 char used_as_reloc_target;
158 * Boolean of whether this buffer can be re-used
163 * Size in bytes of this buffer and its relocation descendents.
165 * Used to avoid costly tree walking in drm_intel_bufmgr_check_aperture in
170 * Number of potential fence registers required by this buffer and its
173 int reloc_tree_fences;
177 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count);
180 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count);
183 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t *tiling_mode,
184 uint32_t *swizzle_mode);
187 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t *tiling_mode,
191 drm_intel_gem_bo_unreference_locked(drm_intel_bo *bo);
194 drm_intel_gem_bo_unreference(drm_intel_bo *bo);
197 drm_intel_gem_bo_free(drm_intel_bo *bo);
199 static struct drm_intel_gem_bo_bucket *
200 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
205 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
206 struct drm_intel_gem_bo_bucket *bucket = &bufmgr_gem->cache_bucket[i];
207 if (bucket->size >= size) {
215 static void drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
219 for (i = 0; i < bufmgr_gem->exec_count; i++) {
220 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
221 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
223 if (bo_gem->relocs == NULL) {
224 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle, bo_gem->name);
228 for (j = 0; j < bo_gem->reloc_count; j++) {
229 drm_intel_bo *target_bo = bo_gem->reloc_target_bo[j];
230 drm_intel_bo_gem *target_gem = (drm_intel_bo_gem *)target_bo;
232 DBG("%2d: %d (%s)@0x%08llx -> %d (%s)@0x%08lx + 0x%08x\n",
234 bo_gem->gem_handle, bo_gem->name,
235 (unsigned long long)bo_gem->relocs[j].offset,
236 target_gem->gem_handle, target_gem->name, target_bo->offset,
237 bo_gem->relocs[j].delta);
243 drm_intel_gem_bo_reference(drm_intel_bo *bo)
245 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
247 assert(atomic_read(&bo_gem->refcount) > 0);
248 atomic_inc(&bo_gem->refcount);
252 * Adds the given buffer to the list of buffers to be validated (moved into the
253 * appropriate memory type) with the next batch submission.
255 * If a buffer is validated multiple times in a batch submission, it ends up
256 * with the intersection of the memory type flags and the union of the
260 drm_intel_add_validate_buffer(drm_intel_bo *bo)
262 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
263 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
266 if (bo_gem->validate_index != -1)
269 /* Extend the array of validation entries as necessary. */
270 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
271 int new_size = bufmgr_gem->exec_size * 2;
276 bufmgr_gem->exec_objects =
277 realloc(bufmgr_gem->exec_objects,
278 sizeof(*bufmgr_gem->exec_objects) * new_size);
279 bufmgr_gem->exec_bos =
280 realloc(bufmgr_gem->exec_bos,
281 sizeof(*bufmgr_gem->exec_bos) * new_size);
282 bufmgr_gem->exec_size = new_size;
285 index = bufmgr_gem->exec_count;
286 bo_gem->validate_index = index;
287 /* Fill in array entry */
288 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
289 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
290 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
291 bufmgr_gem->exec_objects[index].alignment = 0;
292 bufmgr_gem->exec_objects[index].offset = 0;
293 bufmgr_gem->exec_bos[index] = bo;
294 drm_intel_gem_bo_reference(bo);
295 bufmgr_gem->exec_count++;
299 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
303 drm_intel_setup_reloc_list(drm_intel_bo *bo)
305 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
306 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
308 bo_gem->relocs = malloc(bufmgr_gem->max_relocs *
309 sizeof(struct drm_i915_gem_relocation_entry));
310 bo_gem->reloc_target_bo = malloc(bufmgr_gem->max_relocs *
311 sizeof(drm_intel_bo *));
317 drm_intel_gem_bo_busy(drm_intel_bo *bo)
319 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
320 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
321 struct drm_i915_gem_busy busy;
324 memset(&busy, 0, sizeof(busy));
325 busy.handle = bo_gem->gem_handle;
327 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
329 return (ret == 0 && busy.busy);
333 drm_intel_gem_bo_madvise(drm_intel_bufmgr_gem *bufmgr_gem,
334 drm_intel_bo_gem *bo_gem,
337 struct drm_i915_gem_madvise madv;
339 madv.handle = bo_gem->gem_handle;
342 ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
344 return madv.retained;
347 /* drop the oldest entries that have been purged by the kernel */
349 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
350 struct drm_intel_gem_bo_bucket *bucket)
352 while (!DRMLISTEMPTY(&bucket->head)) {
353 drm_intel_bo_gem *bo_gem;
355 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, bucket->head.next, head);
356 if (drm_intel_gem_bo_madvise (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
359 DRMLISTDEL(&bo_gem->head);
360 drm_intel_gem_bo_free(&bo_gem->bo);
364 static drm_intel_bo *
365 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, const char *name,
366 unsigned long size, unsigned int alignment,
369 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
370 drm_intel_bo_gem *bo_gem;
371 unsigned int page_size = getpagesize();
373 struct drm_intel_gem_bo_bucket *bucket;
374 int alloc_from_cache;
375 unsigned long bo_size;
377 /* Round the allocated size up to a power of two number of pages. */
378 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
380 /* If we don't have caching at this size, don't actually round the
383 if (bucket == NULL) {
385 if (bo_size < page_size)
388 bo_size = bucket->size;
391 pthread_mutex_lock(&bufmgr_gem->lock);
392 /* Get a buffer out of the cache if available */
394 alloc_from_cache = 0;
395 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
397 /* Allocate new render-target BOs from the tail (MRU)
398 * of the list, as it will likely be hot in the GPU cache
399 * and in the aperture for us.
401 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, bucket->head.prev, head);
402 DRMLISTDEL(&bo_gem->head);
403 alloc_from_cache = 1;
405 /* For non-render-target BOs (where we're probably going to map it
406 * first thing in order to fill it with data), check if the
407 * last BO in the cache is unbusy, and only reuse in that case.
408 * Otherwise, allocating a new buffer is probably faster than
409 * waiting for the GPU to finish.
411 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, bucket->head.next, head);
412 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
413 alloc_from_cache = 1;
414 DRMLISTDEL(&bo_gem->head);
418 if (alloc_from_cache) {
419 if(!drm_intel_gem_bo_madvise(bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
420 drm_intel_gem_bo_free(&bo_gem->bo);
421 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem, bucket);
426 pthread_mutex_unlock(&bufmgr_gem->lock);
428 if (!alloc_from_cache) {
429 struct drm_i915_gem_create create;
431 bo_gem = calloc(1, sizeof(*bo_gem));
435 bo_gem->bo.size = bo_size;
436 memset(&create, 0, sizeof(create));
437 create.size = bo_size;
439 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CREATE, &create);
440 bo_gem->gem_handle = create.handle;
441 bo_gem->bo.handle = bo_gem->gem_handle;
446 bo_gem->bo.bufmgr = bufmgr;
450 atomic_set(&bo_gem->refcount, 1);
451 bo_gem->validate_index = -1;
452 bo_gem->reloc_tree_size = bo_gem->bo.size;
453 bo_gem->reloc_tree_fences = 0;
454 bo_gem->used_as_reloc_target = 0;
455 bo_gem->tiling_mode = I915_TILING_NONE;
456 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
457 bo_gem->reusable = 1;
459 DBG("bo_create: buf %d (%s) %ldb\n",
460 bo_gem->gem_handle, bo_gem->name, size);
465 static drm_intel_bo *
466 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, const char *name,
467 unsigned long size, unsigned int alignment)
469 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, alignment, 1);
472 static drm_intel_bo *
473 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
474 unsigned long size, unsigned int alignment)
476 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, alignment, 0);
480 * Returns a drm_intel_bo wrapping the given buffer object handle.
482 * This can be used when one application needs to pass a buffer object
486 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr, const char *name,
489 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
490 drm_intel_bo_gem *bo_gem;
492 struct drm_gem_open open_arg;
493 struct drm_i915_gem_get_tiling get_tiling;
495 bo_gem = calloc(1, sizeof(*bo_gem));
499 memset(&open_arg, 0, sizeof(open_arg));
500 open_arg.name = handle;
501 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_OPEN, &open_arg);
503 fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
504 name, handle, strerror(errno));
508 bo_gem->bo.size = open_arg.size;
509 bo_gem->bo.offset = 0;
510 bo_gem->bo.virtual = NULL;
511 bo_gem->bo.bufmgr = bufmgr;
513 atomic_set (&bo_gem->refcount, 1);
514 bo_gem->validate_index = -1;
515 bo_gem->gem_handle = open_arg.handle;
516 bo_gem->global_name = handle;
517 bo_gem->reusable = 0;
519 memset(&get_tiling, 0, sizeof(get_tiling));
520 get_tiling.handle = bo_gem->gem_handle;
521 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
523 drm_intel_gem_bo_unreference(&bo_gem->bo);
526 bo_gem->tiling_mode = get_tiling.tiling_mode;
527 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
528 if (bo_gem->tiling_mode == I915_TILING_NONE)
529 bo_gem->reloc_tree_fences = 0;
531 bo_gem->reloc_tree_fences = 1;
533 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
539 drm_intel_gem_bo_free(drm_intel_bo *bo)
541 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
542 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
543 struct drm_gem_close close;
546 if (bo_gem->mem_virtual)
547 munmap (bo_gem->mem_virtual, bo_gem->bo.size);
548 if (bo_gem->gtt_virtual)
549 munmap (bo_gem->gtt_virtual, bo_gem->bo.size);
551 free(bo_gem->reloc_target_bo);
552 free(bo_gem->relocs);
554 /* Close this object */
555 memset(&close, 0, sizeof(close));
556 close.handle = bo_gem->gem_handle;
557 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
560 "DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
561 bo_gem->gem_handle, bo_gem->name, strerror(errno));
566 /** Frees all cached buffers significantly older than @time. */
568 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
572 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
573 struct drm_intel_gem_bo_bucket *bucket = &bufmgr_gem->cache_bucket[i];
575 while (!DRMLISTEMPTY(&bucket->head)) {
576 drm_intel_bo_gem *bo_gem;
578 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, bucket->head.next, head);
579 if (time - bo_gem->free_time <= 1)
582 DRMLISTDEL(&bo_gem->head);
584 drm_intel_gem_bo_free(&bo_gem->bo);
590 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo)
592 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
593 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
594 struct drm_intel_gem_bo_bucket *bucket;
595 uint32_t tiling_mode;
597 if (bo_gem->relocs != NULL) {
600 /* Unreference all the target buffers */
601 for (i = 0; i < bo_gem->reloc_count; i++)
602 drm_intel_gem_bo_unreference_locked(bo_gem->reloc_target_bo[i]);
605 DBG("bo_unreference final: %d (%s)\n",
606 bo_gem->gem_handle, bo_gem->name);
608 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
609 /* Put the buffer into our internal cache for reuse if we can. */
610 tiling_mode = I915_TILING_NONE;
611 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
612 drm_intel_gem_bo_set_tiling(bo, &tiling_mode, 0) == 0)
614 struct timespec time;
616 clock_gettime(CLOCK_MONOTONIC, &time);
617 bo_gem->free_time = time.tv_sec;
620 bo_gem->validate_index = -1;
621 bo_gem->reloc_count = 0;
623 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
625 drm_intel_gem_bo_madvise(bufmgr_gem, bo_gem, I915_MADV_DONTNEED);
626 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
628 drm_intel_gem_bo_free(bo);
633 drm_intel_gem_bo_unreference_locked(drm_intel_bo *bo)
635 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
637 assert(atomic_read(&bo_gem->refcount) > 0);
638 if (atomic_dec_and_test (&bo_gem->refcount))
639 drm_intel_gem_bo_unreference_final(bo);
643 drm_intel_gem_bo_unreference(drm_intel_bo *bo)
645 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
647 assert(atomic_read(&bo_gem->refcount) > 0);
648 if (atomic_dec_and_test (&bo_gem->refcount)) {
649 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
650 pthread_mutex_lock(&bufmgr_gem->lock);
651 drm_intel_gem_bo_unreference_final(bo);
652 pthread_mutex_unlock(&bufmgr_gem->lock);
657 drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
659 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
660 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
661 struct drm_i915_gem_set_domain set_domain;
664 pthread_mutex_lock(&bufmgr_gem->lock);
666 /* Allow recursive mapping. Mesa may recursively map buffers with
667 * nested display loops.
669 if (!bo_gem->mem_virtual) {
670 struct drm_i915_gem_mmap mmap_arg;
672 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
674 memset(&mmap_arg, 0, sizeof(mmap_arg));
675 mmap_arg.handle = bo_gem->gem_handle;
677 mmap_arg.size = bo->size;
678 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MMAP, &mmap_arg);
680 fprintf(stderr, "%s:%d: Error mapping buffer %d (%s): %s .\n",
682 bo_gem->gem_handle, bo_gem->name, strerror(errno));
683 pthread_mutex_unlock(&bufmgr_gem->lock);
686 bo_gem->mem_virtual = (void *)(uintptr_t)mmap_arg.addr_ptr;
688 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
689 bo_gem->mem_virtual);
690 bo->virtual = bo_gem->mem_virtual;
692 set_domain.handle = bo_gem->gem_handle;
693 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
695 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
697 set_domain.write_domain = 0;
699 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN,
701 } while (ret == -1 && errno == EINTR);
703 fprintf (stderr, "%s:%d: Error setting to CPU domain %d: %s\n",
704 __FILE__, __LINE__, bo_gem->gem_handle, strerror (errno));
705 pthread_mutex_unlock(&bufmgr_gem->lock);
709 pthread_mutex_unlock(&bufmgr_gem->lock);
715 drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
717 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
718 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
719 struct drm_i915_gem_set_domain set_domain;
722 pthread_mutex_lock(&bufmgr_gem->lock);
724 /* Get a mapping of the buffer if we haven't before. */
725 if (bo_gem->gtt_virtual == NULL) {
726 struct drm_i915_gem_mmap_gtt mmap_arg;
728 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
730 memset(&mmap_arg, 0, sizeof(mmap_arg));
731 mmap_arg.handle = bo_gem->gem_handle;
733 /* Get the fake offset back... */
734 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &mmap_arg);
737 "%s:%d: Error preparing buffer map %d (%s): %s .\n",
739 bo_gem->gem_handle, bo_gem->name,
741 pthread_mutex_unlock(&bufmgr_gem->lock);
746 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
747 MAP_SHARED, bufmgr_gem->fd,
749 if (bo_gem->gtt_virtual == MAP_FAILED) {
751 "%s:%d: Error mapping buffer %d (%s): %s .\n",
753 bo_gem->gem_handle, bo_gem->name,
755 pthread_mutex_unlock(&bufmgr_gem->lock);
760 bo->virtual = bo_gem->gtt_virtual;
762 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
763 bo_gem->gtt_virtual);
765 /* Now move it to the GTT domain so that the CPU caches are flushed */
766 set_domain.handle = bo_gem->gem_handle;
767 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
768 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
770 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN,
772 } while (ret == -1 && errno == EINTR);
775 fprintf (stderr, "%s:%d: Error setting domain %d: %s\n",
776 __FILE__, __LINE__, bo_gem->gem_handle, strerror (errno));
779 pthread_mutex_unlock(&bufmgr_gem->lock);
785 drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
787 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
788 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
794 assert(bo_gem->gtt_virtual != NULL);
796 pthread_mutex_lock(&bufmgr_gem->lock);
798 pthread_mutex_unlock(&bufmgr_gem->lock);
804 drm_intel_gem_bo_unmap(drm_intel_bo *bo)
806 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
807 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
808 struct drm_i915_gem_sw_finish sw_finish;
814 assert(bo_gem->mem_virtual != NULL);
816 pthread_mutex_lock(&bufmgr_gem->lock);
818 /* Cause a flush to happen if the buffer's pinned for scanout, so the
819 * results show up in a timely manner.
821 sw_finish.handle = bo_gem->gem_handle;
823 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SW_FINISH,
825 } while (ret == -1 && errno == EINTR);
828 pthread_mutex_unlock(&bufmgr_gem->lock);
833 drm_intel_gem_bo_subdata (drm_intel_bo *bo, unsigned long offset,
834 unsigned long size, const void *data)
836 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
837 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
838 struct drm_i915_gem_pwrite pwrite;
841 memset (&pwrite, 0, sizeof (pwrite));
842 pwrite.handle = bo_gem->gem_handle;
843 pwrite.offset = offset;
845 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
847 ret = ioctl (bufmgr_gem->fd, DRM_IOCTL_I915_GEM_PWRITE, &pwrite);
848 } while (ret == -1 && errno == EINTR);
850 fprintf (stderr, "%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
852 bo_gem->gem_handle, (int) offset, (int) size,
859 drm_intel_gem_get_pipe_from_crtc_id (drm_intel_bufmgr *bufmgr, int crtc_id)
861 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
862 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
865 get_pipe_from_crtc_id.crtc_id = crtc_id;
866 ret = ioctl (bufmgr_gem->fd, DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
867 &get_pipe_from_crtc_id);
869 /* We return -1 here to signal that we don't
870 * know which pipe is associated with this crtc.
871 * This lets the caller know that this information
872 * isn't available; using the wrong pipe for
873 * vblank waiting can cause the chipset to lock up
878 return get_pipe_from_crtc_id.pipe;
882 drm_intel_gem_bo_get_subdata (drm_intel_bo *bo, unsigned long offset,
883 unsigned long size, void *data)
885 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
886 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
887 struct drm_i915_gem_pread pread;
890 memset (&pread, 0, sizeof (pread));
891 pread.handle = bo_gem->gem_handle;
892 pread.offset = offset;
894 pread.data_ptr = (uint64_t) (uintptr_t) data;
896 ret = ioctl (bufmgr_gem->fd, DRM_IOCTL_I915_GEM_PREAD, &pread);
897 } while (ret == -1 && errno == EINTR);
899 fprintf (stderr, "%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
901 bo_gem->gem_handle, (int) offset, (int) size,
907 /** Waits for all GPU rendering to the object to have completed. */
909 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
911 drm_intel_gem_bo_start_gtt_access(bo, 0);
915 * Sets the object to the GTT read and possibly write domain, used by the X
916 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
918 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
919 * can do tiled pixmaps this way.
922 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
924 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
925 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
926 struct drm_i915_gem_set_domain set_domain;
929 set_domain.handle = bo_gem->gem_handle;
930 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
931 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
933 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
934 } while (ret == -1 && errno == EINTR);
936 fprintf (stderr, "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
938 bo_gem->gem_handle, set_domain.read_domains, set_domain.write_domain,
944 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
946 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
949 free(bufmgr_gem->exec_objects);
950 free(bufmgr_gem->exec_bos);
952 pthread_mutex_destroy(&bufmgr_gem->lock);
954 /* Free any cached buffer objects we were going to reuse */
955 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
956 struct drm_intel_gem_bo_bucket *bucket = &bufmgr_gem->cache_bucket[i];
957 drm_intel_bo_gem *bo_gem;
959 while (!DRMLISTEMPTY(&bucket->head)) {
960 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, bucket->head.next, head);
961 DRMLISTDEL(&bo_gem->head);
963 drm_intel_gem_bo_free(&bo_gem->bo);
971 * Adds the target buffer to the validation list and adds the relocation
972 * to the reloc_buffer's relocation list.
974 * The relocation entry at the given offset must already contain the
975 * precomputed relocation value, because the kernel will optimize out
976 * the relocation entry write when the buffer hasn't moved from the
977 * last known offset in target_bo.
980 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
981 drm_intel_bo *target_bo, uint32_t target_offset,
982 uint32_t read_domains, uint32_t write_domain)
984 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
985 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
986 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *)target_bo;
988 pthread_mutex_lock(&bufmgr_gem->lock);
990 /* Create a new relocation list if needed */
991 if (bo_gem->relocs == NULL)
992 drm_intel_setup_reloc_list(bo);
995 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
998 assert (offset <= bo->size - 4);
999 assert ((write_domain & (write_domain-1)) == 0);
1001 /* Make sure that we're not adding a reloc to something whose size has
1002 * already been accounted for.
1004 assert(!bo_gem->used_as_reloc_target);
1005 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1006 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1008 /* Flag the target to disallow further relocations in it. */
1009 target_bo_gem->used_as_reloc_target = 1;
1011 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1012 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1013 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1014 target_bo_gem->gem_handle;
1015 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1016 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1017 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1019 bo_gem->reloc_target_bo[bo_gem->reloc_count] = target_bo;
1020 drm_intel_gem_bo_reference(target_bo);
1022 bo_gem->reloc_count++;
1024 pthread_mutex_unlock(&bufmgr_gem->lock);
1030 * Walk the tree of relocations rooted at BO and accumulate the list of
1031 * validations to be performed and update the relocation buffers with
1032 * index values into the validation list.
1035 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1037 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1040 if (bo_gem->relocs == NULL)
1043 for (i = 0; i < bo_gem->reloc_count; i++) {
1044 drm_intel_bo *target_bo = bo_gem->reloc_target_bo[i];
1046 /* Continue walking the tree depth-first. */
1047 drm_intel_gem_bo_process_reloc(target_bo);
1049 /* Add the target to the validate list */
1050 drm_intel_add_validate_buffer(target_bo);
1055 drm_intel_update_buffer_offsets (drm_intel_bufmgr_gem *bufmgr_gem)
1059 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1060 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1061 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1063 /* Update the buffer offset */
1064 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1065 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1066 bo_gem->gem_handle, bo_gem->name, bo->offset,
1067 (unsigned long long)bufmgr_gem->exec_objects[i].offset);
1068 bo->offset = bufmgr_gem->exec_objects[i].offset;
1074 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1075 drm_clip_rect_t *cliprects, int num_cliprects,
1078 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1079 struct drm_i915_gem_execbuffer execbuf;
1082 pthread_mutex_lock(&bufmgr_gem->lock);
1083 /* Update indices and set up the validate list. */
1084 drm_intel_gem_bo_process_reloc(bo);
1086 /* Add the batch buffer to the validation list. There are no relocations
1089 drm_intel_add_validate_buffer(bo);
1091 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec_objects;
1092 execbuf.buffer_count = bufmgr_gem->exec_count;
1093 execbuf.batch_start_offset = 0;
1094 execbuf.batch_len = used;
1095 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1096 execbuf.num_cliprects = num_cliprects;
1101 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_EXECBUFFER, &execbuf);
1102 } while (ret != 0 && errno == EAGAIN);
1104 if (ret != 0 && errno == ENOMEM) {
1105 fprintf(stderr, "Execbuffer fails to pin. Estimate: %u. Actual: %u. Available: %u\n",
1106 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1107 bufmgr_gem->exec_count),
1108 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1109 bufmgr_gem->exec_count),
1110 (unsigned int) bufmgr_gem->gtt_size);
1112 drm_intel_update_buffer_offsets (bufmgr_gem);
1114 if (bufmgr_gem->bufmgr.debug)
1115 drm_intel_gem_dump_validation_list(bufmgr_gem);
1117 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1118 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1119 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1121 /* Disconnect the buffer from the validate list */
1122 bo_gem->validate_index = -1;
1123 drm_intel_gem_bo_unreference_locked(bo);
1124 bufmgr_gem->exec_bos[i] = NULL;
1126 bufmgr_gem->exec_count = 0;
1127 pthread_mutex_unlock(&bufmgr_gem->lock);
1133 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1135 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1136 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1137 struct drm_i915_gem_pin pin;
1140 memset(&pin, 0, sizeof(pin));
1141 pin.handle = bo_gem->gem_handle;
1142 pin.alignment = alignment;
1145 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_PIN, &pin);
1146 } while (ret == -1 && errno == EINTR);
1151 bo->offset = pin.offset;
1156 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1158 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1159 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1160 struct drm_i915_gem_unpin unpin;
1163 memset(&unpin, 0, sizeof(unpin));
1164 unpin.handle = bo_gem->gem_handle;
1166 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1174 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t *tiling_mode,
1177 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1178 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1179 struct drm_i915_gem_set_tiling set_tiling;
1182 if (bo_gem->global_name == 0 && *tiling_mode == bo_gem->tiling_mode)
1185 /* If we're going from non-tiling to tiling, bump fence count */
1186 if (bo_gem->tiling_mode == I915_TILING_NONE)
1187 bo_gem->reloc_tree_fences++;
1189 memset(&set_tiling, 0, sizeof(set_tiling));
1190 set_tiling.handle = bo_gem->gem_handle;
1191 set_tiling.tiling_mode = *tiling_mode;
1192 set_tiling.stride = stride;
1194 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_TILING, &set_tiling);
1196 *tiling_mode = bo_gem->tiling_mode;
1199 bo_gem->tiling_mode = set_tiling.tiling_mode;
1200 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1202 /* If we're going from tiling to non-tiling, drop fence count */
1203 if (bo_gem->tiling_mode == I915_TILING_NONE)
1204 bo_gem->reloc_tree_fences--;
1206 *tiling_mode = bo_gem->tiling_mode;
1211 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t *tiling_mode,
1212 uint32_t *swizzle_mode)
1214 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1216 *tiling_mode = bo_gem->tiling_mode;
1217 *swizzle_mode = bo_gem->swizzle_mode;
1222 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t *name)
1224 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1225 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1226 struct drm_gem_flink flink;
1229 if (!bo_gem->global_name) {
1230 memset(&flink, 0, sizeof(flink));
1231 flink.handle = bo_gem->gem_handle;
1233 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1236 bo_gem->global_name = flink.name;
1237 bo_gem->reusable = 0;
1240 *name = bo_gem->global_name;
1245 * Enables unlimited caching of buffer objects for reuse.
1247 * This is potentially very memory expensive, as the cache at each bucket
1248 * size is only bounded by how many buffers of that size we've managed to have
1249 * in flight at once.
1252 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1254 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1256 bufmgr_gem->bo_reuse = 1;
1260 * Return the additional aperture space required by the tree of buffer objects
1264 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1266 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1270 if (bo == NULL || bo_gem->included_in_check_aperture)
1274 bo_gem->included_in_check_aperture = 1;
1276 for (i = 0; i < bo_gem->reloc_count; i++)
1277 total += drm_intel_gem_bo_get_aperture_space(bo_gem->reloc_target_bo[i]);
1283 * Count the number of buffers in this list that need a fence reg
1285 * If the count is greater than the number of available regs, we'll have
1286 * to ask the caller to resubmit a batch with fewer tiled buffers.
1288 * This function over-counts if the same buffer is used multiple times.
1291 drm_intel_gem_total_fences(drm_intel_bo **bo_array, int count)
1294 unsigned int total = 0;
1296 for (i = 0; i < count; i++) {
1297 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo_array[i];
1302 total += bo_gem->reloc_tree_fences;
1308 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1309 * for the next drm_intel_bufmgr_check_aperture_space() call.
1312 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1314 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1317 if (bo == NULL || !bo_gem->included_in_check_aperture)
1320 bo_gem->included_in_check_aperture = 0;
1322 for (i = 0; i < bo_gem->reloc_count; i++)
1323 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->reloc_target_bo[i]);
1327 * Return a conservative estimate for the amount of aperture required
1328 * for a collection of buffers. This may double-count some buffers.
1331 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1334 unsigned int total = 0;
1336 for (i = 0; i < count; i++) {
1337 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo_array[i];
1339 total += bo_gem->reloc_tree_size;
1345 * Return the amount of aperture needed for a collection of buffers.
1346 * This avoids double counting any buffers, at the cost of looking
1347 * at every buffer in the set.
1350 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1353 unsigned int total = 0;
1355 for (i = 0; i < count; i++) {
1356 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1357 /* For the first buffer object in the array, we get an accurate count
1358 * back for its reloc_tree size (since nothing had been flagged as
1359 * being counted yet). We can save that value out as a more
1360 * conservative reloc_tree_size that avoids double-counting target
1361 * buffers. Since the first buffer happens to usually be the batch
1362 * buffer in our callers, this can pull us back from doing the tree
1363 * walk on every new batch emit.
1366 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo_array[i];
1367 bo_gem->reloc_tree_size = total;
1371 for (i = 0; i < count; i++)
1372 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1377 * Return -1 if the batchbuffer should be flushed before attempting to
1378 * emit rendering referencing the buffers pointed to by bo_array.
1380 * This is required because if we try to emit a batchbuffer with relocations
1381 * to a tree of buffers that won't simultaneously fit in the aperture,
1382 * the rendering will return an error at a point where the software is not
1383 * prepared to recover from it.
1385 * However, we also want to emit the batchbuffer significantly before we reach
1386 * the limit, as a series of batchbuffers each of which references buffers
1387 * covering almost all of the aperture means that at each emit we end up
1388 * waiting to evict a buffer from the last rendering, and we get synchronous
1389 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1390 * get better parallelism.
1393 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1395 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo_array[0]->bufmgr;
1396 unsigned int total = 0;
1397 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1400 /* Check for fence reg constraints if necessary */
1401 if (bufmgr_gem->available_fences) {
1402 total_fences = drm_intel_gem_total_fences(bo_array, count);
1403 if (total_fences > bufmgr_gem->available_fences)
1407 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1409 if (total > threshold)
1410 total = drm_intel_gem_compute_batch_space(bo_array, count);
1412 if (total > threshold) {
1413 DBG("check_space: overflowed available aperture, %dkb vs %dkb\n",
1414 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1417 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024 ,
1418 (int)bufmgr_gem->gtt_size / 1024);
1424 * Disable buffer reuse for objects which are shared with the kernel
1425 * as scanout buffers
1428 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1430 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1432 bo_gem->reusable = 0;
1437 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1438 * for the next drm_intel_bufmgr_check_aperture_space() call.
1441 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1443 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1446 if (bo == NULL || target_bo == NULL)
1449 for (i = 0; i < bo_gem->reloc_count; i++) {
1450 if (bo_gem->reloc_target_bo[i] == target_bo)
1452 if (drm_intel_gem_bo_references(bo_gem->reloc_target_bo[i], target_bo))
1460 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1461 * and manage map buffer objections.
1463 * \param fd File descriptor of the opened DRM device.
1466 drm_intel_bufmgr_gem_init(int fd, int batch_size)
1468 drm_intel_bufmgr_gem *bufmgr_gem;
1469 struct drm_i915_gem_get_aperture aperture;
1470 drm_i915_getparam_t gp;
1474 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
1475 bufmgr_gem->fd = fd;
1477 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
1482 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
1485 bufmgr_gem->gtt_size = aperture.aper_available_size;
1487 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
1489 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
1490 fprintf(stderr, "Assuming %dkB available aperture size.\n"
1491 "May lead to reduced performance or incorrect rendering.\n",
1492 (int)bufmgr_gem->gtt_size / 1024);
1495 gp.param = I915_PARAM_CHIPSET_ID;
1496 gp.value = &bufmgr_gem->pci_device;
1497 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1499 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
1500 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
1503 if (!IS_I965G(bufmgr_gem)) {
1504 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
1505 gp.value = &bufmgr_gem->available_fences;
1506 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1508 fprintf(stderr, "get fences failed: %d [%d]\n", ret, errno);
1509 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
1510 bufmgr_gem->available_fences = 0;
1514 /* Let's go with one relocation per every 2 dwords (but round down a bit
1515 * since a power of two will mean an extra page allocation for the reloc
1518 * Every 4 was too few for the blender benchmark.
1520 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
1522 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
1523 bufmgr_gem->bufmgr.bo_alloc_for_render = drm_intel_gem_bo_alloc_for_render;
1524 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
1525 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
1526 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
1527 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
1528 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
1529 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
1530 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
1531 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
1532 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
1533 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
1534 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
1535 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
1536 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
1537 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
1538 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
1539 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
1540 bufmgr_gem->bufmgr.debug = 0;
1541 bufmgr_gem->bufmgr.check_aperture_space = drm_intel_gem_check_aperture_space;
1542 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
1543 bufmgr_gem->bufmgr.get_pipe_from_crtc_id = drm_intel_gem_get_pipe_from_crtc_id;
1544 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
1546 /* Initialize the linked lists for BO reuse cache. */
1547 for (i = 0, size = 4096; i < DRM_INTEL_GEM_BO_BUCKETS; i++, size *= 2) {
1548 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
1549 bufmgr_gem->cache_bucket[i].size = size;
1552 return &bufmgr_gem->bufmgr;