2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 * @file intel_bufmgr.h
31 * Public definitions of Intel-specific bufmgr functions.
34 #ifndef INTEL_BUFMGR_H
35 #define INTEL_BUFMGR_H
39 typedef struct _drm_intel_bufmgr drm_intel_bufmgr;
40 typedef struct _drm_intel_bo drm_intel_bo;
42 struct _drm_intel_bo {
44 * Size in bytes of the buffer object.
46 * The size may be larger than the size originally requested for the
47 * allocation, such as being aligned to page size.
51 * Card virtual address (offset from the beginning of the aperture) for the
52 * object. Only valid while validated.
56 * Virtual address for accessing the buffer data. Only valid while mapped.
60 /** Buffer manager context associated with this buffer object */
61 drm_intel_bufmgr *bufmgr;
64 drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
65 unsigned long size, unsigned int alignment);
66 void drm_intel_bo_reference(drm_intel_bo *bo);
67 void drm_intel_bo_unreference(drm_intel_bo *bo);
68 int drm_intel_bo_map(drm_intel_bo *bo, int write_enable);
69 int drm_intel_bo_unmap(drm_intel_bo *bo);
71 int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
72 unsigned long size, const void *data);
73 int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
74 unsigned long size, void *data);
75 void drm_intel_bo_wait_rendering(drm_intel_bo *bo);
77 void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug);
78 void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr);
79 int drm_intel_bo_exec(drm_intel_bo *bo, int used,
80 drm_clip_rect_t *cliprects, int num_cliprects,
82 int drm_intel_bufmgr_check_aperture_space(drm_intel_bo **bo_array, int count);
84 int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
85 drm_intel_bo *target_bo, uint32_t target_offset,
86 uint32_t read_domains, uint32_t write_domain);
87 int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment);
88 int drm_intel_bo_unpin(drm_intel_bo *bo);
89 int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t *tiling_mode,
91 int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t *tiling_mode,
92 uint32_t *swizzle_mode);
93 int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t *name);
95 /* drm_intel_bufmgr_gem.c */
96 drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size);
97 drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
100 void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr);
102 /* drm_intel_bufmgr_fake.c */
103 drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd,
104 unsigned long low_offset,
107 volatile unsigned int *last_dispatch);
108 void drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr,
109 volatile unsigned int *last_dispatch);
110 void drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr,
111 int (*exec)(drm_intel_bo *bo,
115 void drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr,
116 unsigned int (*emit)(void *priv),
117 void (*wait)(unsigned int fence,
120 drm_intel_bo *drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr,
122 unsigned long offset, unsigned long size,
124 void drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo,
125 void (*invalidate_cb)(drm_intel_bo *bo,
129 void drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr);
130 void drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr);
132 /** @{ Compatibility defines to keep old code building despite the symbol rename
133 * from dri_* to drm_intel_*
135 #define dri_bo drm_intel_bo
136 #define dri_bufmgr drm_intel_bufmgr
137 #define dri_bo_alloc drm_intel_bo_alloc
138 #define dri_bo_reference drm_intel_bo_reference
139 #define dri_bo_unreference drm_intel_bo_unreference
140 #define dri_bo_map drm_intel_bo_map
141 #define dri_bo_unmap drm_intel_bo_unmap
142 #define dri_bo_subdata drm_intel_bo_subdata
143 #define dri_bo_get_subdata drm_intel_bo_get_subdata
144 #define dri_bo_wait_rendering drm_intel_bo_wait_rendering
145 #define dri_bufmgr_set_debug drm_intel_bufmgr_set_debug
146 #define dri_bufmgr_destroy drm_intel_bufmgr_destroy
147 #define dri_bo_exec drm_intel_bo_exec
148 #define dri_bufmgr_check_aperture_space drm_intel_bufmgr_check_aperture_space
149 #define dri_bo_emit_reloc(reloc_bo, read, write, target_offset, \
150 reloc_offset, target_bo) \
151 drm_intel_bo_emit_reloc(reloc_bo, reloc_offset, \
152 target_bo, target_offset, \
154 #define dri_bo_pin drm_intel_bo_pin
155 #define dri_bo_unpin drm_intel_bo_unpin
156 #define dri_bo_get_tiling drm_intel_bo_get_tiling
157 #define dri_bo_set_tiling(bo, mode) drm_intel_bo_set_tiling(bo, mode, 0)
158 #define dri_bo_flink drm_intel_bo_flink
159 #define intel_bufmgr_gem_init drm_intel_bufmgr_gem_init
160 #define intel_bo_gem_create_from_name drm_intel_bo_gem_create_from_name
161 #define intel_bufmgr_gem_enable_reuse drm_intel_bufmgr_gem_enable_reuse
162 #define intel_bufmgr_fake_init drm_intel_bufmgr_fake_init
163 #define intel_bufmgr_fake_set_last_dispatch drm_intel_bufmgr_fake_set_last_dispatch
164 #define intel_bufmgr_fake_set_exec_callback drm_intel_bufmgr_fake_set_exec_callback
165 #define intel_bufmgr_fake_set_fence_callback drm_intel_bufmgr_fake_set_fence_callback
166 #define intel_bo_fake_alloc_static drm_intel_bo_fake_alloc_static
167 #define intel_bo_fake_disable_backing_store drm_intel_bo_fake_disable_backing_store
168 #define intel_bufmgr_fake_contended_lock_take drm_intel_bufmgr_fake_contended_lock_take
169 #define intel_bufmgr_fake_evict_all drm_intel_bufmgr_fake_evict_all
173 #endif /* INTEL_BUFMGR_H */