lib_blackfin/cache.c

   1 /*
   2  * U-boot - cache.c
   3  *
   4  * Copyright (c) 2005-2008 Analog Devices Inc.
   5  *
   6  * (C) Copyright 2000-2004
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * Licensed under the GPL-2 or later.
  10  */
  11
  12 #include <common.h>
  13 #include <asm/blackfin.h>
  14 #include <asm/mach-common/bits/mpu.h>
  15
  16 void flush_cache(unsigned long addr, unsigned long size)
  17 {
  18         void *start_addr, *end_addr;
  19         int istatus, dstatus;
  20
  21         /* no need to flush stuff in on chip memory (L1/L2/etc...) */
  22         if (addr >= 0xE0000000)
  23                 return;
  24
  25         start_addr = (void *)addr;
  26         end_addr = (void *)(addr + size);
  27         istatus = icache_status();
  28         dstatus = dcache_status();
  29
  30         if (istatus) {
  31                 if (dstatus)
  32                         blackfin_icache_dcache_flush_range(start_addr, end_addr);
  33                 else
  34                         blackfin_icache_flush_range(start_addr, end_addr);
  35         } else if (dstatus)
  36                 blackfin_dcache_flush_range(start_addr, end_addr);
  37 }
  38
  39 void icache_enable(void)
  40 {
  41         bfin_write_IMEM_CONTROL(IMC | ENICPLB);
  42         SSYNC();
  43 }
  44
  45 void icache_disable(void)
  46 {
  47         bfin_write_IMEM_CONTROL(0);
  48         SSYNC();
  49 }
  50
  51 int icache_status(void)
  52 {
  53         return bfin_read_IMEM_CONTROL() & IMC;
  54 }
  55
  56 void dcache_enable(void)
  57 {
  58         bfin_write_DMEM_CONTROL(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
  59         SSYNC();
  60 }
  61
  62 void dcache_disable(void)
  63 {
  64         bfin_write_DMEM_CONTROL(0);
  65         SSYNC();
  66 }
  67
  68 int dcache_status(void)
  69 {
  70         return bfin_read_DMEM_CONTROL() & ACACHE_BCACHE;
  71 }