packaging: only on x86* arch
[platform/upstream/intel-gpu-tools.git] / lib / rendercopy_i830.c
1 #include <stdlib.h>
2 #include <sys/ioctl.h>
3 #include <stdio.h>
4 #include <string.h>
5 #include <assert.h>
6 #include <fcntl.h>
7 #include <inttypes.h>
8 #include <errno.h>
9 #include <sys/stat.h>
10 #include <sys/time.h>
11 #include "drm.h"
12 #include "i915_drm.h"
13 #include "drmtest.h"
14 #include "intel_bufmgr.h"
15 #include "intel_batchbuffer.h"
16 #include "intel_io.h"
17
18 #include "i830_reg.h"
19 #include "rendercopy.h"
20
21 #define TB0C_LAST_STAGE (1 << 31)
22 #define TB0C_RESULT_SCALE_1X            (0 << 29)
23 #define TB0C_RESULT_SCALE_2X            (1 << 29)
24 #define TB0C_RESULT_SCALE_4X            (2 << 29)
25 #define TB0C_OP_ARG1                    (1 << 25)
26 #define TB0C_OP_MODULE                  (3 << 25)
27 #define TB0C_OUTPUT_WRITE_CURRENT       (0 << 24)
28 #define TB0C_OUTPUT_WRITE_ACCUM         (1 << 24)
29 #define TB0C_ARG3_REPLICATE_ALPHA       (1<<23)
30 #define TB0C_ARG3_INVERT                (1<<22)
31 #define TB0C_ARG3_SEL_XXX
32 #define TB0C_ARG2_REPLICATE_ALPHA       (1<<17)
33 #define TB0C_ARG2_INVERT                (1<<16)
34 #define TB0C_ARG2_SEL_ONE               (0 << 12)
35 #define TB0C_ARG2_SEL_FACTOR            (1 << 12)
36 #define TB0C_ARG2_SEL_TEXEL0            (6 << 12)
37 #define TB0C_ARG2_SEL_TEXEL1            (7 << 12)
38 #define TB0C_ARG2_SEL_TEXEL2            (8 << 12)
39 #define TB0C_ARG2_SEL_TEXEL3            (9 << 12)
40 #define TB0C_ARG1_REPLICATE_ALPHA       (1<<11)
41 #define TB0C_ARG1_INVERT                (1<<10)
42 #define TB0C_ARG1_SEL_ONE               (0 << 6)
43 #define TB0C_ARG1_SEL_TEXEL0            (6 << 6)
44 #define TB0C_ARG1_SEL_TEXEL1            (7 << 6)
45 #define TB0C_ARG1_SEL_TEXEL2            (8 << 6)
46 #define TB0C_ARG1_SEL_TEXEL3            (9 << 6)
47 #define TB0C_ARG0_REPLICATE_ALPHA       (1<<5)
48 #define TB0C_ARG0_SEL_XXX
49
50 #define TB0A_CTR_STAGE_ENABLE           (1<<31)
51 #define TB0A_RESULT_SCALE_1X            (0 << 29)
52 #define TB0A_RESULT_SCALE_2X            (1 << 29)
53 #define TB0A_RESULT_SCALE_4X            (2 << 29)
54 #define TB0A_OP_ARG1                    (1 << 25)
55 #define TB0A_OP_MODULE                  (3 << 25)
56 #define TB0A_OUTPUT_WRITE_CURRENT       (0<<24)
57 #define TB0A_OUTPUT_WRITE_ACCUM         (1<<24)
58 #define TB0A_CTR_STAGE_SEL_BITS_XXX
59 #define TB0A_ARG3_SEL_XXX
60 #define TB0A_ARG3_INVERT                (1<<17)
61 #define TB0A_ARG2_INVERT                (1<<16)
62 #define TB0A_ARG2_SEL_ONE               (0 << 12)
63 #define TB0A_ARG2_SEL_TEXEL0            (6 << 12)
64 #define TB0A_ARG2_SEL_TEXEL1            (7 << 12)
65 #define TB0A_ARG2_SEL_TEXEL2            (8 << 12)
66 #define TB0A_ARG2_SEL_TEXEL3            (9 << 12)
67 #define TB0A_ARG1_INVERT                (1<<10)
68 #define TB0A_ARG1_SEL_ONE               (0 << 6)
69 #define TB0A_ARG1_SEL_TEXEL0            (6 << 6)
70 #define TB0A_ARG1_SEL_TEXEL1            (7 << 6)
71 #define TB0A_ARG1_SEL_TEXEL2            (8 << 6)
72 #define TB0A_ARG1_SEL_TEXEL3            (9 << 6)
73
74
75 static void gen2_emit_invariant(struct intel_batchbuffer *batch)
76 {
77         int i;
78
79         for (i = 0; i < 4; i++) {
80                 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(i));
81                 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD | MAP_UNIT(i) |
82                           DISABLE_TEX_STREAM_BUMP |
83                           ENABLE_TEX_STREAM_COORD_SET | TEX_STREAM_COORD_SET(i) |
84                           ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(i));
85                 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
86                 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(i));
87         }
88
89         OUT_BATCH(_3DSTATE_MAP_COORD_SETBIND_CMD);
90         OUT_BATCH(TEXBIND_SET3(TEXCOORDSRC_VTXSET_3) |
91                   TEXBIND_SET2(TEXCOORDSRC_VTXSET_2) |
92                   TEXBIND_SET1(TEXCOORDSRC_VTXSET_1) |
93                   TEXBIND_SET0(TEXCOORDSRC_VTXSET_0));
94
95         OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
96
97         OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM);
98         OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE);
99
100         OUT_BATCH(_3DSTATE_W_STATE_CMD);
101         OUT_BATCH(MAGIC_W_STATE_DWORD1);
102         OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
103
104         OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD |
105                   DISABLE_INDPT_ALPHA_BLEND |
106                   ENABLE_ALPHA_BLENDFUNC | ABLENDFUNC_ADD);
107
108         OUT_BATCH(_3DSTATE_CONST_BLEND_COLOR_CMD);
109         OUT_BATCH(0);
110
111         OUT_BATCH(_3DSTATE_MODES_1_CMD |
112                   ENABLE_COLR_BLND_FUNC | BLENDFUNC_ADD |
113                   ENABLE_SRC_BLND_FACTOR | SRC_BLND_FACT(BLENDFACTOR_ONE) |
114                   ENABLE_DST_BLND_FACTOR | DST_BLND_FACT(BLENDFACTOR_ZERO));
115
116         OUT_BATCH(_3DSTATE_ENABLES_1_CMD |
117                   DISABLE_LOGIC_OP |
118                   DISABLE_STENCIL_TEST |
119                   DISABLE_DEPTH_BIAS |
120                   DISABLE_SPEC_ADD |
121                   DISABLE_FOG |
122                   DISABLE_ALPHA_TEST |
123                   DISABLE_DEPTH_TEST |
124                   ENABLE_COLOR_BLEND);
125
126         OUT_BATCH(_3DSTATE_ENABLES_2_CMD |
127                   DISABLE_STENCIL_WRITE |
128                   DISABLE_DITHER |
129                   DISABLE_DEPTH_WRITE |
130                   ENABLE_COLOR_MASK |
131                   ENABLE_COLOR_WRITE |
132                   ENABLE_TEX_CACHE);
133 }
134
135 static void gen2_emit_target(struct intel_batchbuffer *batch,
136                              struct igt_buf *dst)
137 {
138         uint32_t tiling;
139
140         tiling = 0;
141         if (dst->tiling != I915_TILING_NONE)
142                 tiling = BUF_3D_TILED_SURFACE;
143         if (dst->tiling == I915_TILING_Y)
144                 tiling |= BUF_3D_TILE_WALK_Y;
145
146         OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
147         OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling | BUF_3D_PITCH(dst->stride));
148         OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
149
150         OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
151         OUT_BATCH(COLR_BUF_ARGB8888 |
152                   DSTORG_HORT_BIAS(0x8) |
153                   DSTORG_VERT_BIAS(0x8));
154
155         OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
156         OUT_BATCH(0);
157         OUT_BATCH(0);           /* ymin, xmin */
158         OUT_BATCH(DRAW_YMAX(igt_buf_height(dst) - 1) |
159                   DRAW_XMAX(igt_buf_width(dst) - 1));
160         OUT_BATCH(0);           /* yorig, xorig */
161 }
162
163 static void gen2_emit_texture(struct intel_batchbuffer *batch,
164                               struct igt_buf *src,
165                               int unit)
166 {
167         uint32_t tiling;
168
169         tiling = 0;
170         if (src->tiling != I915_TILING_NONE)
171                 tiling = TM0S1_TILED_SURFACE;
172         if (src->tiling == I915_TILING_Y)
173                 tiling |= TM0S1_TILE_WALK;
174
175         OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 | LOAD_TEXTURE_MAP(unit) | 4);
176         OUT_RELOC(src->bo, I915_GEM_DOMAIN_SAMPLER, 0, 0);
177         OUT_BATCH((igt_buf_height(src) - 1) << TM0S1_HEIGHT_SHIFT |
178                   (igt_buf_width(src) - 1) << TM0S1_WIDTH_SHIFT |
179                   MAPSURF_32BIT | MT_32BIT_ARGB8888 | tiling);
180         OUT_BATCH((src->stride / 4 - 1) << TM0S2_PITCH_SHIFT | TM0S2_MAP_2D);
181         OUT_BATCH(FILTER_NEAREST << TM0S3_MAG_FILTER_SHIFT |
182                   FILTER_NEAREST << TM0S3_MIN_FILTER_SHIFT |
183                   MIPFILTER_NONE << TM0S3_MIP_FILTER_SHIFT);
184         OUT_BATCH(0);   /* default color */
185
186         OUT_BATCH(_3DSTATE_MAP_COORD_SET_CMD | TEXCOORD_SET(unit) |
187                   ENABLE_TEXCOORD_PARAMS | TEXCOORDS_ARE_NORMAL |
188                   TEXCOORDTYPE_CARTESIAN |
189                   ENABLE_ADDR_V_CNTL | TEXCOORD_ADDR_V_MODE(TEXCOORDMODE_CLAMP_BORDER) |
190                   ENABLE_ADDR_U_CNTL | TEXCOORD_ADDR_U_MODE(TEXCOORDMODE_CLAMP_BORDER));
191 }
192
193 static void gen2_emit_copy_pipeline(struct intel_batchbuffer *batch)
194 {
195         OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD | DISABLE_INDPT_ALPHA_BLEND);
196         OUT_BATCH(_3DSTATE_ENABLES_1_CMD | DISABLE_LOGIC_OP |
197                   DISABLE_STENCIL_TEST | DISABLE_DEPTH_BIAS |
198                   DISABLE_SPEC_ADD | DISABLE_FOG | DISABLE_ALPHA_TEST |
199                   DISABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
200
201         OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
202                   LOAD_TEXTURE_BLEND_STAGE(0) | 1);
203         OUT_BATCH(TB0C_LAST_STAGE | TB0C_RESULT_SCALE_1X |
204                   TB0C_OUTPUT_WRITE_CURRENT |
205                   TB0C_OP_ARG1 | TB0C_ARG1_SEL_TEXEL0);
206         OUT_BATCH(TB0A_RESULT_SCALE_1X | TB0A_OUTPUT_WRITE_CURRENT |
207                   TB0A_OP_ARG1 | TB0A_ARG1_SEL_TEXEL0);
208 }
209
210 void gen2_render_copyfunc(struct intel_batchbuffer *batch,
211                           drm_intel_context *context,
212                           struct igt_buf *src, unsigned src_x, unsigned src_y,
213                           unsigned width, unsigned height,
214                           struct igt_buf *dst, unsigned dst_x, unsigned dst_y)
215 {
216         gen2_emit_invariant(batch);
217         gen2_emit_copy_pipeline(batch);
218
219         gen2_emit_target(batch, dst);
220         gen2_emit_texture(batch, src, 0);
221
222         OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
223                   I1_LOAD_S(2) | I1_LOAD_S(3) | I1_LOAD_S(8) | 2);
224         OUT_BATCH(1<<12);
225         OUT_BATCH(S3_CULLMODE_NONE | S3_VERTEXHAS_XY);
226         OUT_BATCH(S8_ENABLE_COLOR_BUFFER_WRITE);
227
228         OUT_BATCH(_3DSTATE_VERTEX_FORMAT_2_CMD | TEXCOORDFMT_2D << 0);
229
230         OUT_BATCH(PRIM3D_INLINE | PRIM3D_RECTLIST | (3*4 -1));
231         emit_vertex(batch, dst_x + width);
232         emit_vertex(batch, dst_y + height);
233         emit_vertex_normalized(batch, src_x + width, igt_buf_width(src));
234         emit_vertex_normalized(batch, src_y + height, igt_buf_height(src));
235
236         emit_vertex(batch, dst_x);
237         emit_vertex(batch, dst_y + height);
238         emit_vertex_normalized(batch, src_x, igt_buf_width(src));
239         emit_vertex_normalized(batch, src_y + height, igt_buf_height(src));
240
241         emit_vertex(batch, dst_x);
242         emit_vertex(batch, dst_y);
243         emit_vertex_normalized(batch, src_x, igt_buf_width(src));
244         emit_vertex_normalized(batch, src_y, igt_buf_height(src));
245
246         intel_batchbuffer_flush(batch);
247 }