lib/rendercopy_i830.c

   1 #include <stdlib.h>
   2 #include <sys/ioctl.h>
   3 #include <stdio.h>
   4 #include <string.h>
   5 #include <assert.h>
   6 #include <fcntl.h>
   7 #include <inttypes.h>
   8 #include <errno.h>
   9 #include <sys/stat.h>
  10 #include <sys/time.h>
  11 #include <getopt.h>
  12 #include "drm.h"
  13 #include "i915_drm.h"
  14 #include "drmtest.h"
  15 #include "intel_bufmgr.h"
  16 #include "intel_batchbuffer.h"
  17 #include "intel_gpu_tools.h"
  18
  19 #include "i830_reg.h"
  20 #include "rendercopy.h"
  21
  22 #define TB0C_LAST_STAGE (1 << 31)
  23 #define TB0C_RESULT_SCALE_1X            (0 << 29)
  24 #define TB0C_RESULT_SCALE_2X            (1 << 29)
  25 #define TB0C_RESULT_SCALE_4X            (2 << 29)
  26 #define TB0C_OP_ARG1                    (1 << 25)
  27 #define TB0C_OP_MODULE                  (3 << 25)
  28 #define TB0C_OUTPUT_WRITE_CURRENT       (0 << 24)
  29 #define TB0C_OUTPUT_WRITE_ACCUM         (1 << 24)
  30 #define TB0C_ARG3_REPLICATE_ALPHA       (1<<23)
  31 #define TB0C_ARG3_INVERT                (1<<22)
  32 #define TB0C_ARG3_SEL_XXX
  33 #define TB0C_ARG2_REPLICATE_ALPHA       (1<<17)
  34 #define TB0C_ARG2_INVERT                (1<<16)
  35 #define TB0C_ARG2_SEL_ONE               (0 << 12)
  36 #define TB0C_ARG2_SEL_FACTOR            (1 << 12)
  37 #define TB0C_ARG2_SEL_TEXEL0            (6 << 12)
  38 #define TB0C_ARG2_SEL_TEXEL1            (7 << 12)
  39 #define TB0C_ARG2_SEL_TEXEL2            (8 << 12)
  40 #define TB0C_ARG2_SEL_TEXEL3            (9 << 12)
  41 #define TB0C_ARG1_REPLICATE_ALPHA       (1<<11)
  42 #define TB0C_ARG1_INVERT                (1<<10)
  43 #define TB0C_ARG1_SEL_ONE               (0 << 6)
  44 #define TB0C_ARG1_SEL_TEXEL0            (6 << 6)
  45 #define TB0C_ARG1_SEL_TEXEL1            (7 << 6)
  46 #define TB0C_ARG1_SEL_TEXEL2            (8 << 6)
  47 #define TB0C_ARG1_SEL_TEXEL3            (9 << 6)
  48 #define TB0C_ARG0_REPLICATE_ALPHA       (1<<5)
  49 #define TB0C_ARG0_SEL_XXX
  50
  51 #define TB0A_CTR_STAGE_ENABLE           (1<<31)
  52 #define TB0A_RESULT_SCALE_1X            (0 << 29)
  53 #define TB0A_RESULT_SCALE_2X            (1 << 29)
  54 #define TB0A_RESULT_SCALE_4X            (2 << 29)
  55 #define TB0A_OP_ARG1                    (1 << 25)
  56 #define TB0A_OP_MODULE                  (3 << 25)
  57 #define TB0A_OUTPUT_WRITE_CURRENT       (0<<24)
  58 #define TB0A_OUTPUT_WRITE_ACCUM         (1<<24)
  59 #define TB0A_CTR_STAGE_SEL_BITS_XXX
  60 #define TB0A_ARG3_SEL_XXX
  61 #define TB0A_ARG3_INVERT                (1<<17)
  62 #define TB0A_ARG2_INVERT                (1<<16)
  63 #define TB0A_ARG2_SEL_ONE               (0 << 12)
  64 #define TB0A_ARG2_SEL_TEXEL0            (6 << 12)
  65 #define TB0A_ARG2_SEL_TEXEL1            (7 << 12)
  66 #define TB0A_ARG2_SEL_TEXEL2            (8 << 12)
  67 #define TB0A_ARG2_SEL_TEXEL3            (9 << 12)
  68 #define TB0A_ARG1_INVERT                (1<<10)
  69 #define TB0A_ARG1_SEL_ONE               (0 << 6)
  70 #define TB0A_ARG1_SEL_TEXEL0            (6 << 6)
  71 #define TB0A_ARG1_SEL_TEXEL1            (7 << 6)
  72 #define TB0A_ARG1_SEL_TEXEL2            (8 << 6)
  73 #define TB0A_ARG1_SEL_TEXEL3            (9 << 6)
  74
  75
  76 static void gen2_emit_invariant(struct intel_batchbuffer *batch)
  77 {
  78         int i;
  79
  80         for (i = 0; i < 4; i++) {
  81                 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(i));
  82                 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD | MAP_UNIT(i) |
  83                           DISABLE_TEX_STREAM_BUMP |
  84                           ENABLE_TEX_STREAM_COORD_SET | TEX_STREAM_COORD_SET(i) |
  85                           ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(i));
  86                 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
  87                 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(i));
  88         }
  89
  90         OUT_BATCH(_3DSTATE_MAP_COORD_SETBIND_CMD);
  91         OUT_BATCH(TEXBIND_SET3(TEXCOORDSRC_VTXSET_3) |
  92                   TEXBIND_SET2(TEXCOORDSRC_VTXSET_2) |
  93                   TEXBIND_SET1(TEXCOORDSRC_VTXSET_1) |
  94                   TEXBIND_SET0(TEXCOORDSRC_VTXSET_0));
  95
  96         OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
  97
  98         OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM);
  99         OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE);
 100
 101         OUT_BATCH(_3DSTATE_W_STATE_CMD);
 102         OUT_BATCH(MAGIC_W_STATE_DWORD1);
 103         OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
 104
 105         OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD |
 106                   DISABLE_INDPT_ALPHA_BLEND |
 107                   ENABLE_ALPHA_BLENDFUNC | ABLENDFUNC_ADD);
 108
 109         OUT_BATCH(_3DSTATE_CONST_BLEND_COLOR_CMD);
 110         OUT_BATCH(0);
 111
 112         OUT_BATCH(_3DSTATE_MODES_1_CMD |
 113                   ENABLE_COLR_BLND_FUNC | BLENDFUNC_ADD |
 114                   ENABLE_SRC_BLND_FACTOR | SRC_BLND_FACT(BLENDFACTOR_ONE) |
 115                   ENABLE_DST_BLND_FACTOR | DST_BLND_FACT(BLENDFACTOR_ZERO));
 116
 117         OUT_BATCH(_3DSTATE_ENABLES_1_CMD |
 118                   DISABLE_LOGIC_OP |
 119                   DISABLE_STENCIL_TEST |
 120                   DISABLE_DEPTH_BIAS |
 121                   DISABLE_SPEC_ADD |
 122                   DISABLE_FOG |
 123                   DISABLE_ALPHA_TEST |
 124                   DISABLE_DEPTH_TEST |
 125                   ENABLE_COLOR_BLEND);
 126
 127         OUT_BATCH(_3DSTATE_ENABLES_2_CMD |
 128                   DISABLE_STENCIL_WRITE |
 129                   DISABLE_DITHER |
 130                   DISABLE_DEPTH_WRITE |
 131                   ENABLE_COLOR_MASK |
 132                   ENABLE_COLOR_WRITE |
 133                   ENABLE_TEX_CACHE);
 134 }
 135
 136 static void gen2_emit_target(struct intel_batchbuffer *batch,
 137                              struct scratch_buf *dst)
 138 {
 139         uint32_t tiling;
 140
 141         tiling = 0;
 142         if (dst->tiling != I915_TILING_NONE)
 143                 tiling = BUF_3D_TILED_SURFACE;
 144         if (dst->tiling == I915_TILING_Y)
 145                 tiling |= BUF_3D_TILE_WALK_Y;
 146
 147         OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
 148         OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling | BUF_3D_PITCH(dst->stride));
 149         OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
 150
 151         OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
 152         OUT_BATCH(COLR_BUF_ARGB8888 |
 153                   DSTORG_HORT_BIAS(0x8) |
 154                   DSTORG_VERT_BIAS(0x8));
 155
 156         OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
 157         OUT_BATCH(0);
 158         OUT_BATCH(0);           /* ymin, xmin */
 159         OUT_BATCH(DRAW_YMAX(buf_height(dst) - 1) |
 160                   DRAW_XMAX(buf_width(dst) - 1));
 161         OUT_BATCH(0);           /* yorig, xorig */
 162 }
 163
 164 static void gen2_emit_texture(struct intel_batchbuffer *batch,
 165                               struct scratch_buf *src,
 166                               int unit)
 167 {
 168         uint32_t tiling;
 169
 170         tiling = 0;
 171         if (src->tiling != I915_TILING_NONE)
 172                 tiling = TM0S1_TILED_SURFACE;
 173         if (src->tiling == I915_TILING_Y)
 174                 tiling |= TM0S1_TILE_WALK;
 175
 176         OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 | LOAD_TEXTURE_MAP(unit) | 4);
 177         OUT_RELOC(src->bo, I915_GEM_DOMAIN_SAMPLER, 0, 0);
 178         OUT_BATCH((buf_height(src) - 1) << TM0S1_HEIGHT_SHIFT |
 179                   (buf_width(src) - 1) << TM0S1_WIDTH_SHIFT |
 180                   MAPSURF_32BIT | MT_32BIT_ARGB8888 | tiling);
 181         OUT_BATCH((src->stride / 4 - 1) << TM0S2_PITCH_SHIFT | TM0S2_MAP_2D);
 182         OUT_BATCH(FILTER_NEAREST << TM0S3_MAG_FILTER_SHIFT |
 183                   FILTER_NEAREST << TM0S3_MIN_FILTER_SHIFT |
 184                   MIPFILTER_NONE << TM0S3_MIP_FILTER_SHIFT);
 185         OUT_BATCH(0);   /* default color */
 186
 187         OUT_BATCH(_3DSTATE_MAP_COORD_SET_CMD | TEXCOORD_SET(unit) |
 188                   ENABLE_TEXCOORD_PARAMS | TEXCOORDS_ARE_NORMAL |
 189                   TEXCOORDTYPE_CARTESIAN |
 190                   ENABLE_ADDR_V_CNTL | TEXCOORD_ADDR_V_MODE(TEXCOORDMODE_CLAMP_BORDER) |
 191                   ENABLE_ADDR_U_CNTL | TEXCOORD_ADDR_U_MODE(TEXCOORDMODE_CLAMP_BORDER));
 192 }
 193
 194 static void gen2_emit_copy_pipeline(struct intel_batchbuffer *batch)
 195 {
 196         OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD | DISABLE_INDPT_ALPHA_BLEND);
 197         OUT_BATCH(_3DSTATE_ENABLES_1_CMD | DISABLE_LOGIC_OP |
 198                   DISABLE_STENCIL_TEST | DISABLE_DEPTH_BIAS |
 199                   DISABLE_SPEC_ADD | DISABLE_FOG | DISABLE_ALPHA_TEST |
 200                   DISABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
 201
 202         OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
 203                   LOAD_TEXTURE_BLEND_STAGE(0) | 1);
 204         OUT_BATCH(TB0C_LAST_STAGE | TB0C_RESULT_SCALE_1X |
 205                   TB0C_OUTPUT_WRITE_CURRENT |
 206                   TB0C_OP_ARG1 | TB0C_ARG1_SEL_TEXEL0);
 207         OUT_BATCH(TB0A_RESULT_SCALE_1X | TB0A_OUTPUT_WRITE_CURRENT |
 208                   TB0A_OP_ARG1 | TB0A_ARG1_SEL_TEXEL0);
 209 }
 210
 211 void gen2_render_copyfunc(struct intel_batchbuffer *batch,
 212                           drm_intel_context *context,
 213                           struct scratch_buf *src, unsigned src_x, unsigned src_y,
 214                           unsigned width, unsigned height,
 215                           struct scratch_buf *dst, unsigned dst_x, unsigned dst_y)
 216 {
 217         gen2_emit_invariant(batch);
 218         gen2_emit_copy_pipeline(batch);
 219
 220         gen2_emit_target(batch, dst);
 221         gen2_emit_texture(batch, src, 0);
 222
 223         OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
 224                   I1_LOAD_S(2) | I1_LOAD_S(3) | I1_LOAD_S(8) | 2);
 225         OUT_BATCH(1<<12);
 226         OUT_BATCH(S3_CULLMODE_NONE | S3_VERTEXHAS_XY);
 227         OUT_BATCH(S8_ENABLE_COLOR_BUFFER_WRITE);
 228
 229         OUT_BATCH(_3DSTATE_VERTEX_FORMAT_2_CMD | TEXCOORDFMT_2D << 0);
 230
 231         OUT_BATCH(PRIM3D_INLINE | PRIM3D_RECTLIST | (3*4 -1));
 232         emit_vertex(batch, dst_x + width);
 233         emit_vertex(batch, dst_y + height);
 234         emit_vertex_normalized(batch, src_x + width, buf_width(src));
 235         emit_vertex_normalized(batch, src_y + height, buf_height(src));
 236
 237         emit_vertex(batch, dst_x);
 238         emit_vertex(batch, dst_y + height);
 239         emit_vertex_normalized(batch, src_x, buf_width(src));
 240         emit_vertex_normalized(batch, src_y + height, buf_height(src));
 241
 242         emit_vertex(batch, dst_x);
 243         emit_vertex(batch, dst_y);
 244         emit_vertex_normalized(batch, src_x, buf_width(src));
 245         emit_vertex_normalized(batch, src_y, buf_height(src));
 246
 247         intel_batchbuffer_flush(batch);
 248 }