2 #include "rendercopy.h"
4 #define TB0C_LAST_STAGE (1 << 31)
5 #define TB0C_RESULT_SCALE_1X (0 << 29)
6 #define TB0C_RESULT_SCALE_2X (1 << 29)
7 #define TB0C_RESULT_SCALE_4X (2 << 29)
8 #define TB0C_OP_ARG1 (1 << 25)
9 #define TB0C_OP_MODULE (3 << 25)
10 #define TB0C_OUTPUT_WRITE_CURRENT (0 << 24)
11 #define TB0C_OUTPUT_WRITE_ACCUM (1 << 24)
12 #define TB0C_ARG3_REPLICATE_ALPHA (1<<23)
13 #define TB0C_ARG3_INVERT (1<<22)
14 #define TB0C_ARG3_SEL_XXX
15 #define TB0C_ARG2_REPLICATE_ALPHA (1<<17)
16 #define TB0C_ARG2_INVERT (1<<16)
17 #define TB0C_ARG2_SEL_ONE (0 << 12)
18 #define TB0C_ARG2_SEL_FACTOR (1 << 12)
19 #define TB0C_ARG2_SEL_TEXEL0 (6 << 12)
20 #define TB0C_ARG2_SEL_TEXEL1 (7 << 12)
21 #define TB0C_ARG2_SEL_TEXEL2 (8 << 12)
22 #define TB0C_ARG2_SEL_TEXEL3 (9 << 12)
23 #define TB0C_ARG1_REPLICATE_ALPHA (1<<11)
24 #define TB0C_ARG1_INVERT (1<<10)
25 #define TB0C_ARG1_SEL_ONE (0 << 6)
26 #define TB0C_ARG1_SEL_TEXEL0 (6 << 6)
27 #define TB0C_ARG1_SEL_TEXEL1 (7 << 6)
28 #define TB0C_ARG1_SEL_TEXEL2 (8 << 6)
29 #define TB0C_ARG1_SEL_TEXEL3 (9 << 6)
30 #define TB0C_ARG0_REPLICATE_ALPHA (1<<5)
31 #define TB0C_ARG0_SEL_XXX
33 #define TB0A_CTR_STAGE_ENABLE (1<<31)
34 #define TB0A_RESULT_SCALE_1X (0 << 29)
35 #define TB0A_RESULT_SCALE_2X (1 << 29)
36 #define TB0A_RESULT_SCALE_4X (2 << 29)
37 #define TB0A_OP_ARG1 (1 << 25)
38 #define TB0A_OP_MODULE (3 << 25)
39 #define TB0A_OUTPUT_WRITE_CURRENT (0<<24)
40 #define TB0A_OUTPUT_WRITE_ACCUM (1<<24)
41 #define TB0A_CTR_STAGE_SEL_BITS_XXX
42 #define TB0A_ARG3_SEL_XXX
43 #define TB0A_ARG3_INVERT (1<<17)
44 #define TB0A_ARG2_INVERT (1<<16)
45 #define TB0A_ARG2_SEL_ONE (0 << 12)
46 #define TB0A_ARG2_SEL_TEXEL0 (6 << 12)
47 #define TB0A_ARG2_SEL_TEXEL1 (7 << 12)
48 #define TB0A_ARG2_SEL_TEXEL2 (8 << 12)
49 #define TB0A_ARG2_SEL_TEXEL3 (9 << 12)
50 #define TB0A_ARG1_INVERT (1<<10)
51 #define TB0A_ARG1_SEL_ONE (0 << 6)
52 #define TB0A_ARG1_SEL_TEXEL0 (6 << 6)
53 #define TB0A_ARG1_SEL_TEXEL1 (7 << 6)
54 #define TB0A_ARG1_SEL_TEXEL2 (8 << 6)
55 #define TB0A_ARG1_SEL_TEXEL3 (9 << 6)
58 static void gen2_emit_invariant(struct intel_batchbuffer *batch)
62 for (i = 0; i < 4; i++) {
63 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(i));
64 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD | MAP_UNIT(i) |
65 DISABLE_TEX_STREAM_BUMP |
66 ENABLE_TEX_STREAM_COORD_SET | TEX_STREAM_COORD_SET(i) |
67 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(i));
68 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
69 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(i));
72 OUT_BATCH(_3DSTATE_MAP_COORD_SETBIND_CMD);
73 OUT_BATCH(TEXBIND_SET3(TEXCOORDSRC_VTXSET_3) |
74 TEXBIND_SET2(TEXCOORDSRC_VTXSET_2) |
75 TEXBIND_SET1(TEXCOORDSRC_VTXSET_1) |
76 TEXBIND_SET0(TEXCOORDSRC_VTXSET_0));
78 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
80 OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM);
81 OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE);
83 OUT_BATCH(_3DSTATE_W_STATE_CMD);
84 OUT_BATCH(MAGIC_W_STATE_DWORD1);
85 OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
87 OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD |
88 DISABLE_INDPT_ALPHA_BLEND |
89 ENABLE_ALPHA_BLENDFUNC | ABLENDFUNC_ADD);
91 OUT_BATCH(_3DSTATE_CONST_BLEND_COLOR_CMD);
94 OUT_BATCH(_3DSTATE_MODES_1_CMD |
95 ENABLE_COLR_BLND_FUNC | BLENDFUNC_ADD |
96 ENABLE_SRC_BLND_FACTOR | SRC_BLND_FACT(BLENDFACTOR_ONE) |
97 ENABLE_DST_BLND_FACTOR | DST_BLND_FACT(BLENDFACTOR_ZERO));
99 OUT_BATCH(_3DSTATE_ENABLES_1_CMD |
101 DISABLE_STENCIL_TEST |
109 OUT_BATCH(_3DSTATE_ENABLES_2_CMD |
110 DISABLE_STENCIL_WRITE |
112 DISABLE_DEPTH_WRITE |
118 static void gen2_emit_target(struct intel_batchbuffer *batch,
119 struct scratch_buf *dst)
124 if (dst->tiling != I915_TILING_NONE)
125 tiling = BUF_3D_TILED_SURFACE;
126 if (dst->tiling == I915_TILING_Y)
127 tiling |= BUF_3D_TILE_WALK_Y;
129 OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
130 OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling | BUF_3D_PITCH(dst->stride));
131 OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
133 OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
134 OUT_BATCH(COLR_BUF_ARGB8888 |
135 DSTORG_HORT_BIAS(0x8) |
136 DSTORG_VERT_BIAS(0x8));
138 OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
140 OUT_BATCH(0); /* ymin, xmin */
141 OUT_BATCH(DRAW_YMAX(buf_height(dst) - 1) |
142 DRAW_XMAX(buf_width(dst) - 1));
143 OUT_BATCH(0); /* yorig, xorig */
146 static void gen2_emit_texture(struct intel_batchbuffer *batch,
147 struct scratch_buf *src,
153 if (src->tiling != I915_TILING_NONE)
154 tiling = TM0S1_TILED_SURFACE;
155 if (src->tiling == I915_TILING_Y)
156 tiling |= TM0S1_TILE_WALK;
158 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 | LOAD_TEXTURE_MAP(unit) | 4);
159 OUT_RELOC(src->bo, I915_GEM_DOMAIN_SAMPLER, 0, 0);
160 OUT_BATCH((buf_height(src) - 1) << TM0S1_HEIGHT_SHIFT |
161 (buf_width(src) - 1) << TM0S1_WIDTH_SHIFT |
162 MAPSURF_32BIT | MT_32BIT_ARGB8888 | tiling);
163 OUT_BATCH((src->stride / 4 - 1) << TM0S2_PITCH_SHIFT | TM0S2_MAP_2D);
164 OUT_BATCH(FILTER_NEAREST << TM0S3_MAG_FILTER_SHIFT |
165 FILTER_NEAREST << TM0S3_MIN_FILTER_SHIFT |
166 MIPFILTER_NONE << TM0S3_MIP_FILTER_SHIFT);
167 OUT_BATCH(0); /* default color */
169 OUT_BATCH(_3DSTATE_MAP_COORD_SET_CMD | TEXCOORD_SET(unit) |
170 ENABLE_TEXCOORD_PARAMS | TEXCOORDS_ARE_NORMAL |
171 TEXCOORDTYPE_CARTESIAN |
172 ENABLE_ADDR_V_CNTL | TEXCOORD_ADDR_V_MODE(TEXCOORDMODE_CLAMP_BORDER) |
173 ENABLE_ADDR_U_CNTL | TEXCOORD_ADDR_U_MODE(TEXCOORDMODE_CLAMP_BORDER));
176 static void gen2_emit_copy_pipeline(struct intel_batchbuffer *batch)
178 OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD | DISABLE_INDPT_ALPHA_BLEND);
179 OUT_BATCH(_3DSTATE_ENABLES_1_CMD | DISABLE_LOGIC_OP |
180 DISABLE_STENCIL_TEST | DISABLE_DEPTH_BIAS |
181 DISABLE_SPEC_ADD | DISABLE_FOG | DISABLE_ALPHA_TEST |
182 DISABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
184 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
185 LOAD_TEXTURE_BLEND_STAGE(0) | 1);
186 OUT_BATCH(TB0C_LAST_STAGE | TB0C_RESULT_SCALE_1X |
187 TB0C_OUTPUT_WRITE_CURRENT |
188 TB0C_OP_ARG1 | TB0C_ARG1_SEL_TEXEL0);
189 OUT_BATCH(TB0A_RESULT_SCALE_1X | TB0A_OUTPUT_WRITE_CURRENT |
190 TB0A_OP_ARG1 | TB0A_ARG1_SEL_TEXEL0);
193 void gen2_render_copyfunc(struct intel_batchbuffer *batch,
194 drm_intel_context *context,
195 struct scratch_buf *src, unsigned src_x, unsigned src_y,
196 unsigned width, unsigned height,
197 struct scratch_buf *dst, unsigned dst_x, unsigned dst_y)
199 gen2_emit_invariant(batch);
200 gen2_emit_copy_pipeline(batch);
202 gen2_emit_target(batch, dst);
203 gen2_emit_texture(batch, src, 0);
205 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
206 I1_LOAD_S(2) | I1_LOAD_S(3) | I1_LOAD_S(8) | 2);
208 OUT_BATCH(S3_CULLMODE_NONE | S3_VERTEXHAS_XY);
209 OUT_BATCH(S8_ENABLE_COLOR_BUFFER_WRITE);
211 OUT_BATCH(_3DSTATE_VERTEX_FORMAT_2_CMD | TEXCOORDFMT_2D << 0);
213 OUT_BATCH(PRIM3D_INLINE | PRIM3D_RECTLIST | (3*4 -1));
214 emit_vertex(batch, dst_x + width);
215 emit_vertex(batch, dst_y + height);
216 emit_vertex_normalized(batch, src_x + width, buf_width(src));
217 emit_vertex_normalized(batch, src_y + height, buf_height(src));
219 emit_vertex(batch, dst_x);
220 emit_vertex(batch, dst_y + height);
221 emit_vertex_normalized(batch, src_x, buf_width(src));
222 emit_vertex_normalized(batch, src_y + height, buf_height(src));
224 emit_vertex(batch, dst_x);
225 emit_vertex(batch, dst_y);
226 emit_vertex_normalized(batch, src_x, buf_width(src));
227 emit_vertex_normalized(batch, src_y, buf_height(src));
229 intel_batchbuffer_flush(batch);
232 render_copyfunc_t get_render_copyfunc(int devid)
234 render_copyfunc_t copy = NULL;
237 copy = gen2_render_copyfunc;
238 else if (IS_GEN3(devid))
239 copy = gen3_render_copyfunc;
240 else if (IS_GEN6(devid))
241 copy = gen6_render_copyfunc;
242 else if (IS_GEN7(devid))
243 copy = gen7_render_copyfunc;
244 else if (IS_GEN8(devid))
245 copy = gen8_render_copyfunc;