lib/rendercopy_gen8.c

   1 #include <assert.h>
   2 #include <stdlib.h>
   3 #include <sys/ioctl.h>
   4 #include <stdio.h>
   5 #include <string.h>
   6 #include <assert.h>
   7 #include <fcntl.h>
   8 #include <inttypes.h>
   9 #include <errno.h>
  10 #include <sys/stat.h>
  11 #include <sys/time.h>
  12
  13 #include <drm.h>
  14 #include <i915_drm.h>
  15
  16 #include "drmtest.h"
  17 #include "intel_bufmgr.h"
  18 #include "intel_batchbuffer.h"
  19 #include "intel_io.h"
  20 #include "rendercopy.h"
  21 #include "gen8_render.h"
  22 #include "intel_reg.h"
  23 #include "igt_aux.h"
  24
  25 #include <intel_aub.h>
  26
  27 #define VERTEX_SIZE (3*4)
  28
  29 #if DEBUG_RENDERCPY
  30 static void dump_batch(struct intel_batchbuffer *batch) {
  31         int fd = open("/tmp/i965-batchbuffers.dump", O_WRONLY | O_CREAT,  0666);
  32         if (fd != -1) {
  33                 write(fd, batch->buffer, 4096);
  34                 fd = close(fd);
  35         }
  36 }
  37 #else
  38 #define dump_batch(x) do { } while(0)
  39 #endif
  40
  41 struct {
  42         uint32_t cc_state;
  43         uint32_t blend_state;
  44 } cc;
  45
  46 struct {
  47         uint32_t cc_state;
  48         uint32_t sf_clip_state;
  49 } viewport;
  50
  51 /* see shaders/ps/blit.g7a */
  52 static const uint32_t ps_kernel[][4] = {
  53 #if 1
  54    { 0x0060005a, 0x21403ae8, 0x3a0000c0, 0x008d0040 },
  55    { 0x0060005a, 0x21603ae8, 0x3a0000c0, 0x008d0080 },
  56    { 0x0060005a, 0x21803ae8, 0x3a0000d0, 0x008d0040 },
  57    { 0x0060005a, 0x21a03ae8, 0x3a0000d0, 0x008d0080 },
  58    { 0x02800031, 0x2e0022e8, 0x0e000140, 0x08840001 },
  59    { 0x05800031, 0x200022e0, 0x0e000e00, 0x90031000 },
  60 #else
  61    /* Write all -1 */
  62    { 0x00600001, 0x2e000608, 0x00000000, 0x3f800000 },
  63    { 0x00600001, 0x2e200608, 0x00000000, 0x3f800000 },
  64    { 0x00600001, 0x2e400608, 0x00000000, 0x3f800000 },
  65    { 0x00600001, 0x2e600608, 0x00000000, 0x3f800000 },
  66    { 0x00600001, 0x2e800608, 0x00000000, 0x3f800000 },
  67    { 0x00600001, 0x2ea00608, 0x00000000, 0x3f800000 },
  68    { 0x00600001, 0x2ec00608, 0x00000000, 0x3f800000 },
  69    { 0x00600001, 0x2ee00608, 0x00000000, 0x3f800000 },
  70    { 0x05800031, 0x200022e0, 0x0e000e00, 0x90031000 },
  71 #endif
  72 };
  73
  74 /* AUB annotation support */
  75 #define MAX_ANNOTATIONS 33
  76 struct annotations_context {
  77         drm_intel_aub_annotation annotations[MAX_ANNOTATIONS];
  78         int index;
  79         uint32_t offset;
  80 } aub_annotations;
  81
  82 static void annotation_init(struct annotations_context *ctx)
  83 {
  84         /* ctx->annotations is an array keeping a list of annotations of the
  85          * batch buffer ordered by offset. ctx->annotations[0] is thus left
  86          * for the command stream and will be filled just before executing
  87          * the batch buffer with annotations_add_batch() */
  88         ctx->index = 1;
  89 }
  90
  91 static void add_annotation(drm_intel_aub_annotation *a,
  92                            uint32_t type, uint32_t subtype,
  93                            uint32_t ending_offset)
  94 {
  95         a->type = type;
  96         a->subtype = subtype;
  97         a->ending_offset = ending_offset;
  98 }
  99
 100 static void annotation_add_batch(struct annotations_context *ctx, size_t size)
 101 {
 102         add_annotation(&ctx->annotations[0], AUB_TRACE_TYPE_BATCH, 0, size);
 103 }
 104
 105 static void annotation_add_state(struct annotations_context *ctx,
 106                                  uint32_t state_type,
 107                                  uint32_t start_offset,
 108                                  size_t   size)
 109 {
 110         igt_assert(ctx->index < MAX_ANNOTATIONS);
 111
 112         add_annotation(&ctx->annotations[ctx->index++],
 113                        AUB_TRACE_TYPE_NOTYPE, 0,
 114                        start_offset);
 115         add_annotation(&ctx->annotations[ctx->index++],
 116                        AUB_TRACE_TYPE(state_type),
 117                        AUB_TRACE_SUBTYPE(state_type),
 118                        start_offset + size);
 119 }
 120
 121 static void annotation_flush(struct annotations_context *ctx,
 122                              struct intel_batchbuffer *batch)
 123 {
 124         if (!igt_aub_dump_enabled())
 125                 return;
 126
 127         drm_intel_bufmgr_gem_set_aub_annotations(batch->bo,
 128                                                  ctx->annotations,
 129                                                  ctx->index);
 130 }
 131
 132 static uint32_t
 133 batch_used(struct intel_batchbuffer *batch)
 134 {
 135         return batch->ptr - batch->buffer;
 136 }
 137
 138 static uint32_t
 139 batch_align(struct intel_batchbuffer *batch, uint32_t align)
 140 {
 141         uint32_t offset = batch_used(batch);
 142         offset = ALIGN(offset, align);
 143         batch->ptr = batch->buffer + offset;
 144         return offset;
 145 }
 146
 147 static void *
 148 batch_alloc(struct intel_batchbuffer *batch, uint32_t size, uint32_t align)
 149 {
 150         uint32_t offset = batch_align(batch, align);
 151         batch->ptr += size;
 152         return memset(batch->buffer + offset, 0, size);
 153 }
 154
 155 static uint32_t
 156 batch_offset(struct intel_batchbuffer *batch, void *ptr)
 157 {
 158         return (uint8_t *)ptr - batch->buffer;
 159 }
 160
 161 static uint32_t
 162 batch_copy(struct intel_batchbuffer *batch, const void *ptr, uint32_t size, uint32_t align)
 163 {
 164         return batch_offset(batch, memcpy(batch_alloc(batch, size, align), ptr, size));
 165 }
 166
 167 static void
 168 gen6_render_flush(struct intel_batchbuffer *batch,
 169                   drm_intel_context *context, uint32_t batch_end)
 170 {
 171         int ret;
 172
 173         ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer);
 174         if (ret == 0)
 175                 ret = drm_intel_gem_bo_context_exec(batch->bo, context,
 176                                                     batch_end, 0);
 177         igt_assert(ret == 0);
 178 }
 179
 180 /* Mostly copy+paste from gen6, except height, width, pitch moved */
 181 static uint32_t
 182 gen8_bind_buf(struct intel_batchbuffer *batch, struct igt_buf *buf,
 183               uint32_t format, int is_dst) {
 184         struct gen8_surface_state *ss;
 185         uint32_t write_domain, read_domain, offset;
 186         int ret;
 187
 188         if (is_dst) {
 189                 write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
 190         } else {
 191                 write_domain = 0;
 192                 read_domain = I915_GEM_DOMAIN_SAMPLER;
 193         }
 194
 195         ss = batch_alloc(batch, sizeof(*ss), 64);
 196         offset = batch_offset(batch, ss);
 197         annotation_add_state(&aub_annotations, AUB_TRACE_SURFACE_STATE,
 198                              offset, sizeof(*ss));
 199
 200         ss->ss0.surface_type = GEN6_SURFACE_2D;
 201         ss->ss0.surface_format = format;
 202         ss->ss0.render_cache_read_write = 1;
 203         ss->ss0.vertical_alignment = 1; /* align 4 */
 204         ss->ss0.horizontal_alignment = 1; /* align 4 */
 205         if (buf->tiling == I915_TILING_X)
 206                 ss->ss0.tiled_mode = 2;
 207         else if (buf->tiling == I915_TILING_Y)
 208                 ss->ss0.tiled_mode = 3;
 209
 210         ss->ss8.base_addr = buf->bo->offset;
 211
 212         ret = drm_intel_bo_emit_reloc(batch->bo,
 213                                       batch_offset(batch, ss) + 8 * 4,
 214                                       buf->bo, 0,
 215                                       read_domain, write_domain);
 216         igt_assert(ret == 0);
 217
 218         ss->ss2.height = igt_buf_height(buf) - 1;
 219         ss->ss2.width  = igt_buf_width(buf) - 1;
 220         ss->ss3.pitch  = buf->stride - 1;
 221
 222         ss->ss7.shader_chanel_select_r = 4;
 223         ss->ss7.shader_chanel_select_g = 5;
 224         ss->ss7.shader_chanel_select_b = 6;
 225         ss->ss7.shader_chanel_select_a = 7;
 226
 227         return offset;
 228 }
 229
 230 static uint32_t
 231 gen8_bind_surfaces(struct intel_batchbuffer *batch,
 232                    struct igt_buf *src,
 233                    struct igt_buf *dst)
 234 {
 235         uint32_t *binding_table, offset;
 236
 237         binding_table = batch_alloc(batch, 8, 32);
 238         offset = batch_offset(batch, binding_table);
 239         annotation_add_state(&aub_annotations, AUB_TRACE_BINDING_TABLE,
 240                              offset, 8);
 241
 242         binding_table[0] =
 243                 gen8_bind_buf(batch, dst, GEN6_SURFACEFORMAT_B8G8R8A8_UNORM, 1);
 244         binding_table[1] =
 245                 gen8_bind_buf(batch, src, GEN6_SURFACEFORMAT_B8G8R8A8_UNORM, 0);
 246
 247         return offset;
 248 }
 249
 250 /* Mostly copy+paste from gen6, except wrap modes moved */
 251 static uint32_t
 252 gen8_create_sampler(struct intel_batchbuffer *batch) {
 253         struct gen8_sampler_state *ss;
 254         uint32_t offset;
 255
 256         ss = batch_alloc(batch, sizeof(*ss), 64);
 257         offset = batch_offset(batch, ss);
 258         annotation_add_state(&aub_annotations, AUB_TRACE_SAMPLER_STATE,
 259                              offset, sizeof(*ss));
 260
 261         ss->ss0.min_filter = GEN6_MAPFILTER_NEAREST;
 262         ss->ss0.mag_filter = GEN6_MAPFILTER_NEAREST;
 263         ss->ss3.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
 264         ss->ss3.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
 265         ss->ss3.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
 266
 267         /* I've experimented with non-normalized coordinates and using the LD
 268          * sampler fetch, but couldn't make it work. */
 269         ss->ss3.non_normalized_coord = 0;
 270
 271         return offset;
 272 }
 273
 274 static uint32_t
 275 gen8_fill_ps(struct intel_batchbuffer *batch,
 276              const uint32_t kernel[][4],
 277              size_t size)
 278 {
 279         uint32_t offset;
 280
 281         offset = batch_copy(batch, kernel, size, 64);
 282         annotation_add_state(&aub_annotations, AUB_TRACE_KERNEL_INSTRUCTIONS,
 283                              offset, size);
 284
 285         return offset;
 286 }
 287
 288 /*
 289  * gen7_fill_vertex_buffer_data populate vertex buffer with data.
 290  *
 291  * The vertex buffer consists of 3 vertices to construct a RECTLIST. The 4th
 292  * vertex is implied (automatically derived by the HW). Each element has the
 293  * destination offset, and the normalized texture offset (src). The rectangle
 294  * itself will span the entire subsurface to be copied.
 295  *
 296  * see gen6_emit_vertex_elements
 297  */
 298 static uint32_t
 299 gen7_fill_vertex_buffer_data(struct intel_batchbuffer *batch,
 300                              struct igt_buf *src,
 301                              uint32_t src_x, uint32_t src_y,
 302                              uint32_t dst_x, uint32_t dst_y,
 303                              uint32_t width, uint32_t height)
 304 {
 305         void *start;
 306         uint32_t offset;
 307
 308         batch_align(batch, 8);
 309         start = batch->ptr;
 310
 311         emit_vertex_2s(batch, dst_x + width, dst_y + height);
 312         emit_vertex_normalized(batch, src_x + width, igt_buf_width(src));
 313         emit_vertex_normalized(batch, src_y + height, igt_buf_height(src));
 314
 315         emit_vertex_2s(batch, dst_x, dst_y + height);
 316         emit_vertex_normalized(batch, src_x, igt_buf_width(src));
 317         emit_vertex_normalized(batch, src_y + height, igt_buf_height(src));
 318
 319         emit_vertex_2s(batch, dst_x, dst_y);
 320         emit_vertex_normalized(batch, src_x, igt_buf_width(src));
 321         emit_vertex_normalized(batch, src_y, igt_buf_height(src));
 322
 323         offset = batch_offset(batch, start);
 324         annotation_add_state(&aub_annotations, AUB_TRACE_VERTEX_BUFFER,
 325                              offset, 3 * VERTEX_SIZE);
 326         return offset;
 327 }
 328
 329 /*
 330  * gen6_emit_vertex_elements - The vertex elements describe the contents of the
 331  * vertex buffer. We pack the vertex buffer in a semi weird way, conforming to
 332  * what gen6_rendercopy did. The most straightforward would be to store
 333  * everything as floats.
 334  *
 335  * see gen7_fill_vertex_buffer_data() for where the corresponding elements are
 336  * packed.
 337  */
 338 static void
 339 gen6_emit_vertex_elements(struct intel_batchbuffer *batch) {
 340         /*
 341          * The VUE layout
 342          *    dword 0-3: pad (0, 0, 0. 0)
 343          *    dword 4-7: position (x, y, 0, 1.0),
 344          *    dword 8-11: texture coordinate 0 (u0, v0, 0, 1.0)
 345          */
 346         OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | (3 * 2 + 1 - 2));
 347
 348         /* Element state 0. These are 4 dwords of 0 required for the VUE format.
 349          * We don't really know or care what they do.
 350          */
 351         OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
 352                   GEN6_SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT |
 353                   0 << VE0_OFFSET_SHIFT); /* we specify 0, but it's really does not exist */
 354         OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
 355                   GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
 356                   GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
 357                   GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
 358
 359         /* Element state 1 - Our "destination" vertices. These are passed down
 360          * through the pipeline, and eventually make it to the pixel shader as
 361          * the offsets in the destination surface. It's packed as the 16
 362          * signed/scaled because of gen6 rendercopy. I see no particular reason
 363          * for doing this though.
 364          */
 365         OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
 366                   GEN6_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
 367                   0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */
 368         OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
 369                   GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
 370                   GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
 371                   GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
 372
 373         /* Element state 2. Last but not least we store the U,V components as
 374          * normalized floats. These will be used in the pixel shader to sample
 375          * from the source buffer.
 376          */
 377         OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
 378                   GEN6_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT |
 379                   4 << VE0_OFFSET_SHIFT);       /* offset vb in bytes */
 380         OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
 381                   GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
 382                   GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
 383                   GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
 384 }
 385
 386 /*
 387  * gen7_emit_vertex_buffer emit the vertex buffers command
 388  *
 389  * @batch
 390  * @offset - bytw offset within the @batch where the vertex buffer starts.
 391  */
 392 static void gen7_emit_vertex_buffer(struct intel_batchbuffer *batch,
 393                                     uint32_t offset) {
 394         OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | (1 + (4 * 1) - 2));
 395         OUT_BATCH(0 << VB0_BUFFER_INDEX_SHIFT | /* VB 0th index */
 396                   GEN7_VB0_BUFFER_ADDR_MOD_EN | /* Address Modify Enable */
 397                   VERTEX_SIZE << VB0_BUFFER_PITCH_SHIFT);
 398         OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, offset);
 399         OUT_BATCH(0);
 400         OUT_BATCH(3 * VERTEX_SIZE);
 401 }
 402
 403 static uint32_t
 404 gen6_create_cc_state(struct intel_batchbuffer *batch)
 405 {
 406         struct gen6_color_calc_state *cc_state;
 407         uint32_t offset;
 408
 409         cc_state = batch_alloc(batch, sizeof(*cc_state), 64);
 410         offset = batch_offset(batch, cc_state);
 411         annotation_add_state(&aub_annotations, AUB_TRACE_CC_STATE,
 412                              offset, sizeof(*cc_state));
 413
 414         return offset;
 415 }
 416
 417 static uint32_t
 418 gen8_create_blend_state(struct intel_batchbuffer *batch)
 419 {
 420         struct gen8_blend_state *blend;
 421         int i;
 422         uint32_t offset;
 423
 424         blend = batch_alloc(batch, sizeof(*blend), 64);
 425         offset = batch_offset(batch, blend);
 426         annotation_add_state(&aub_annotations, AUB_TRACE_BLEND_STATE,
 427                              offset, sizeof(*blend));
 428
 429         for (i = 0; i < 16; i++) {
 430                 blend->bs[i].dest_blend_factor = GEN6_BLENDFACTOR_ZERO;
 431                 blend->bs[i].source_blend_factor = GEN6_BLENDFACTOR_ONE;
 432                 blend->bs[i].color_blend_func = GEN6_BLENDFUNCTION_ADD;
 433                 blend->bs[i].pre_blend_color_clamp = 1;
 434                 blend->bs[i].color_buffer_blend = 0;
 435         }
 436
 437         return offset;
 438 }
 439
 440 static uint32_t
 441 gen6_create_cc_viewport(struct intel_batchbuffer *batch)
 442 {
 443         struct gen6_cc_viewport *vp;
 444         uint32_t offset;
 445
 446         vp = batch_alloc(batch, sizeof(*vp), 32);
 447         offset = batch_offset(batch, vp);
 448         annotation_add_state(&aub_annotations, AUB_TRACE_CC_VP_STATE,
 449                              offset, sizeof(*vp));
 450
 451         /* XXX I don't understand this */
 452         vp->min_depth = -1.e35;
 453         vp->max_depth = 1.e35;
 454
 455         return offset;
 456 }
 457
 458 static uint32_t
 459 gen7_create_sf_clip_viewport(struct intel_batchbuffer *batch) {
 460         /* XXX these are likely not needed */
 461         struct gen7_sf_clip_viewport *scv_state;
 462         uint32_t offset;
 463
 464         scv_state = batch_alloc(batch, sizeof(*scv_state), 64);
 465         offset = batch_offset(batch, scv_state);
 466         annotation_add_state(&aub_annotations, AUB_TRACE_CLIP_VP_STATE,
 467                              offset, sizeof(*scv_state));
 468
 469         scv_state->guardband.xmin = 0;
 470         scv_state->guardband.xmax = 1.0f;
 471         scv_state->guardband.ymin = 0;
 472         scv_state->guardband.ymax = 1.0f;
 473
 474         return offset;
 475 }
 476
 477 static uint32_t
 478 gen6_create_scissor_rect(struct intel_batchbuffer *batch)
 479 {
 480         struct gen6_scissor_rect *scissor;
 481         uint32_t offset;
 482
 483         scissor = batch_alloc(batch, sizeof(*scissor), 64);
 484         offset = batch_offset(batch, scissor);
 485         annotation_add_state(&aub_annotations, AUB_TRACE_SCISSOR_STATE,
 486                              offset, sizeof(*scissor));
 487
 488         return offset;
 489 }
 490
 491 static void
 492 gen8_emit_sip(struct intel_batchbuffer *batch) {
 493         OUT_BATCH(GEN6_STATE_SIP | (3 - 2));
 494         OUT_BATCH(0);
 495         OUT_BATCH(0);
 496 }
 497
 498 static void
 499 gen7_emit_push_constants(struct intel_batchbuffer *batch) {
 500         OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS);
 501         OUT_BATCH(0);
 502         OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS);
 503         OUT_BATCH(0);
 504         OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS);
 505         OUT_BATCH(0);
 506         OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS);
 507         OUT_BATCH(0);
 508         OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS);
 509         OUT_BATCH(0);
 510 }
 511
 512 static void
 513 gen8_emit_state_base_address(struct intel_batchbuffer *batch) {
 514         OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (16 - 2));
 515
 516         /* general */
 517         OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
 518         OUT_BATCH(0);
 519
 520         /* stateless data port */
 521         OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
 522
 523         /* surface */
 524         OUT_RELOC(batch->bo, I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY);
 525
 526         /* dynamic */
 527         OUT_RELOC(batch->bo, I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION,
 528                   0, BASE_ADDRESS_MODIFY);
 529
 530         /* indirect */
 531         OUT_BATCH(0);
 532         OUT_BATCH(0);
 533
 534         /* instruction */
 535         OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
 536
 537         /* general state buffer size */
 538         OUT_BATCH(0xfffff000 | 1);
 539         /* dynamic state buffer size */
 540         OUT_BATCH(1 << 12 | 1);
 541         /* indirect object buffer size */
 542         OUT_BATCH(0xfffff000 | 1);
 543         /* intruction buffer size */
 544         OUT_BATCH(1 << 12 | 1);
 545 }
 546
 547 static void
 548 gen7_emit_urb(struct intel_batchbuffer *batch) {
 549         /* XXX: Min valid values from mesa */
 550         const int vs_entries = 64;
 551         const int vs_size = 2;
 552         const int vs_start = 2;
 553
 554         OUT_BATCH(GEN7_3DSTATE_URB_VS);
 555         OUT_BATCH(vs_entries | ((vs_size - 1) << 16) | (vs_start << 25));
 556         OUT_BATCH(GEN7_3DSTATE_URB_GS);
 557         OUT_BATCH(vs_start << 25);
 558         OUT_BATCH(GEN7_3DSTATE_URB_HS);
 559         OUT_BATCH(vs_start << 25);
 560         OUT_BATCH(GEN7_3DSTATE_URB_DS);
 561         OUT_BATCH(vs_start << 25);
 562 }
 563
 564 static void
 565 gen8_emit_cc(struct intel_batchbuffer *batch) {
 566         OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS);
 567         OUT_BATCH(cc.blend_state | 1);
 568
 569         OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS);
 570         OUT_BATCH(cc.cc_state | 1);
 571 }
 572
 573 static void
 574 gen8_emit_multisample(struct intel_batchbuffer *batch) {
 575         OUT_BATCH(GEN8_3DSTATE_MULTISAMPLE);
 576         OUT_BATCH(0);
 577
 578         OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK);
 579         OUT_BATCH(1);
 580 }
 581
 582 static void
 583 gen8_emit_vs(struct intel_batchbuffer *batch) {
 584         OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS);
 585         OUT_BATCH(0);
 586
 587         OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS);
 588         OUT_BATCH(0);
 589
 590         OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | (11 - 2));
 591         OUT_BATCH(0);
 592         OUT_BATCH(0);
 593         OUT_BATCH(0);
 594         OUT_BATCH(0);
 595         OUT_BATCH(0);
 596         OUT_BATCH(0);
 597         OUT_BATCH(0);
 598         OUT_BATCH(0);
 599         OUT_BATCH(0);
 600         OUT_BATCH(0);
 601
 602         OUT_BATCH(GEN6_3DSTATE_VS | (9-2));
 603         OUT_BATCH(0);
 604         OUT_BATCH(0);
 605         OUT_BATCH(0);
 606         OUT_BATCH(0);
 607         OUT_BATCH(0);
 608         OUT_BATCH(0);
 609         OUT_BATCH(0);
 610         OUT_BATCH(0);
 611 }
 612
 613 static void
 614 gen8_emit_hs(struct intel_batchbuffer *batch) {
 615         OUT_BATCH(GEN7_3DSTATE_CONSTANT_HS | (11 - 2));
 616         OUT_BATCH(0);
 617         OUT_BATCH(0);
 618         OUT_BATCH(0);
 619         OUT_BATCH(0);
 620         OUT_BATCH(0);
 621         OUT_BATCH(0);
 622         OUT_BATCH(0);
 623         OUT_BATCH(0);
 624         OUT_BATCH(0);
 625         OUT_BATCH(0);
 626
 627         OUT_BATCH(GEN7_3DSTATE_HS | (9-2));
 628         OUT_BATCH(0);
 629         OUT_BATCH(0);
 630         OUT_BATCH(0);
 631         OUT_BATCH(0);
 632         OUT_BATCH(0);
 633         OUT_BATCH(0);
 634         OUT_BATCH(0);
 635         OUT_BATCH(0);
 636
 637         OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS);
 638         OUT_BATCH(0);
 639
 640         OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS);
 641         OUT_BATCH(0);
 642 }
 643
 644 static void
 645 gen8_emit_gs(struct intel_batchbuffer *batch) {
 646         OUT_BATCH(GEN7_3DSTATE_CONSTANT_GS | (11 - 2));
 647         OUT_BATCH(0);
 648         OUT_BATCH(0);
 649         OUT_BATCH(0);
 650         OUT_BATCH(0);
 651         OUT_BATCH(0);
 652         OUT_BATCH(0);
 653         OUT_BATCH(0);
 654         OUT_BATCH(0);
 655         OUT_BATCH(0);
 656         OUT_BATCH(0);
 657
 658         OUT_BATCH(GEN7_3DSTATE_GS | (10-2));
 659         OUT_BATCH(0);
 660         OUT_BATCH(0);
 661         OUT_BATCH(0);
 662         OUT_BATCH(0);
 663         OUT_BATCH(0);
 664         OUT_BATCH(0);
 665         OUT_BATCH(0);
 666         OUT_BATCH(0);
 667         OUT_BATCH(0);
 668
 669         OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS);
 670         OUT_BATCH(0);
 671
 672         OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS);
 673         OUT_BATCH(0);
 674 }
 675
 676 static void
 677 gen8_emit_ds(struct intel_batchbuffer *batch) {
 678         OUT_BATCH(GEN7_3DSTATE_CONSTANT_DS | (11 - 2));
 679         OUT_BATCH(0);
 680         OUT_BATCH(0);
 681         OUT_BATCH(0);
 682         OUT_BATCH(0);
 683         OUT_BATCH(0);
 684         OUT_BATCH(0);
 685         OUT_BATCH(0);
 686         OUT_BATCH(0);
 687         OUT_BATCH(0);
 688         OUT_BATCH(0);
 689
 690         OUT_BATCH(GEN7_3DSTATE_DS | (9-2));
 691         OUT_BATCH(0);
 692         OUT_BATCH(0);
 693         OUT_BATCH(0);
 694         OUT_BATCH(0);
 695         OUT_BATCH(0);
 696         OUT_BATCH(0);
 697         OUT_BATCH(0);
 698         OUT_BATCH(0);
 699
 700         OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS);
 701         OUT_BATCH(0);
 702
 703         OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS);
 704         OUT_BATCH(0);
 705 }
 706
 707 static void
 708 gen8_emit_wm_hz_op(struct intel_batchbuffer *batch) {
 709         OUT_BATCH(GEN8_3DSTATE_WM_HZ_OP | (5-2));
 710         OUT_BATCH(0);
 711         OUT_BATCH(0);
 712         OUT_BATCH(0);
 713         OUT_BATCH(0);
 714 }
 715
 716 static void
 717 gen8_emit_null_state(struct intel_batchbuffer *batch) {
 718         gen8_emit_wm_hz_op(batch);
 719         gen8_emit_hs(batch);
 720         OUT_BATCH(GEN7_3DSTATE_TE | (4-2));
 721         OUT_BATCH(0);
 722         OUT_BATCH(0);
 723         OUT_BATCH(0);
 724         gen8_emit_gs(batch);
 725         gen8_emit_ds(batch);
 726         gen8_emit_vs(batch);
 727 }
 728
 729 static void
 730 gen7_emit_clip(struct intel_batchbuffer *batch) {
 731         OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2));
 732         OUT_BATCH(0);
 733         OUT_BATCH(0); /*  pass-through */
 734         OUT_BATCH(0);
 735 }
 736
 737 static void
 738 gen8_emit_sf(struct intel_batchbuffer *batch)
 739 {
 740         int i;
 741
 742         OUT_BATCH(GEN7_3DSTATE_SBE | (4 - 2));
 743         OUT_BATCH(1 << GEN7_SBE_NUM_OUTPUTS_SHIFT |
 744                   GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH |
 745                   GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET |
 746                   1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 747                   1 << GEN8_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 748         OUT_BATCH(0);
 749         OUT_BATCH(0);
 750
 751         OUT_BATCH(GEN8_3DSTATE_SBE_SWIZ | (11 - 2));
 752         for (i = 0; i < 8; i++)
 753                 OUT_BATCH(0);
 754         OUT_BATCH(0);
 755         OUT_BATCH(0);
 756
 757         OUT_BATCH(GEN8_3DSTATE_RASTER | (5 - 2));
 758         OUT_BATCH(GEN8_RASTER_FRONT_WINDING_CCW | GEN8_RASTER_CULL_NONE);
 759         OUT_BATCH(0);
 760         OUT_BATCH(0);
 761         OUT_BATCH(0);
 762
 763         OUT_BATCH(GEN6_3DSTATE_SF | (4 - 2));
 764         OUT_BATCH(0);
 765         OUT_BATCH(0);
 766         OUT_BATCH(0);
 767 }
 768
 769 static void
 770 gen8_emit_ps(struct intel_batchbuffer *batch, uint32_t kernel) {
 771         const int max_threads = 63;
 772
 773         OUT_BATCH(GEN6_3DSTATE_WM | (2 - 2));
 774         OUT_BATCH(/* XXX: I don't understand the BARYCENTRIC stuff, but it
 775                    * appears we need it to put our setup data in the place we
 776                    * expect (g6, see below) */
 777                   GEN7_3DSTATE_PS_PERSPECTIVE_PIXEL_BARYCENTRIC);
 778
 779         OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS | (11-2));
 780         OUT_BATCH(0);
 781         OUT_BATCH(0);
 782         OUT_BATCH(0);
 783         OUT_BATCH(0);
 784         OUT_BATCH(0);
 785         OUT_BATCH(0);
 786         OUT_BATCH(0);
 787         OUT_BATCH(0);
 788         OUT_BATCH(0);
 789         OUT_BATCH(0);
 790
 791         OUT_BATCH(GEN7_3DSTATE_PS | (12-2));
 792         OUT_BATCH(kernel);
 793         OUT_BATCH(0); /* kernel hi */
 794         OUT_BATCH(1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF |
 795                   2 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 796         OUT_BATCH(0); /* scratch space stuff */
 797         OUT_BATCH(0); /* scratch hi */
 798         OUT_BATCH((max_threads - 1) << GEN8_3DSTATE_PS_MAX_THREADS_SHIFT |
 799                   GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
 800         OUT_BATCH(6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT);
 801         OUT_BATCH(0); // kernel 1
 802         OUT_BATCH(0); /* kernel 1 hi */
 803         OUT_BATCH(0); // kernel 2
 804         OUT_BATCH(0); /* kernel 2 hi */
 805
 806         OUT_BATCH(GEN8_3DSTATE_PS_BLEND | (2 - 2));
 807         OUT_BATCH(GEN8_PS_BLEND_HAS_WRITEABLE_RT);
 808
 809         OUT_BATCH(GEN8_3DSTATE_PS_EXTRA | (2 - 2));
 810         OUT_BATCH(GEN8_PSX_PIXEL_SHADER_VALID | GEN8_PSX_ATTRIBUTE_ENABLE);
 811 }
 812
 813 static void
 814 gen8_emit_depth(struct intel_batchbuffer *batch) {
 815         OUT_BATCH(GEN8_3DSTATE_WM_DEPTH_STENCIL | (3 - 2));
 816         OUT_BATCH(0);
 817         OUT_BATCH(0);
 818
 819         OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (8-2));
 820         OUT_BATCH(0);
 821         OUT_BATCH(0);
 822         OUT_BATCH(0);
 823         OUT_BATCH(0);
 824         OUT_BATCH(0);
 825         OUT_BATCH(0);
 826         OUT_BATCH(0);
 827
 828         OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER | (5 - 2));
 829         OUT_BATCH(0);
 830         OUT_BATCH(0);
 831         OUT_BATCH(0);
 832         OUT_BATCH(0);
 833
 834         OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER | (5 - 2));
 835         OUT_BATCH(0);
 836         OUT_BATCH(0);
 837         OUT_BATCH(0);
 838         OUT_BATCH(0);
 839 }
 840
 841 static void
 842 gen7_emit_clear(struct intel_batchbuffer *batch) {
 843         OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS | (3-2));
 844         OUT_BATCH(0);
 845         OUT_BATCH(1); // clear valid
 846 }
 847
 848 static void
 849 gen6_emit_drawing_rectangle(struct intel_batchbuffer *batch, struct igt_buf *dst)
 850 {
 851         OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
 852         OUT_BATCH(0);
 853         OUT_BATCH((igt_buf_height(dst) - 1) << 16 | (igt_buf_width(dst) - 1));
 854         OUT_BATCH(0);
 855 }
 856
 857 static void gen8_emit_vf_topology(struct intel_batchbuffer *batch)
 858 {
 859         OUT_BATCH(GEN8_3DSTATE_VF_TOPOLOGY);
 860         OUT_BATCH(_3DPRIM_RECTLIST);
 861 }
 862
 863 /* Vertex elements MUST be defined before this according to spec */
 864 static void gen8_emit_primitive(struct intel_batchbuffer *batch, uint32_t offset)
 865 {
 866         OUT_BATCH(GEN8_3DSTATE_VF_INSTANCING | (3 - 2));
 867         OUT_BATCH(0);
 868         OUT_BATCH(0);
 869
 870         OUT_BATCH(GEN6_3DPRIMITIVE | (7-2));
 871         OUT_BATCH(0);   /* gen8+ ignore the topology type field */
 872         OUT_BATCH(3);   /* vertex count */
 873         OUT_BATCH(0);   /*  We're specifying this instead with offset in GEN6_3DSTATE_VERTEX_BUFFERS */
 874         OUT_BATCH(1);   /* single instance */
 875         OUT_BATCH(0);   /* start instance location */
 876         OUT_BATCH(0);   /* index buffer offset, ignored */
 877 }
 878
 879 /* The general rule is if it's named gen6 it is directly copied from
 880  * gen6_render_copyfunc.
 881  *
 882  * This sets up most of the 3d pipeline, and most of that to NULL state. The
 883  * docs aren't specific about exactly what must be set up NULL, but the general
 884  * rule is we could be run at any time, and so the most state we set to NULL,
 885  * the better our odds of success.
 886  *
 887  * +---------------+ <---- 4096
 888  * |       ^       |
 889  * |       |       |
 890  * |    various    |
 891  * |      state    |
 892  * |       |       |
 893  * |_______|_______| <---- 2048 + ?
 894  * |       ^       |
 895  * |       |       |
 896  * |   batch       |
 897  * |    commands   |
 898  * |       |       |
 899  * |       |       |
 900  * +---------------+ <---- 0 + ?
 901  *
 902  * The batch commands point to state within tthe batch, so all state offsets should be
 903  * 0 < offset < 4096. Both commands and state build upwards, and are constructed
 904  * in that order. This means too many batch commands can delete state if not
 905  * careful.
 906  *
 907  */
 908
 909 #define BATCH_STATE_SPLIT 2048
 910
 911 void gen8_render_copyfunc(struct intel_batchbuffer *batch,
 912                           drm_intel_context *context,
 913                           struct igt_buf *src, unsigned src_x, unsigned src_y,
 914                           unsigned width, unsigned height,
 915                           struct igt_buf *dst, unsigned dst_x, unsigned dst_y)
 916 {
 917         uint32_t ps_sampler_state, ps_kernel_off, ps_binding_table;
 918         uint32_t scissor_state;
 919         uint32_t vertex_buffer;
 920         uint32_t batch_end;
 921
 922         intel_batchbuffer_flush_with_context(batch, context);
 923
 924         batch_align(batch, 8);
 925
 926         batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
 927
 928         annotation_init(&aub_annotations);
 929
 930         ps_binding_table  = gen8_bind_surfaces(batch, src, dst);
 931         ps_sampler_state  = gen8_create_sampler(batch);
 932         ps_kernel_off = gen8_fill_ps(batch, ps_kernel, sizeof(ps_kernel));
 933         vertex_buffer = gen7_fill_vertex_buffer_data(batch, src,
 934                                                      src_x, src_y,
 935                                                      dst_x, dst_y,
 936                                                      width, height);
 937         cc.cc_state = gen6_create_cc_state(batch);
 938         cc.blend_state = gen8_create_blend_state(batch);
 939         viewport.cc_state = gen6_create_cc_viewport(batch);
 940         viewport.sf_clip_state = gen7_create_sf_clip_viewport(batch);
 941         scissor_state = gen6_create_scissor_rect(batch);
 942         /* TODO: theree is other state which isn't setup */
 943
 944         igt_assert(batch->ptr < &batch->buffer[4095]);
 945
 946         batch->ptr = batch->buffer;
 947
 948         /* Start emitting the commands. The order roughly follows the mesa blorp
 949          * order */
 950         OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D);
 951
 952         gen8_emit_sip(batch);
 953
 954         gen7_emit_push_constants(batch);
 955
 956         gen8_emit_state_base_address(batch);
 957
 958         OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC);
 959         OUT_BATCH(viewport.cc_state);
 960         OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP);
 961         OUT_BATCH(viewport.sf_clip_state);
 962
 963         gen7_emit_urb(batch);
 964
 965         gen8_emit_cc(batch);
 966
 967         gen8_emit_multisample(batch);
 968
 969         gen8_emit_null_state(batch);
 970
 971         OUT_BATCH(GEN7_3DSTATE_STREAMOUT | (5-2));
 972         OUT_BATCH(0);
 973         OUT_BATCH(0);
 974         OUT_BATCH(0);
 975         OUT_BATCH(0);
 976
 977         gen7_emit_clip(batch);
 978
 979         gen8_emit_sf(batch);
 980
 981         OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS);
 982         OUT_BATCH(ps_binding_table);
 983
 984         OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS);
 985         OUT_BATCH(ps_sampler_state);
 986
 987         gen8_emit_ps(batch, ps_kernel_off);
 988
 989         OUT_BATCH(GEN6_3DSTATE_SCISSOR_STATE_POINTERS);
 990         OUT_BATCH(scissor_state);
 991
 992         gen8_emit_depth(batch);
 993
 994         gen7_emit_clear(batch);
 995
 996         gen6_emit_drawing_rectangle(batch, dst);
 997
 998         gen7_emit_vertex_buffer(batch, vertex_buffer);
 999         gen6_emit_vertex_elements(batch);
1000
1001         gen8_emit_vf_topology(batch);
1002         gen8_emit_primitive(batch, vertex_buffer);
1003
1004         OUT_BATCH(MI_BATCH_BUFFER_END);
1005
1006         batch_end = batch_align(batch, 8);
1007         igt_assert(batch_end < BATCH_STATE_SPLIT);
1008         annotation_add_batch(&aub_annotations, batch_end);
1009
1010         dump_batch(batch);
1011
1012         annotation_flush(&aub_annotations, batch);
1013
1014         gen6_render_flush(batch, context, batch_end);
1015         intel_batchbuffer_reset(batch);
1016 }