lib/rendercopy_gen8.c

   1 #include "rendercopy.h"
   2 #include "gen8_render.h"
   3
   4 #include <assert.h>
   5
   6 #define ALIGN(x, y) (((x) + (y)-1) & ~((y)-1))
   7 #define VERTEX_SIZE (3*4)
   8
   9 #if DEBUG_RENDERCPY
  10 static void dump_batch(struct intel_batchbuffer *batch)
  11 #else
  12 #define dump_batch(x) do { } while(0)
  13 #endif
  14
  15 struct {
  16         uint32_t cc_state;
  17         uint32_t blend_state;
  18 } cc;
  19
  20 struct {
  21         uint32_t cc_state;
  22         uint32_t sf_clip_state;
  23 } viewport;
  24
  25 /* see shaders/ps/blit.g7a */
  26 static const uint32_t ps_kernel[][4] = {
  27 #if 1
  28    { 0x0060005a, 0x21403ae8, 0x3a0000c0, 0x008d0040 },
  29    { 0x0060005a, 0x21603ae8, 0x3a0000c0, 0x008d0080 },
  30    { 0x0060005a, 0x21803ae8, 0x3a0000d0, 0x008d0040 },
  31    { 0x0060005a, 0x21a03ae8, 0x3a0000d0, 0x008d0080 },
  32    { 0x02800031, 0x2e0022e8, 0x0e000140, 0x08840001 },
  33    { 0x05800031, 0x200022e0, 0x0e000e00, 0x90031000 },
  34 #else
  35    /* Write all -1 */
  36    { 0x00600001, 0x2e000061, 0x00000000, 0x3f800000 },
  37    { 0x00600001, 0x2e200061, 0x00000000, 0x3f800000 },
  38    { 0x00600001, 0x2e400061, 0x00000000, 0x3f800000 },
  39    { 0x00600001, 0x2e600061, 0x00000000, 0x3f800000 },
  40    { 0x00600001, 0x2e800061, 0x00000000, 0x3f800000 },
  41    { 0x00600001, 0x2ea00061, 0x00000000, 0x3f800000 },
  42    { 0x00600001, 0x2ec00061, 0x00000000, 0x3f800000 },
  43    { 0x00600001, 0x2ee00061, 0x00000000, 0x3f800000 },
  44    { 0x05800031, 0x20001e3c, 0x00000e00, 0x90031000 },
  45 #endif
  46 };
  47
  48 static uint32_t
  49 batch_used(struct intel_batchbuffer *batch)
  50 {
  51         return batch->ptr - batch->buffer;
  52 }
  53
  54 static uint32_t
  55 batch_align(struct intel_batchbuffer *batch, uint32_t align)
  56 {
  57         uint32_t offset = batch_used(batch);
  58         offset = ALIGN(offset, align);
  59         batch->ptr = batch->buffer + offset;
  60         return offset;
  61 }
  62
  63 static void *
  64 batch_alloc(struct intel_batchbuffer *batch, uint32_t size, uint32_t align)
  65 {
  66         uint32_t offset = batch_align(batch, align);
  67         batch->ptr += size;
  68         return memset(batch->buffer + offset, 0, size);
  69 }
  70
  71 static uint32_t
  72 batch_offset(struct intel_batchbuffer *batch, void *ptr)
  73 {
  74         return (uint8_t *)ptr - batch->buffer;
  75 }
  76
  77 static uint32_t
  78 batch_copy(struct intel_batchbuffer *batch, const void *ptr, uint32_t size, uint32_t align)
  79 {
  80         return batch_offset(batch, memcpy(batch_alloc(batch, size, align), ptr, size));
  81 }
  82
  83 static void
  84 gen6_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end)
  85 {
  86         int ret;
  87
  88         ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer);
  89         if (ret == 0)
  90                 ret = drm_intel_bo_mrb_exec(batch->bo, batch_end,
  91                                             NULL, 0, 0, 0);
  92         assert(ret == 0);
  93 }
  94
  95 /* Mostly copy+paste from gen6, except height, width, pitch moved */
  96 static uint32_t
  97 gen8_bind_buf(struct intel_batchbuffer *batch, struct scratch_buf *buf,
  98               uint32_t format, int is_dst) {
  99         struct gen8_surface_state *ss;
 100         uint32_t write_domain, read_domain;
 101         int ret;
 102
 103         if (is_dst) {
 104                 write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
 105         } else {
 106                 write_domain = 0;
 107                 read_domain = I915_GEM_DOMAIN_SAMPLER;
 108         }
 109
 110         ss = batch_alloc(batch, sizeof(*ss), 32);
 111         ss->ss0.surface_type = GEN6_SURFACE_2D;
 112         ss->ss0.surface_format = format;
 113         ss->ss0.render_cache_read_write = 1;
 114         if (buf->tiling == I915_TILING_X)
 115                 ss->ss0.tiled_mode = 2;
 116         else if (buf->tiling == I915_TILING_Y)
 117                 ss->ss0.tiled_mode = 3;
 118
 119         ss->ss8.base_addr = buf->bo->offset;
 120
 121         ret = drm_intel_bo_emit_reloc(batch->bo,
 122                                       batch_offset(batch, ss) + 4,
 123                                       buf->bo, 0,
 124                                       read_domain, write_domain);
 125         assert(ret == 0);
 126
 127         ss->ss2.height = buf_height(buf) - 1;
 128         ss->ss2.width  = buf_width(buf) - 1;
 129         ss->ss3.pitch  = buf->stride - 1;
 130
 131         ss->ss7.shader_chanel_select_a = 4;
 132         ss->ss7.shader_chanel_select_g = 5;
 133         ss->ss7.shader_chanel_select_b = 6;
 134         ss->ss7.shader_chanel_select_a = 7;
 135
 136         return batch_offset(batch, ss);
 137 }
 138
 139 static uint32_t
 140 gen8_bind_surfaces(struct intel_batchbuffer *batch,
 141                    struct scratch_buf *src,
 142                    struct scratch_buf *dst) {
 143         uint32_t *binding_table;
 144
 145         binding_table = batch_alloc(batch, 8, 32);
 146
 147         binding_table[0] =
 148                 gen8_bind_buf(batch, dst, GEN6_SURFACEFORMAT_B8G8R8A8_UNORM, 1);
 149         binding_table[1] =
 150                 gen8_bind_buf(batch, src, GEN6_SURFACEFORMAT_B8G8R8A8_UNORM, 0);
 151
 152         return batch_offset(batch, binding_table);
 153 }
 154
 155 /* Mostly copy+paste from gen6, except wrap modes moved */
 156 static uint32_t
 157 gen8_create_sampler(struct intel_batchbuffer *batch) {
 158         struct gen8_sampler_state *ss;
 159
 160         ss = batch_alloc(batch, sizeof(*ss), 32);
 161
 162         ss->ss0.min_filter = GEN6_MAPFILTER_NEAREST;
 163         ss->ss0.mag_filter = GEN6_MAPFILTER_NEAREST;
 164         ss->ss3.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
 165         ss->ss3.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
 166         ss->ss3.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
 167
 168         /* I've experimented with non-normalized coordinates and using the LD
 169          * sampler fetch, but couldn't make it work. */
 170         ss->ss3.non_normalized_coord = 0;
 171
 172         return batch_offset(batch, ss);
 173 }
 174
 175 /**
 176  * gen7_fill_vertex_buffer_data populate vertex buffer with data.
 177  *
 178  * The vertex buffer consists of 3 vertices to construct a RECTLIST. The 4th
 179  * vertex is implied (automatically derived by the HW). Each element has the
 180  * destination offset, and the normalized texture offset (src). The rectangle
 181  * itself will span the entire subsurface to be copied.
 182  *
 183  * see gen6_emit_vertex_elements
 184  */
 185 static uint32_t
 186 gen7_fill_vertex_buffer_data(struct intel_batchbuffer *batch,
 187                              struct scratch_buf *src,
 188                              uint32_t src_x, uint32_t src_y,
 189                              uint32_t dst_x, uint32_t dst_y,
 190                              uint32_t width, uint32_t height) {
 191         void *ret;
 192
 193         ret = batch->ptr;
 194
 195         emit_vertex_2s(batch, dst_x + width, dst_y + height);
 196         emit_vertex_normalized(batch, src_x + width, buf_width(src));
 197         emit_vertex_normalized(batch, src_y + height, buf_height(src));
 198
 199         emit_vertex_2s(batch, dst_x, dst_y + height);
 200         emit_vertex_normalized(batch, src_x, buf_width(src));
 201         emit_vertex_normalized(batch, src_y + height, buf_height(src));
 202
 203         emit_vertex_2s(batch, dst_x, dst_y);
 204         emit_vertex_normalized(batch, src_x, buf_width(src));
 205         emit_vertex_normalized(batch, src_y, buf_height(src));
 206
 207         return batch_offset(batch, ret);
 208 }
 209
 210 /**
 211  * gen6_emit_vertex_elements - The vertex elements describe the contents of the
 212  * vertex buffer. We pack the vertex buffer in a semi weird way, conforming to
 213  * what gen6_rendercopy did. The most straightforward would be to store
 214  * everything as floats.
 215  *
 216  * see gen7_fill_vertex_buffer_data() for where the corresponding elements are
 217  * packed.
 218  */
 219 static void
 220 gen6_emit_vertex_elements(struct intel_batchbuffer *batch) {
 221         /*
 222          * The VUE layout
 223          *    dword 0-3: pad (0, 0, 0. 0)
 224          *    dword 4-7: position (x, y, 0, 1.0),
 225          *    dword 8-11: texture coordinate 0 (u0, v0, 0, 1.0)
 226          */
 227         OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | (3 * 2 + 1 - 2));
 228
 229         /* Element state 0. These are 4 dwords of 0 required for the VUE format.
 230          * We don't really know or care what they do.
 231          */
 232         OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
 233                   GEN6_SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT |
 234                   0 << VE0_OFFSET_SHIFT); /* we specify 0, but it's really does not exist */
 235         OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
 236                   GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
 237                   GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
 238                   GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
 239
 240         /* Element state 1 - Our "destination" vertices. These are passed down
 241          * through the pipeline, and eventually make it to the pixel shader as
 242          * the offsets in the destination surface. It's packed as the 16
 243          * signed/scaled because of gen6 rendercopy. I see no particular reason
 244          * for doing this though.
 245          */
 246         OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
 247                   GEN6_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
 248                   0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */
 249         OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
 250                   GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
 251                   GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
 252                   GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
 253
 254         /* Element state 2. Last but not least we store the U,V components as
 255          * normalized floats. These will be used in the pixel shader to sample
 256          * from the source buffer.
 257          */
 258         OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
 259                   GEN6_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT |
 260                   4 << VE0_OFFSET_SHIFT);       /* offset vb in bytes */
 261         OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
 262                   GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
 263                   GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
 264                   GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
 265 }
 266
 267 /**
 268  * gen7_emit_vertex_buffer emit the vertex buffers command
 269  *
 270  * @batch
 271  * @offset - bytw offset within the @batch where the vertex buffer starts.
 272  */
 273 static void gen7_emit_vertex_buffer(struct intel_batchbuffer *batch,
 274                                     uint32_t offset) {
 275         OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | (4 * 1 - 1));
 276         OUT_BATCH(0 << VB0_BUFFER_INDEX_SHIFT | /* VB 0th index */
 277                   VB0_VERTEXDATA |
 278                   GEN7_VB0_BUFFER_ADDR_MOD_EN | /* Address Modify Enable */
 279                   VERTEX_SIZE << VB0_BUFFER_PITCH_SHIFT);
 280         OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, offset);
 281         OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, offset + (VERTEX_SIZE * 3) - 1);
 282         OUT_BATCH(0);
 283 }
 284
 285 static uint32_t
 286 gen6_create_cc_state(struct intel_batchbuffer *batch)
 287 {
 288         struct gen6_color_calc_state *cc_state;
 289         cc_state = batch_alloc(batch, sizeof(*cc_state), 64);
 290         return batch_offset(batch, cc_state);
 291 }
 292
 293 static uint32_t
 294 gen8_create_blend_state(struct intel_batchbuffer *batch)
 295 {
 296         struct gen8_blend_state *blend;
 297         int i;
 298
 299         blend = batch_alloc(batch, sizeof(*blend), 64);
 300         for (i = 0; i < 16; i++) {
 301                 blend->bs[i].pre_blend_color_clamp = 1;
 302                 blend->bs[i].color_buffer_blend = 0;
 303         }
 304         return batch_offset(batch, blend);
 305 }
 306
 307 static uint32_t
 308 gen6_create_cc_viewport(struct intel_batchbuffer *batch)
 309 {
 310         struct gen6_cc_viewport *vp;
 311
 312         vp = batch_alloc(batch, sizeof(*vp), 32);
 313         /* XXX I don't understand this */
 314         vp->min_depth = -1.e35;
 315         vp->max_depth = 1.e35;
 316         return batch_offset(batch, vp);
 317 }
 318
 319 static uint32_t
 320 gen7_create_sf_clip_viewport(struct intel_batchbuffer *batch) {
 321         /* XXX these are likely not needed */
 322         struct gen7_sf_clip_viewport *scv_state;
 323         scv_state = batch_alloc(batch, sizeof(*scv_state), 64);
 324         scv_state->guardband.xmin = 0;
 325         scv_state->guardband.xmax = 1.0f;
 326         scv_state->guardband.ymin = 0;
 327         scv_state->guardband.ymax = 1.0f;
 328         return batch_offset(batch, scv_state);
 329 }
 330
 331 static uint32_t
 332 gen6_create_scissor_rect(struct intel_batchbuffer *batch)
 333 {
 334         struct gen6_scissor_rect *scissor;
 335         scissor = batch_alloc(batch, sizeof(*scissor), 64);
 336         return batch_offset(batch, scissor);
 337 }
 338
 339
 340
 341
 342
 343 static void
 344 gen6_emit_sip(struct intel_batchbuffer *batch) {
 345         OUT_BATCH(GEN6_STATE_SIP | 0);
 346         OUT_BATCH(0);
 347 }
 348
 349 static void
 350 gen7_emit_push_constants(struct intel_batchbuffer *batch) {
 351         OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS);
 352         OUT_BATCH(0);
 353         OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS);
 354         OUT_BATCH(0);
 355         OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS);
 356         OUT_BATCH(0);
 357         OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS);
 358         OUT_BATCH(0);
 359         OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS);
 360         OUT_BATCH(0);
 361 }
 362
 363 static void
 364 gen7_emit_state_base_address(struct intel_batchbuffer *batch) {
 365         OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (10 - 2));
 366         /* general (stateless) */
 367         /* surface */
 368         /* instruction */
 369         /* indirect */
 370         /* dynamic */
 371         OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
 372         OUT_RELOC(batch->bo, I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY);
 373         OUT_RELOC(batch->bo, I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION,
 374                   0, BASE_ADDRESS_MODIFY);
 375         OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
 376         OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
 377
 378         OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
 379         OUT_BATCH(0xfffff000 | BASE_ADDRESS_MODIFY); // copied from mesa
 380         OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
 381         OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
 382 }
 383
 384 static void
 385 gen7_emit_urb(struct intel_batchbuffer *batch) {
 386         /* XXX: Min valid values from mesa */
 387         const int vs_entries = 32;
 388         const int vs_size = 2;
 389         const int vs_start = 2;
 390
 391         OUT_BATCH(GEN7_3DSTATE_URB_VS);
 392         OUT_BATCH(vs_entries | ((vs_size - 1) << 16) | (vs_start << 25));
 393         OUT_BATCH(GEN7_3DSTATE_URB_GS);
 394         OUT_BATCH(vs_start << 25);
 395         OUT_BATCH(GEN7_3DSTATE_URB_HS);
 396         OUT_BATCH(vs_start << 25);
 397         OUT_BATCH(GEN7_3DSTATE_URB_DS);
 398         OUT_BATCH(vs_start << 25);
 399 }
 400
 401 static void
 402 gen8_emit_cc(struct intel_batchbuffer *batch) {
 403         OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS);
 404         OUT_BATCH(cc.blend_state | 1);
 405
 406         OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS);
 407         OUT_BATCH(cc.cc_state | 1);
 408 }
 409
 410 static void
 411 gen7_emit_multisample(struct intel_batchbuffer *batch) {
 412         OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | 2);
 413         OUT_BATCH(0);
 414         OUT_BATCH(0);
 415         OUT_BATCH(0);
 416
 417         OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK);
 418         OUT_BATCH(1);
 419 }
 420
 421 static void
 422 gen7_emit_vs(struct intel_batchbuffer *batch) {
 423         OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS);
 424         OUT_BATCH(0);
 425
 426         OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS);
 427         OUT_BATCH(0);
 428
 429         OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | (7-2));
 430         OUT_BATCH(0);
 431         OUT_BATCH(0);
 432         OUT_BATCH(0);
 433         OUT_BATCH(0);
 434         OUT_BATCH(0);
 435         OUT_BATCH(0);
 436
 437         OUT_BATCH(GEN6_3DSTATE_VS | (6-2));
 438         OUT_BATCH(0);
 439         OUT_BATCH(0);
 440         OUT_BATCH(0);
 441         OUT_BATCH(0);
 442         OUT_BATCH(0);
 443 }
 444
 445 static void
 446 gen7_emit_hs(struct intel_batchbuffer *batch) {
 447         OUT_BATCH(GEN7_3DSTATE_CONSTANT_HS | (7-2));
 448         OUT_BATCH(0);
 449         OUT_BATCH(0);
 450         OUT_BATCH(0);
 451         OUT_BATCH(0);
 452         OUT_BATCH(0);
 453         OUT_BATCH(0);
 454
 455         OUT_BATCH(GEN7_3DSTATE_HS | (7-2));
 456         OUT_BATCH(0);
 457         OUT_BATCH(0);
 458         OUT_BATCH(0);
 459         OUT_BATCH(0);
 460         OUT_BATCH(0);
 461         OUT_BATCH(0);
 462
 463         OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS);
 464         OUT_BATCH(0);
 465
 466         OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS);
 467         OUT_BATCH(0);
 468 }
 469
 470 static void
 471 gen7_emit_gs(struct intel_batchbuffer *batch) {
 472         OUT_BATCH(GEN7_3DSTATE_CONSTANT_GS | (7-2));
 473         OUT_BATCH(0);
 474         OUT_BATCH(0);
 475         OUT_BATCH(0);
 476         OUT_BATCH(0);
 477         OUT_BATCH(0);
 478         OUT_BATCH(0);
 479
 480         OUT_BATCH(GEN7_3DSTATE_GS | (7-2));
 481         OUT_BATCH(0);
 482         OUT_BATCH(0);
 483         OUT_BATCH(0);
 484         OUT_BATCH(0);
 485         OUT_BATCH(0);
 486         OUT_BATCH(0);
 487
 488         OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS);
 489         OUT_BATCH(0);
 490
 491         OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS);
 492         OUT_BATCH(0);
 493 }
 494
 495 static void
 496 gen7_emit_ds(struct intel_batchbuffer *batch) {
 497         OUT_BATCH(GEN7_3DSTATE_CONSTANT_DS | (7-2));
 498         OUT_BATCH(0);
 499         OUT_BATCH(0);
 500         OUT_BATCH(0);
 501         OUT_BATCH(0);
 502         OUT_BATCH(0);
 503         OUT_BATCH(0);
 504
 505         OUT_BATCH(GEN7_3DSTATE_DS | (6-2));
 506         OUT_BATCH(0);
 507         OUT_BATCH(0);
 508         OUT_BATCH(0);
 509         OUT_BATCH(0);
 510         OUT_BATCH(0);
 511
 512         OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS);
 513         OUT_BATCH(0);
 514
 515         OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS);
 516         OUT_BATCH(0);
 517 }
 518
 519 static void
 520 gen7_emit_null_state(struct intel_batchbuffer *batch) {
 521         gen7_emit_hs(batch);
 522         OUT_BATCH(GEN7_3DSTATE_TE | (4-2));
 523         OUT_BATCH(0);
 524         OUT_BATCH(0);
 525         OUT_BATCH(0);
 526         gen7_emit_gs(batch);
 527         gen7_emit_ds(batch);
 528         gen7_emit_vs(batch);
 529 }
 530
 531 static void
 532 gen7_emit_clip(struct intel_batchbuffer *batch) {
 533         OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2));
 534         OUT_BATCH(0);
 535         OUT_BATCH(0); /*  pass-through */
 536         OUT_BATCH(0);
 537 }
 538
 539 static void
 540 gen7_emit_sf(struct intel_batchbuffer *batch) {
 541         OUT_BATCH(GEN7_3DSTATE_SBE | (14 - 2));
 542 #ifdef GPU_HANG
 543         OUT_BATCH(0 << 22 | 1 << 11 | 1 << 4);
 544 #else
 545         OUT_BATCH(1 << 22 | 1 << 11 | 1 << 4);
 546 #endif
 547         OUT_BATCH(0);
 548         OUT_BATCH(0);
 549         OUT_BATCH(0);
 550         OUT_BATCH(0);
 551         OUT_BATCH(0);
 552         OUT_BATCH(0);
 553         OUT_BATCH(0);
 554         OUT_BATCH(0);
 555         OUT_BATCH(0);
 556         OUT_BATCH(0);
 557         OUT_BATCH(0);
 558         OUT_BATCH(0);
 559
 560         OUT_BATCH(GEN6_3DSTATE_SF | (7 - 2));
 561         OUT_BATCH(0);
 562         OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
 563 //      OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
 564         OUT_BATCH(0);
 565         OUT_BATCH(0);
 566         OUT_BATCH(0);
 567         OUT_BATCH(0);
 568 }
 569
 570 static void
 571 gen8_emit_ps(struct intel_batchbuffer *batch, uint32_t kernel) {
 572         const int max_threads = 86;
 573
 574         OUT_BATCH(GEN6_3DSTATE_WM | (3 - 2));
 575         OUT_BATCH(GEN7_WM_DISPATCH_ENABLE |
 576                   /* XXX: I don't understand the BARYCENTRIC stuff, but it
 577                    * appears we need it to put our setup data in the place we
 578                    * expect (g6, see below) */
 579                   GEN7_3DSTATE_PS_PERSPECTIVE_PIXEL_BARYCENTRIC);
 580         OUT_BATCH(0);
 581
 582         OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS | (7-2));
 583         OUT_BATCH(0);
 584         OUT_BATCH(0);
 585         OUT_BATCH(0);
 586         OUT_BATCH(0);
 587         OUT_BATCH(0);
 588         OUT_BATCH(0);
 589
 590         OUT_BATCH(GEN7_3DSTATE_PS | (10-2));
 591         OUT_BATCH(kernel);
 592         OUT_BATCH(0); /* kernel hi */
 593         OUT_BATCH(1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF |
 594                   2 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 595         OUT_BATCH(0); /* scratch space stuff */
 596         OUT_BATCH(0); /* scratch hi */
 597         OUT_BATCH((max_threads - 1) << GEN7_3DSTATE_WM_MAX_THREADS_SHIFT |
 598                   GEN7_3DSTATE_PS_ATTRIBUTE_ENABLED |
 599                   GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
 600         OUT_BATCH(6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT);
 601         OUT_BATCH(0); // kernel 1
 602         OUT_BATCH(0); /* kernel 1 hi */
 603 }
 604
 605 static void
 606 gen8_emit_depth(struct intel_batchbuffer *batch) {
 607         OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7-2));
 608         OUT_BATCH(0);
 609         OUT_BATCH(0);
 610         OUT_BATCH(0);
 611         OUT_BATCH(0);
 612         OUT_BATCH(0);
 613         OUT_BATCH(0);
 614
 615         OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER | (3-2));
 616         OUT_BATCH(0);
 617         OUT_BATCH(0);
 618
 619         OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER | (3-2));
 620         OUT_BATCH(0);
 621         OUT_BATCH(0);
 622 }
 623
 624 static void
 625 gen7_emit_clear(struct intel_batchbuffer *batch) {
 626         OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS | (3-2));
 627         OUT_BATCH(0);
 628         OUT_BATCH(1); // clear valid
 629 }
 630
 631 static void
 632 gen6_emit_drawing_rectangle(struct intel_batchbuffer *batch, struct scratch_buf *dst)
 633 {
 634         OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
 635         OUT_BATCH(0);
 636         OUT_BATCH((buf_height(dst) - 1) << 16 | (buf_width(dst) - 1));
 637         OUT_BATCH(0);
 638 }
 639
 640 /* Vertex elements MUST be defined before this according to spec */
 641 static void gen7_emit_primitive(struct intel_batchbuffer *batch, uint32_t offset)
 642 {
 643         OUT_BATCH(GEN6_3DPRIMITIVE | (7-2));
 644         OUT_BATCH(_3DPRIM_RECTLIST);
 645         OUT_BATCH(3);   /* vertex count */
 646         OUT_BATCH(0);   /*  We're specifying this instead with offset in GEN6_3DSTATE_VERTEX_BUFFERS */
 647         OUT_BATCH(1);   /* single instance */
 648         OUT_BATCH(0);   /* start instance location */
 649         OUT_BATCH(0);   /* index buffer offset, ignored */
 650 }
 651
 652 /* The general rule is if it's named gen6 it is directly copied from
 653  * gen6_render_copyfunc.
 654  *
 655  * This sets up most of the 3d pipeline, and most of that to NULL state. The
 656  * docs aren't specific about exactly what must be set up NULL, but the general
 657  * rule is we could be run at any time, and so the most state we set to NULL,
 658  * the better our odds of success.
 659  *
 660  * +---------------+ <---- 4096
 661  * |       ^       |
 662  * |       |       |
 663  * |    various    |
 664  * |      state    |
 665  * |       |       |
 666  * |_______|_______| <---- 2048 + ?
 667  * |       ^       |
 668  * |       |       |
 669  * |   batch       |
 670  * |    commands   |
 671  * |       |       |
 672  * |       |       |
 673  * +---------------+ <---- 0 + ?
 674  *
 675  * The batch commands point to state within tthe batch, so all state offsets should be
 676  * 0 < offset < 4096. Both commands and state build upwards, and are constructed
 677  * in that order. This means too many batch commands can delete state if not
 678  * careful.
 679  *
 680  */
 681
 682 #define BATCH_STATE_SPLIT 2048
 683 void gen8_render_copyfunc(struct intel_batchbuffer *batch,
 684                           struct scratch_buf *src, unsigned src_x, unsigned src_y,
 685                           unsigned width, unsigned height,
 686                           struct scratch_buf *dst, unsigned dst_x, unsigned dst_y)
 687 {
 688         uint32_t ps_sampler_state, ps_kernel_off, ps_binding_table;
 689         uint32_t scissor_state;
 690         uint32_t vertex_buffer;
 691         uint32_t batch_end;
 692
 693         intel_batchbuffer_flush(batch);
 694
 695         batch_align(batch, 8);
 696
 697         batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
 698
 699         ps_binding_table  = gen8_bind_surfaces(batch, src, dst);
 700         ps_sampler_state  = gen8_create_sampler(batch);
 701         ps_kernel_off = batch_copy(batch, ps_kernel, sizeof(ps_kernel), 64);
 702         vertex_buffer = gen7_fill_vertex_buffer_data(batch, src, src_x, src_y, dst_x, dst_y, width, height);
 703         cc.cc_state = gen6_create_cc_state(batch);
 704         cc.blend_state = gen8_create_blend_state(batch);
 705         viewport.cc_state = gen6_create_cc_viewport(batch);
 706         viewport.sf_clip_state = gen7_create_sf_clip_viewport(batch);
 707         scissor_state = gen6_create_scissor_rect(batch);
 708         /* TODO: theree is other state which isn't setup */
 709
 710         assert(batch->ptr < &batch->buffer[4095]);
 711
 712         batch->ptr = batch->buffer;
 713
 714         /* Start emitting the commands. The order roughly follows the mesa blorp
 715          * order */
 716         OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D);
 717
 718         gen6_emit_sip(batch);
 719
 720         gen7_emit_push_constants(batch);
 721
 722         gen7_emit_state_base_address(batch);
 723
 724         OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC);
 725         OUT_BATCH(viewport.cc_state);
 726         OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP);
 727         OUT_BATCH(viewport.sf_clip_state);
 728
 729         gen7_emit_urb(batch);
 730
 731         gen8_emit_cc(batch);
 732
 733         gen7_emit_multisample(batch);
 734
 735         gen7_emit_null_state(batch);
 736
 737         OUT_BATCH(GEN7_3DSTATE_STREAMOUT | 1);
 738         OUT_BATCH(0);
 739         OUT_BATCH(0);
 740
 741         gen7_emit_clip(batch);
 742
 743         gen7_emit_sf(batch);
 744
 745         OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS);
 746         OUT_BATCH(ps_binding_table);
 747
 748         OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS);
 749         OUT_BATCH(ps_sampler_state);
 750
 751         gen8_emit_ps(batch, ps_kernel_off);
 752
 753         OUT_BATCH(GEN6_3DSTATE_SCISSOR_STATE_POINTERS);
 754         OUT_BATCH(scissor_state);
 755
 756         gen8_emit_depth(batch);
 757
 758         gen7_emit_clear(batch);
 759
 760         gen6_emit_drawing_rectangle(batch, dst);
 761
 762         gen7_emit_vertex_buffer(batch, vertex_buffer);
 763         gen6_emit_vertex_elements(batch);
 764
 765         gen7_emit_primitive(batch, vertex_buffer);
 766
 767         OUT_BATCH(MI_BATCH_BUFFER_END);
 768
 769         batch_end = batch_align(batch, 8);
 770         assert(batch_end < BATCH_STATE_SPLIT);
 771
 772         dump_batch(batch);
 773
 774         gen6_render_flush(batch, batch_end);
 775         intel_batchbuffer_reset(batch);
 776 }
 777
 778 #if DEBUG_RENDERCPY
 779 static void dump_batch(struct intel_batchbuffer *batch) {
 780         int fd = open("/tmp/i965-batchbuffers.dump", O_WRONLY | O_CREAT,  0666);
 781         if (fd != -1) {
 782                 write(fd, batch->buffer, 4096);
 783                 fd = close(fd);
 784         }
 785 }
 786 #endif