lib/rendercopy_gen7.c

   1 #include <assert.h>
   2 #include <stdlib.h>
   3 #include <sys/ioctl.h>
   4 #include <stdio.h>
   5 #include <string.h>
   6 #include <assert.h>
   7 #include <fcntl.h>
   8 #include <inttypes.h>
   9 #include <errno.h>
  10 #include <sys/stat.h>
  11 #include <sys/time.h>
  12 #include <getopt.h>
  13 #include "drm.h"
  14 #include "i915_drm.h"
  15 #include "drmtest.h"
  16 #include "intel_bufmgr.h"
  17 #include "intel_batchbuffer.h"
  18 #include "intel_io.h"
  19 #include "intel_chipset.h"
  20 #include "rendercopy.h"
  21 #include "gen7_render.h"
  22 #include "intel_reg.h"
  23
  24
  25 static const uint32_t ps_kernel[][4] = {
  26         { 0x0080005a, 0x2e2077bd, 0x000000c0, 0x008d0040 },
  27         { 0x0080005a, 0x2e6077bd, 0x000000d0, 0x008d0040 },
  28         { 0x02800031, 0x21801fa9, 0x008d0e20, 0x08840001 },
  29         { 0x00800001, 0x2e2003bd, 0x008d0180, 0x00000000 },
  30         { 0x00800001, 0x2e6003bd, 0x008d01c0, 0x00000000 },
  31         { 0x00800001, 0x2ea003bd, 0x008d0200, 0x00000000 },
  32         { 0x00800001, 0x2ee003bd, 0x008d0240, 0x00000000 },
  33         { 0x05800031, 0x20001fa8, 0x008d0e20, 0x90031000 },
  34 };
  35
  36 static uint32_t
  37 batch_used(struct intel_batchbuffer *batch)
  38 {
  39         return batch->state - batch->buffer;
  40 }
  41
  42 static uint32_t
  43 batch_align(struct intel_batchbuffer *batch, uint32_t align)
  44 {
  45         uint32_t offset = batch_used(batch);
  46         offset = ALIGN(offset, align);
  47         batch->state = batch->buffer + offset;
  48         return offset;
  49 }
  50
  51 static void *
  52 batch_alloc(struct intel_batchbuffer *batch, uint32_t size, uint32_t align)
  53 {
  54         uint32_t offset = batch_align(batch, align);
  55         batch->state += size;
  56         return memset(batch->buffer + offset, 0, size);
  57 }
  58
  59 static uint32_t
  60 batch_offset(struct intel_batchbuffer *batch, void *ptr)
  61 {
  62         return (uint8_t *)ptr - batch->buffer;
  63 }
  64
  65 static uint32_t
  66 batch_copy(struct intel_batchbuffer *batch, const void *ptr, uint32_t size, uint32_t align)
  67 {
  68         return batch_offset(batch, memcpy(batch_alloc(batch, size, align), ptr, size));
  69 }
  70
  71 static void
  72 gen7_render_flush(struct intel_batchbuffer *batch,
  73                   drm_intel_context *context, uint32_t batch_end)
  74 {
  75         int ret;
  76
  77         ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer);
  78         if (ret == 0)
  79                 ret = drm_intel_gem_bo_context_exec(batch->bo, context,
  80                                                     batch_end, 0);
  81         assert(ret == 0);
  82 }
  83
  84 static uint32_t
  85 gen7_tiling_bits(uint32_t tiling)
  86 {
  87         switch (tiling) {
  88         default: assert(0);
  89         case I915_TILING_NONE: return 0;
  90         case I915_TILING_X: return GEN7_SURFACE_TILED;
  91         case I915_TILING_Y: return GEN7_SURFACE_TILED | GEN7_SURFACE_TILED_Y;
  92         }
  93 }
  94
  95 static uint32_t
  96 gen7_bind_buf(struct intel_batchbuffer *batch,
  97               struct igt_buf *buf,
  98               uint32_t format,
  99               int is_dst)
 100 {
 101         uint32_t *ss;
 102         uint32_t write_domain, read_domain;
 103         int ret;
 104
 105         if (is_dst) {
 106                 write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
 107         } else {
 108                 write_domain = 0;
 109                 read_domain = I915_GEM_DOMAIN_SAMPLER;
 110         }
 111
 112         ss = batch_alloc(batch, 8 * sizeof(*ss), 32);
 113
 114         ss[0] = (GEN7_SURFACE_2D << GEN7_SURFACE_TYPE_SHIFT |
 115                  gen7_tiling_bits(buf->tiling) |
 116                 format << GEN7_SURFACE_FORMAT_SHIFT);
 117         ss[1] = buf->bo->offset;
 118         ss[2] = ((igt_buf_width(buf) - 1)  << GEN7_SURFACE_WIDTH_SHIFT |
 119                  (igt_buf_height(buf) - 1) << GEN7_SURFACE_HEIGHT_SHIFT);
 120         ss[3] = (buf->stride - 1) << GEN7_SURFACE_PITCH_SHIFT;
 121         ss[4] = 0;
 122         ss[5] = 0;
 123         ss[6] = 0;
 124         ss[7] = 0;
 125         if (IS_HASWELL(batch->devid))
 126                 ss[7] |= HSW_SURFACE_SWIZZLE(RED, GREEN, BLUE, ALPHA);
 127
 128         ret = drm_intel_bo_emit_reloc(batch->bo,
 129                                       batch_offset(batch, ss) + 4,
 130                                       buf->bo, 0,
 131                                       read_domain, write_domain);
 132         assert(ret == 0);
 133
 134         return batch_offset(batch, ss);
 135 }
 136
 137 static void
 138 gen7_emit_vertex_elements(struct intel_batchbuffer *batch)
 139 {
 140         OUT_BATCH(GEN7_3DSTATE_VERTEX_ELEMENTS |
 141                   ((2 * (1 + 2)) + 1 - 2));
 142
 143         OUT_BATCH(0 << GEN7_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN7_VE0_VALID |
 144                   GEN7_SURFACEFORMAT_R32G32B32A32_FLOAT << GEN7_VE0_FORMAT_SHIFT |
 145                   0 << GEN7_VE0_OFFSET_SHIFT);
 146
 147         OUT_BATCH(GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_0_SHIFT |
 148                   GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_1_SHIFT |
 149                   GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT |
 150                   GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_3_SHIFT);
 151
 152         /* x,y */
 153         OUT_BATCH(0 << GEN7_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN7_VE0_VALID |
 154                   GEN7_SURFACEFORMAT_R16G16_SSCALED << GEN7_VE0_FORMAT_SHIFT |
 155                   0 << GEN7_VE0_OFFSET_SHIFT); /* offsets vb in bytes */
 156         OUT_BATCH(GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_0_SHIFT |
 157                   GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_1_SHIFT |
 158                   GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT |
 159                   GEN7_VFCOMPONENT_STORE_1_FLT << GEN7_VE1_VFCOMPONENT_3_SHIFT);
 160
 161         /* s,t */
 162         OUT_BATCH(0 << GEN7_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN7_VE0_VALID |
 163                   GEN7_SURFACEFORMAT_R16G16_SSCALED << GEN7_VE0_FORMAT_SHIFT |
 164                   4 << GEN7_VE0_OFFSET_SHIFT);  /* offset vb in bytes */
 165         OUT_BATCH(GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_0_SHIFT |
 166                   GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_1_SHIFT |
 167                   GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT |
 168                   GEN7_VFCOMPONENT_STORE_1_FLT << GEN7_VE1_VFCOMPONENT_3_SHIFT);
 169 }
 170
 171 static uint32_t
 172 gen7_create_vertex_buffer(struct intel_batchbuffer *batch,
 173                           uint32_t src_x, uint32_t src_y,
 174                           uint32_t dst_x, uint32_t dst_y,
 175                           uint32_t width, uint32_t height)
 176 {
 177         uint16_t *v;
 178
 179         v = batch_alloc(batch, 12*sizeof(*v), 8);
 180
 181         v[0] = dst_x + width;
 182         v[1] = dst_y + height;
 183         v[2] = src_x + width;
 184         v[3] = src_y + height;
 185
 186         v[4] = dst_x;
 187         v[5] = dst_y + height;
 188         v[6] = src_x;
 189         v[7] = src_y + height;
 190
 191         v[8] = dst_x;
 192         v[9] = dst_y;
 193         v[10] = src_x;
 194         v[11] = src_y;
 195
 196         return batch_offset(batch, v);
 197 }
 198
 199 static void gen7_emit_vertex_buffer(struct intel_batchbuffer *batch,
 200                                     int src_x, int src_y,
 201                                     int dst_x, int dst_y,
 202                                     int width, int height)
 203 {
 204         uint32_t offset;
 205
 206         offset = gen7_create_vertex_buffer(batch,
 207                                            src_x, src_y,
 208                                            dst_x, dst_y,
 209                                            width, height);
 210
 211         OUT_BATCH(GEN7_3DSTATE_VERTEX_BUFFERS | (5 - 2));
 212         OUT_BATCH(0 << GEN7_VB0_BUFFER_INDEX_SHIFT |
 213                   GEN7_VB0_VERTEXDATA |
 214                   GEN7_VB0_ADDRESS_MODIFY_ENABLE |
 215                   4*2 << GEN7_VB0_BUFFER_PITCH_SHIFT);
 216
 217         OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, offset);
 218         OUT_BATCH(~0);
 219         OUT_BATCH(0);
 220 }
 221
 222 static uint32_t
 223 gen7_bind_surfaces(struct intel_batchbuffer *batch,
 224                    struct igt_buf *src,
 225                    struct igt_buf *dst)
 226 {
 227         uint32_t *binding_table;
 228
 229         binding_table = batch_alloc(batch, 8, 32);
 230
 231         binding_table[0] =
 232                 gen7_bind_buf(batch, dst, GEN7_SURFACEFORMAT_B8G8R8A8_UNORM, 1);
 233         binding_table[1] =
 234                 gen7_bind_buf(batch, src, GEN7_SURFACEFORMAT_B8G8R8A8_UNORM, 0);
 235
 236         return batch_offset(batch, binding_table);
 237 }
 238
 239 static void
 240 gen7_emit_binding_table(struct intel_batchbuffer *batch,
 241                         struct igt_buf *src,
 242                         struct igt_buf *dst)
 243 {
 244         OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2));
 245         OUT_BATCH(gen7_bind_surfaces(batch, src, dst));
 246 }
 247
 248 static void
 249 gen7_emit_drawing_rectangle(struct intel_batchbuffer *batch, struct igt_buf *dst)
 250 {
 251         OUT_BATCH(GEN7_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
 252         OUT_BATCH(0);
 253         OUT_BATCH((igt_buf_height(dst) - 1) << 16 | (igt_buf_width(dst) - 1));
 254         OUT_BATCH(0);
 255 }
 256
 257 static uint32_t
 258 gen7_create_blend_state(struct intel_batchbuffer *batch)
 259 {
 260         struct gen7_blend_state *blend;
 261
 262         blend = batch_alloc(batch, sizeof(*blend), 64);
 263
 264         blend->blend0.dest_blend_factor = GEN7_BLENDFACTOR_ZERO;
 265         blend->blend0.source_blend_factor = GEN7_BLENDFACTOR_ONE;
 266         blend->blend0.blend_func = GEN7_BLENDFUNCTION_ADD;
 267         blend->blend1.post_blend_clamp_enable = 1;
 268         blend->blend1.pre_blend_clamp_enable = 1;
 269
 270         return batch_offset(batch, blend);
 271 }
 272
 273 static void
 274 gen7_emit_state_base_address(struct intel_batchbuffer *batch)
 275 {
 276         OUT_BATCH(GEN7_STATE_BASE_ADDRESS | (10 - 2));
 277         OUT_BATCH(0);
 278         OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
 279         OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
 280         OUT_BATCH(0);
 281         OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
 282
 283         OUT_BATCH(0);
 284         OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
 285         OUT_BATCH(0);
 286         OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
 287 }
 288
 289 static uint32_t
 290 gen7_create_cc_viewport(struct intel_batchbuffer *batch)
 291 {
 292         struct gen7_cc_viewport *vp;
 293
 294         vp = batch_alloc(batch, sizeof(*vp), 32);
 295         vp->min_depth = -1.e35;
 296         vp->max_depth = 1.e35;
 297
 298         return batch_offset(batch, vp);
 299 }
 300
 301 static void
 302 gen7_emit_cc(struct intel_batchbuffer *batch)
 303 {
 304         OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
 305         OUT_BATCH(gen7_create_blend_state(batch));
 306
 307         OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
 308         OUT_BATCH(gen7_create_cc_viewport(batch));
 309 }
 310
 311 static uint32_t
 312 gen7_create_sampler(struct intel_batchbuffer *batch)
 313 {
 314         struct gen7_sampler_state *ss;
 315
 316         ss = batch_alloc(batch, sizeof(*ss), 32);
 317
 318         ss->ss0.min_filter = GEN7_MAPFILTER_NEAREST;
 319         ss->ss0.mag_filter = GEN7_MAPFILTER_NEAREST;
 320
 321         ss->ss3.r_wrap_mode = GEN7_TEXCOORDMODE_CLAMP;
 322         ss->ss3.s_wrap_mode = GEN7_TEXCOORDMODE_CLAMP;
 323         ss->ss3.t_wrap_mode = GEN7_TEXCOORDMODE_CLAMP;
 324
 325         ss->ss3.non_normalized_coord = 1;
 326
 327         return batch_offset(batch, ss);
 328 }
 329
 330 static void
 331 gen7_emit_sampler(struct intel_batchbuffer *batch)
 332 {
 333         OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2));
 334         OUT_BATCH(gen7_create_sampler(batch));
 335 }
 336
 337 static void
 338 gen7_emit_multisample(struct intel_batchbuffer *batch)
 339 {
 340         OUT_BATCH(GEN7_3DSTATE_MULTISAMPLE | (4 - 2));
 341         OUT_BATCH(GEN7_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
 342                   GEN7_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
 343         OUT_BATCH(0);
 344         OUT_BATCH(0);
 345
 346         OUT_BATCH(GEN7_3DSTATE_SAMPLE_MASK | (2 - 2));
 347         OUT_BATCH(1);
 348 }
 349
 350 static void
 351 gen7_emit_urb(struct intel_batchbuffer *batch)
 352 {
 353         OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
 354         OUT_BATCH(8); /* in 1KBs */
 355
 356         /* num of VS entries must be divisible by 8 if size < 9 */
 357         OUT_BATCH(GEN7_3DSTATE_URB_VS | (2 - 2));
 358         OUT_BATCH((64 << GEN7_URB_ENTRY_NUMBER_SHIFT) |
 359                   (2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
 360                   (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
 361
 362         OUT_BATCH(GEN7_3DSTATE_URB_HS | (2 - 2));
 363         OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
 364                   (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
 365
 366         OUT_BATCH(GEN7_3DSTATE_URB_DS | (2 - 2));
 367         OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
 368                   (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
 369
 370         OUT_BATCH(GEN7_3DSTATE_URB_GS | (2 - 2));
 371         OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
 372                   (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
 373 }
 374
 375 static void
 376 gen7_emit_vs(struct intel_batchbuffer *batch)
 377 {
 378         OUT_BATCH(GEN7_3DSTATE_VS | (6 - 2));
 379         OUT_BATCH(0); /* no VS kernel */
 380         OUT_BATCH(0);
 381         OUT_BATCH(0);
 382         OUT_BATCH(0);
 383         OUT_BATCH(0); /* pass-through */
 384 }
 385
 386 static void
 387 gen7_emit_hs(struct intel_batchbuffer *batch)
 388 {
 389         OUT_BATCH(GEN7_3DSTATE_HS | (7 - 2));
 390         OUT_BATCH(0); /* no HS kernel */
 391         OUT_BATCH(0);
 392         OUT_BATCH(0);
 393         OUT_BATCH(0);
 394         OUT_BATCH(0);
 395         OUT_BATCH(0); /* pass-through */
 396 }
 397
 398 static void
 399 gen7_emit_te(struct intel_batchbuffer *batch)
 400 {
 401         OUT_BATCH(GEN7_3DSTATE_TE | (4 - 2));
 402         OUT_BATCH(0);
 403         OUT_BATCH(0);
 404         OUT_BATCH(0);
 405 }
 406
 407 static void
 408 gen7_emit_ds(struct intel_batchbuffer *batch)
 409 {
 410         OUT_BATCH(GEN7_3DSTATE_DS | (6 - 2));
 411         OUT_BATCH(0);
 412         OUT_BATCH(0);
 413         OUT_BATCH(0);
 414         OUT_BATCH(0);
 415         OUT_BATCH(0);
 416 }
 417
 418 static void
 419 gen7_emit_gs(struct intel_batchbuffer *batch)
 420 {
 421         OUT_BATCH(GEN7_3DSTATE_GS | (7 - 2));
 422         OUT_BATCH(0); /* no GS kernel */
 423         OUT_BATCH(0);
 424         OUT_BATCH(0);
 425         OUT_BATCH(0);
 426         OUT_BATCH(0);
 427         OUT_BATCH(0); /* pass-through  */
 428 }
 429
 430 static void
 431 gen7_emit_streamout(struct intel_batchbuffer *batch)
 432 {
 433         OUT_BATCH(GEN7_3DSTATE_STREAMOUT | (3 - 2));
 434         OUT_BATCH(0);
 435         OUT_BATCH(0);
 436 }
 437
 438 static void
 439 gen7_emit_sf(struct intel_batchbuffer *batch)
 440 {
 441         OUT_BATCH(GEN7_3DSTATE_SF | (7 - 2));
 442         OUT_BATCH(0);
 443         OUT_BATCH(GEN7_3DSTATE_SF_CULL_NONE);
 444         OUT_BATCH(2 << GEN7_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
 445         OUT_BATCH(0);
 446         OUT_BATCH(0);
 447         OUT_BATCH(0);
 448 }
 449
 450 static void
 451 gen7_emit_sbe(struct intel_batchbuffer *batch)
 452 {
 453         OUT_BATCH(GEN7_3DSTATE_SBE | (14 - 2));
 454         OUT_BATCH(1 << GEN7_SBE_NUM_OUTPUTS_SHIFT |
 455                   1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 456                   1 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 457         OUT_BATCH(0);
 458         OUT_BATCH(0); /* dw4 */
 459         OUT_BATCH(0);
 460         OUT_BATCH(0);
 461         OUT_BATCH(0);
 462         OUT_BATCH(0); /* dw8 */
 463         OUT_BATCH(0);
 464         OUT_BATCH(0);
 465         OUT_BATCH(0);
 466         OUT_BATCH(0); /* dw12 */
 467         OUT_BATCH(0);
 468         OUT_BATCH(0);
 469 }
 470
 471 static void
 472 gen7_emit_ps(struct intel_batchbuffer *batch)
 473 {
 474         int threads;
 475
 476         if (IS_HASWELL(batch->devid))
 477                 threads = 40 << HSW_PS_MAX_THREADS_SHIFT | 1 << HSW_PS_SAMPLE_MASK_SHIFT;
 478         else
 479                 threads = 40 << IVB_PS_MAX_THREADS_SHIFT;
 480
 481         OUT_BATCH(GEN7_3DSTATE_PS | (8 - 2));
 482         OUT_BATCH(batch_copy(batch, ps_kernel, sizeof(ps_kernel), 64));
 483         OUT_BATCH(1 << GEN7_PS_SAMPLER_COUNT_SHIFT |
 484                   2 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 485         OUT_BATCH(0); /* scratch address */
 486         OUT_BATCH(threads |
 487                   GEN7_PS_16_DISPATCH_ENABLE |
 488                   GEN7_PS_ATTRIBUTE_ENABLE);
 489         OUT_BATCH(6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 490         OUT_BATCH(0);
 491         OUT_BATCH(0);
 492 }
 493
 494 static void
 495 gen7_emit_clip(struct intel_batchbuffer *batch)
 496 {
 497         OUT_BATCH(GEN7_3DSTATE_CLIP | (4 - 2));
 498         OUT_BATCH(0);
 499         OUT_BATCH(0); /* pass-through */
 500         OUT_BATCH(0);
 501
 502         OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2));
 503         OUT_BATCH(0);
 504 }
 505
 506 static void
 507 gen7_emit_wm(struct intel_batchbuffer *batch)
 508 {
 509         OUT_BATCH(GEN7_3DSTATE_WM | (3 - 2));
 510         OUT_BATCH(GEN7_WM_DISPATCH_ENABLE |
 511                   GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
 512         OUT_BATCH(0);
 513 }
 514
 515 static void
 516 gen7_emit_null_depth_buffer(struct intel_batchbuffer *batch)
 517 {
 518         OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
 519         OUT_BATCH(GEN7_SURFACE_NULL << GEN7_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT |
 520                   GEN7_DEPTHFORMAT_D32_FLOAT << GEN7_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
 521         OUT_BATCH(0); /* disable depth, stencil and hiz */
 522         OUT_BATCH(0);
 523         OUT_BATCH(0);
 524         OUT_BATCH(0);
 525         OUT_BATCH(0);
 526
 527         OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2));
 528         OUT_BATCH(0);
 529         OUT_BATCH(0);
 530 }
 531
 532 #define BATCH_STATE_SPLIT 2048
 533 void gen7_render_copyfunc(struct intel_batchbuffer *batch,
 534                           drm_intel_context *context,
 535                           struct igt_buf *src, unsigned src_x, unsigned src_y,
 536                           unsigned width, unsigned height,
 537                           struct igt_buf *dst, unsigned dst_x, unsigned dst_y)
 538 {
 539         uint32_t batch_end;
 540
 541         intel_batchbuffer_flush_with_context(batch, context);
 542
 543         batch->state = &batch->buffer[BATCH_STATE_SPLIT];
 544
 545         OUT_BATCH(GEN7_PIPELINE_SELECT | PIPELINE_SELECT_3D);
 546
 547         gen7_emit_state_base_address(batch);
 548         gen7_emit_multisample(batch);
 549         gen7_emit_urb(batch);
 550         gen7_emit_vs(batch);
 551         gen7_emit_hs(batch);
 552         gen7_emit_te(batch);
 553         gen7_emit_ds(batch);
 554         gen7_emit_gs(batch);
 555         gen7_emit_clip(batch);
 556         gen7_emit_sf(batch);
 557         gen7_emit_wm(batch);
 558         gen7_emit_streamout(batch);
 559         gen7_emit_null_depth_buffer(batch);
 560
 561         gen7_emit_cc(batch);
 562         gen7_emit_sampler(batch);
 563         gen7_emit_sbe(batch);
 564         gen7_emit_ps(batch);
 565         gen7_emit_vertex_elements(batch);
 566         gen7_emit_vertex_buffer(batch,
 567                                 src_x, src_y, dst_x, dst_y, width, height);
 568         gen7_emit_binding_table(batch, src, dst);
 569         gen7_emit_drawing_rectangle(batch, dst);
 570
 571         OUT_BATCH(GEN7_3DPRIMITIVE | (7- 2));
 572         OUT_BATCH(GEN7_3DPRIMITIVE_VERTEX_SEQUENTIAL | _3DPRIM_RECTLIST);
 573         OUT_BATCH(3);
 574         OUT_BATCH(0);
 575         OUT_BATCH(1);   /* single instance */
 576         OUT_BATCH(0);   /* start instance location */
 577         OUT_BATCH(0);   /* index buffer offset, ignored */
 578
 579         OUT_BATCH(MI_BATCH_BUFFER_END);
 580
 581         batch_end = batch->ptr - batch->buffer;
 582         batch_end = ALIGN(batch_end, 8);
 583         assert(batch_end < BATCH_STATE_SPLIT);
 584
 585         gen7_render_flush(batch, context, batch_end);
 586         intel_batchbuffer_reset(batch);
 587 }