1 #include <intel_bufmgr.h>
4 #include "media_fill.h"
5 #include "gen8_media.h"
12 static const uint32_t media_kernel[][4] = {
13 { 0x00400001, 0x20202288, 0x00000020, 0x00000000 },
14 { 0x00600001, 0x20800208, 0x008d0000, 0x00000000 },
15 { 0x00200001, 0x20800208, 0x00450040, 0x00000000 },
16 { 0x00000001, 0x20880608, 0x00000000, 0x000f000f },
17 { 0x00800001, 0x20a00208, 0x00000020, 0x00000000 },
18 { 0x00800001, 0x20e00208, 0x00000020, 0x00000000 },
19 { 0x00800001, 0x21200208, 0x00000020, 0x00000000 },
20 { 0x00800001, 0x21600208, 0x00000020, 0x00000000 },
21 { 0x0c800031, 0x24000a40, 0x0e000080, 0x120a8000 },
22 { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 },
23 { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 },
27 batch_used(struct intel_batchbuffer *batch)
29 return batch->ptr - batch->buffer;
33 batch_align(struct intel_batchbuffer *batch, uint32_t align)
35 uint32_t offset = batch_used(batch);
36 offset = ALIGN(offset, align);
37 batch->ptr = batch->buffer + offset;
42 batch_alloc(struct intel_batchbuffer *batch, uint32_t size, uint32_t align)
44 uint32_t offset = batch_align(batch, align);
46 return memset(batch->buffer + offset, 0, size);
50 batch_offset(struct intel_batchbuffer *batch, void *ptr)
52 return (uint8_t *)ptr - batch->buffer;
56 batch_copy(struct intel_batchbuffer *batch, const void *ptr, uint32_t size, uint32_t align)
58 return batch_offset(batch, memcpy(batch_alloc(batch, size, align), ptr, size));
62 gen8_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end)
66 ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer);
68 ret = drm_intel_bo_mrb_exec(batch->bo, batch_end,
74 gen8_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
77 uint8_t *curbe_buffer;
80 curbe_buffer = batch_alloc(batch, sizeof(uint32_t) * 8, 64);
81 offset = batch_offset(batch, curbe_buffer);
82 *curbe_buffer = color;
88 gen8_fill_surface_state(struct intel_batchbuffer *batch,
93 struct gen8_surface_state *ss;
94 uint32_t write_domain, read_domain, offset;
98 write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
101 read_domain = I915_GEM_DOMAIN_SAMPLER;
104 ss = batch_alloc(batch, sizeof(*ss), 64);
105 offset = batch_offset(batch, ss);
107 ss->ss0.surface_type = GEN8_SURFACE_2D;
108 ss->ss0.surface_format = format;
109 ss->ss0.render_cache_read_write = 1;
110 ss->ss0.vertical_alignment = 1; /* align 4 */
111 ss->ss0.horizontal_alignment = 1; /* align 4 */
113 if (buf->tiling == I915_TILING_X)
114 ss->ss0.tiled_mode = 2;
115 else if (buf->tiling == I915_TILING_Y)
116 ss->ss0.tiled_mode = 3;
118 ss->ss8.base_addr = buf->bo->offset;
120 ret = drm_intel_bo_emit_reloc(batch->bo,
121 batch_offset(batch, ss) + 8 * 4,
123 read_domain, write_domain);
124 igt_assert(ret == 0);
126 ss->ss2.height = igt_buf_height(buf) - 1;
127 ss->ss2.width = igt_buf_width(buf) - 1;
128 ss->ss3.pitch = buf->stride - 1;
130 ss->ss7.shader_chanel_select_r = 4;
131 ss->ss7.shader_chanel_select_g = 5;
132 ss->ss7.shader_chanel_select_b = 6;
133 ss->ss7.shader_chanel_select_a = 7;
139 gen8_fill_binding_table(struct intel_batchbuffer *batch,
142 uint32_t *binding_table, offset;
144 binding_table = batch_alloc(batch, 32, 64);
145 offset = batch_offset(batch, binding_table);
147 binding_table[0] = gen8_fill_surface_state(batch, dst, GEN8_SURFACEFORMAT_R8_UNORM, 1);
153 gen8_fill_media_kernel(struct intel_batchbuffer *batch,
154 const uint32_t kernel[][4],
159 offset = batch_copy(batch, kernel, size, 64);
165 gen8_fill_interface_descriptor(struct intel_batchbuffer *batch, struct igt_buf *dst)
167 struct gen8_interface_descriptor_data *idd;
169 uint32_t binding_table_offset, kernel_offset;
171 binding_table_offset = gen8_fill_binding_table(batch, dst);
172 kernel_offset = gen8_fill_media_kernel(batch, media_kernel, sizeof(media_kernel));
174 idd = batch_alloc(batch, sizeof(*idd), 64);
175 offset = batch_offset(batch, idd);
177 idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
179 idd->desc2.single_program_flow = 1;
180 idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754;
182 idd->desc3.sampler_count = 0; /* 0 samplers used */
183 idd->desc3.sampler_state_pointer = 0;
185 idd->desc4.binding_table_entry_count = 0;
186 idd->desc4.binding_table_pointer = (binding_table_offset >> 5);
188 idd->desc5.constant_urb_entry_read_offset = 0;
189 idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */
195 gen8_emit_state_base_address(struct intel_batchbuffer *batch)
197 OUT_BATCH(GEN8_STATE_BASE_ADDRESS | (16 - 2));
200 OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
203 /* stateless data port */
204 OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
207 OUT_RELOC(batch->bo, I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY);
211 OUT_RELOC(batch->bo, I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION,
212 0, BASE_ADDRESS_MODIFY);
220 OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
223 /* general state buffer size */
224 OUT_BATCH(0xfffff000 | 1);
225 /* dynamic state buffer size */
226 OUT_BATCH(1 << 12 | 1);
227 /* indirect object buffer size */
228 OUT_BATCH(0xfffff000 | 1);
229 /* intruction buffer size, must set modify enable bit, otherwise it may result in GPU hang */
230 OUT_BATCH(1 << 12 | 1);
234 gen8_emit_vfe_state(struct intel_batchbuffer *batch)
236 OUT_BATCH(GEN8_MEDIA_VFE_STATE | (9 - 2));
242 /* number of threads & urb entries */
248 /* urb entry size & curbe size */
259 gen8_emit_curbe_load(struct intel_batchbuffer *batch, uint32_t curbe_buffer)
261 OUT_BATCH(GEN8_MEDIA_CURBE_LOAD | (4 - 2));
263 /* curbe total data length */
265 /* curbe data start address, is relative to the dynamics base address */
266 OUT_BATCH(curbe_buffer);
270 gen8_emit_interface_descriptor_load(struct intel_batchbuffer *batch, uint32_t interface_descriptor)
272 OUT_BATCH(GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
274 /* interface descriptor data length */
275 OUT_BATCH(sizeof(struct gen8_interface_descriptor_data));
276 /* interface descriptor address, is relative to the dynamics base address */
277 OUT_BATCH(interface_descriptor);
281 gen8_emit_media_state_flush(struct intel_batchbuffer *batch)
283 OUT_BATCH(GEN8_MEDIA_STATE_FLUSH | (2 - 2));
288 gen8_emit_media_objects(struct intel_batchbuffer *batch,
289 unsigned x, unsigned y,
290 unsigned width, unsigned height)
294 for (i = 0; i < width / 16; i++) {
295 for (j = 0; j < height / 16; j++) {
296 OUT_BATCH(GEN8_MEDIA_OBJECT | (8 - 2));
298 /* interface descriptor offset */
301 /* without indirect data */
309 /* inline data (xoffset, yoffset) */
310 OUT_BATCH(x + i * 16);
311 OUT_BATCH(y + j * 16);
312 gen8_emit_media_state_flush(batch);
318 * This sets up the media pipeline,
320 * +---------------+ <---- 4096
326 * |_______|_______| <---- 2048 + ?
333 * +---------------+ <---- 0 + ?
337 #define BATCH_STATE_SPLIT 2048
340 gen8_media_fillfunc(struct intel_batchbuffer *batch,
342 unsigned x, unsigned y,
343 unsigned width, unsigned height,
346 uint32_t curbe_buffer, interface_descriptor;
349 intel_batchbuffer_flush(batch);
352 batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
354 curbe_buffer = gen8_fill_curbe_buffer_data(batch, color);
355 interface_descriptor = gen8_fill_interface_descriptor(batch, dst);
356 igt_assert(batch->ptr < &batch->buffer[4095]);
359 batch->ptr = batch->buffer;
360 OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
361 gen8_emit_state_base_address(batch);
363 gen8_emit_vfe_state(batch);
365 gen8_emit_curbe_load(batch, curbe_buffer);
367 gen8_emit_interface_descriptor_load(batch, interface_descriptor);
369 gen8_emit_media_objects(batch, x, y, width, height);
371 OUT_BATCH(MI_BATCH_BUFFER_END);
373 batch_end = batch_align(batch, 8);
374 igt_assert(batch_end < BATCH_STATE_SPLIT);
376 gen8_render_flush(batch, batch_end);
377 intel_batchbuffer_reset(batch);