1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/i810/i810_reg.h,v 1.13 2003/02/06 04:18:04 dawes Exp $ */
2 /**************************************************************************
4 Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
7 Permission is hereby granted, free of charge, to any person obtaining a
8 copy of this software and associated documentation files (the
9 "Software"), to deal in the Software without restriction, including
10 without limitation the rights to use, copy, modify, merge, publish,
11 distribute, sub license, and/or sell copies of the Software, and to
12 permit persons to whom the Software is furnished to do so, subject to
13 the following conditions:
15 The above copyright notice and this permission notice (including the
16 next paragraph) shall be included in all copies or substantial portions
19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
23 ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * Register names and fields for Intel graphics.
35 * Keith Whitwell <keith@tungstengraphics.com>
36 * Eric Anholt <eric@anholt.net>
38 * based on the i740 driver by
39 * Kevin E. Martin <kevin@precisioninsight.com>
47 /* I/O register offsets
49 #define SRX 0x3C4 /* p208 */
50 #define GRX 0x3CE /* p213 */
51 #define ARX 0x3C0 /* p224 */
53 /* VGA Color Palette Registers */
54 #define DACMASK 0x3C6 /* p232 */
55 #define DACSTATE 0x3C7 /* p232 */
56 #define DACRX 0x3C7 /* p233 */
57 #define DACWX 0x3C8 /* p233 */
58 #define DACDATA 0x3C9 /* p233 */
60 /* CRT Controller Registers (CRX) */
61 #define START_ADDR_HI 0x0C /* p246 */
62 #define START_ADDR_LO 0x0D /* p247 */
63 #define VERT_SYNC_END 0x11 /* p249 */
64 #define EXT_VERT_TOTAL 0x30 /* p257 */
65 #define EXT_VERT_DISPLAY 0x31 /* p258 */
66 #define EXT_VERT_SYNC_START 0x32 /* p259 */
67 #define EXT_VERT_BLANK_START 0x33 /* p260 */
68 #define EXT_HORIZ_TOTAL 0x35 /* p261 */
69 #define EXT_HORIZ_BLANK 0x39 /* p261 */
70 #define EXT_START_ADDR 0x40 /* p262 */
71 #define EXT_START_ADDR_ENABLE 0x80
72 #define EXT_OFFSET 0x41 /* p263 */
73 #define EXT_START_ADDR_HI 0x42 /* p263 */
74 #define INTERLACE_CNTL 0x70 /* p264 */
75 #define INTERLACE_ENABLE 0x80
76 #define INTERLACE_DISABLE 0x00
78 /* Miscellaneous Output Register
80 #define MSR_R 0x3CC /* p207 */
81 #define MSR_W 0x3C2 /* p207 */
82 #define IO_ADDR_SELECT 0x01
84 #define MDA_BASE 0x3B0 /* p207 */
85 #define CGA_BASE 0x3D0 /* p207 */
87 /* CR80 - IO Control, p264
90 #define EXTENDED_ATTR_CNTL 0x02
91 #define EXTENDED_CRTC_CNTL 0x01
93 /* GR10 - Address mapping, p221
95 #define ADDRESS_MAPPING 0x10
96 #define PAGE_TO_LOCAL_MEM_ENABLE 0x10
97 #define GTT_MEM_MAP_ENABLE 0x08
98 #define PACKED_MODE_ENABLE 0x04
99 #define LINEAR_MODE_ENABLE 0x02
100 #define PAGE_MAPPING_ENABLE 0x01
102 #define HOTKEY_VBIOS_SWITCH_BLOCK 0x80
103 #define HOTKEY_SWITCH 0x20
104 #define HOTKEY_TOGGLE 0x10
106 /* Blitter control, p378
108 #define BITBLT_CNTL 0x7000c
109 #define COLEXP_MODE 0x30
110 #define COLEXP_8BPP 0x00
111 #define COLEXP_16BPP 0x10
112 #define COLEXP_24BPP 0x20
113 #define COLEXP_RESERVED 0x30
114 #define BITBLT_STATUS 0x01
116 #define CHDECMISC 0x10111
118 #define C0DRB0 0x10200
119 #define C0DRB1 0x10202
120 #define C0DRB2 0x10204
121 #define C0DRB3 0x10206
122 #define C0DRA01 0x10208
123 #define C0DRA23 0x1020a
124 #define C1DRB0 0x10600
125 #define C1DRB1 0x10602
126 #define C1DRB2 0x10604
127 #define C1DRB3 0x10606
128 #define C1DRA01 0x10608
129 #define C1DRA23 0x1060a
133 #define DISPLAY_CNTL 0x70008
134 #define VGA_WRAP_MODE 0x02
135 #define VGA_WRAP_AT_256KB 0x00
136 #define VGA_NO_WRAP 0x02
137 #define GUI_MODE 0x01
138 #define STANDARD_VGA_MODE 0x00
139 #define HIRES_MODE 0x01
143 #define PIXPIPE_CONFIG_0 0x70009
144 #define DAC_8_BIT 0x80
145 #define DAC_6_BIT 0x00
146 #define HW_CURSOR_ENABLE 0x10
147 #define EXTENDED_PALETTE 0x01
151 #define PIXPIPE_CONFIG_1 0x7000a
152 #define DISPLAY_COLOR_MODE 0x0F
153 #define DISPLAY_VGA_MODE 0x00
154 #define DISPLAY_8BPP_MODE 0x02
155 #define DISPLAY_15BPP_MODE 0x04
156 #define DISPLAY_16BPP_MODE 0x05
157 #define DISPLAY_24BPP_MODE 0x06
158 #define DISPLAY_32BPP_MODE 0x07
162 #define PIXPIPE_CONFIG_2 0x7000b
163 #define DISPLAY_GAMMA_ENABLE 0x08
164 #define DISPLAY_GAMMA_DISABLE 0x00
165 #define OVERLAY_GAMMA_ENABLE 0x04
166 #define OVERLAY_GAMMA_DISABLE 0x00
171 #define DISPLAY_BASE 0x70020
172 #define DISPLAY_BASE_MASK 0x03fffffc
175 /* Cursor control registers, pp383-384
177 /* Desktop (845G, 865G) */
178 #define CURSOR_CONTROL 0x70080
179 #define CURSOR_ENABLE 0x80000000
180 #define CURSOR_GAMMA_ENABLE 0x40000000
181 #define CURSOR_STRIDE_MASK 0x30000000
182 #define CURSOR_FORMAT_SHIFT 24
183 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
184 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
185 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
186 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
187 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
188 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
190 /* Mobile and i810 */
191 #define CURSOR_A_CONTROL CURSOR_CONTROL
192 #define CURSOR_ORIGIN_SCREEN 0x00 /* i810 only */
193 #define CURSOR_ORIGIN_DISPLAY 0x1 /* i810 only */
194 #define CURSOR_MODE 0x27
195 #define CURSOR_MODE_DISABLE 0x00
196 #define CURSOR_MODE_32_4C_AX 0x01 /* i810 only */
197 #define CURSOR_MODE_64_3C 0x04
198 #define CURSOR_MODE_64_4C_AX 0x05
199 #define CURSOR_MODE_64_4C 0x06
200 #define CURSOR_MODE_64_32B_AX 0x07
201 #define CURSOR_MODE_64_ARGB_AX (0x20 | CURSOR_MODE_64_32B_AX)
202 #define MCURSOR_PIPE_SELECT (1 << 28)
203 #define MCURSOR_PIPE_A 0x00
204 #define MCURSOR_PIPE_B (1 << 28)
205 #define MCURSOR_GAMMA_ENABLE (1 << 26)
206 #define MCURSOR_MEM_TYPE_LOCAL (1 << 25)
209 #define CURSOR_BASEADDR 0x70084
210 #define CURSOR_A_BASE CURSOR_BASEADDR
211 #define CURSOR_BASEADDR_MASK 0x1FFFFF00
212 #define CURSOR_A_POSITION 0x70088
213 #define CURSOR_POS_SIGN 0x8000
214 #define CURSOR_POS_MASK 0x007FF
215 #define CURSOR_X_SHIFT 0
216 #define CURSOR_Y_SHIFT 16
217 #define CURSOR_X_LO 0x70088
218 #define CURSOR_X_HI 0x70089
219 #define CURSOR_X_POS 0x00
220 #define CURSOR_X_NEG 0x80
221 #define CURSOR_Y_LO 0x7008A
222 #define CURSOR_Y_HI 0x7008B
223 #define CURSOR_Y_POS 0x00
224 #define CURSOR_Y_NEG 0x80
226 #define CURSOR_A_PALETTE0 0x70090
227 #define CURSOR_A_PALETTE1 0x70094
228 #define CURSOR_A_PALETTE2 0x70098
229 #define CURSOR_A_PALETTE3 0x7009C
231 #define CURSOR_SIZE 0x700A0
232 #define CURSOR_SIZE_MASK 0x3FF
233 #define CURSOR_SIZE_HSHIFT 0
234 #define CURSOR_SIZE_VSHIFT 12
236 #define CURSOR_B_CONTROL 0x700C0
237 #define CURSOR_B_BASE 0x700C4
238 #define CURSOR_B_POSITION 0x700C8
239 #define CURSOR_B_PALETTE0 0x700D0
240 #define CURSOR_B_PALETTE1 0x700D4
241 #define CURSOR_B_PALETTE2 0x700D8
242 #define CURSOR_B_PALETTE3 0x700DC
245 /* Similar registers exist in Device 0 on the i810 (pp55-65), but I'm
246 * not sure they refer to local (graphics) memory.
248 * These details are for the local memory control registers,
249 * (pp301-310). The test machines are not equiped with local memory,
250 * so nothing is tested. Only a single row seems to be supported.
252 #define DRAM_ROW_TYPE 0x3000
253 #define DRAM_ROW_0 0x01
254 #define DRAM_ROW_0_SDRAM 0x01
255 #define DRAM_ROW_0_EMPTY 0x00
256 #define DRAM_ROW_CNTL_LO 0x3001
257 #define DRAM_PAGE_MODE_CTRL 0x10
258 #define DRAM_RAS_TO_CAS_OVRIDE 0x08
259 #define DRAM_CAS_LATENCY 0x04
260 #define DRAM_RAS_TIMING 0x02
261 #define DRAM_RAS_PRECHARGE 0x01
262 #define DRAM_ROW_CNTL_HI 0x3002
263 #define DRAM_REFRESH_RATE 0x18
264 #define DRAM_REFRESH_DISABLE 0x00
265 #define DRAM_REFRESH_60HZ 0x08
266 #define DRAM_REFRESH_FAST_TEST 0x10
267 #define DRAM_REFRESH_RESERVED 0x18
268 #define DRAM_SMS 0x07
269 #define DRAM_SMS_NORMAL 0x00
270 #define DRAM_SMS_NOP_ENABLE 0x01
271 #define DRAM_SMS_ABPCE 0x02
272 #define DRAM_SMS_MRCE 0x03
273 #define DRAM_SMS_CBRCE 0x04
277 #define DPMS_SYNC_SELECT 0x5002
278 #define VSYNC_CNTL 0x08
279 #define VSYNC_ON 0x00
280 #define VSYNC_OFF 0x08
281 #define HSYNC_CNTL 0x02
282 #define HSYNC_ON 0x00
283 #define HSYNC_OFF 0x02
293 # define GPIO_CLOCK_DIR_MASK (1 << 0)
294 # define GPIO_CLOCK_DIR_IN (0 << 1)
295 # define GPIO_CLOCK_DIR_OUT (1 << 1)
296 # define GPIO_CLOCK_VAL_MASK (1 << 2)
297 # define GPIO_CLOCK_VAL_OUT (1 << 3)
298 # define GPIO_CLOCK_VAL_IN (1 << 4)
299 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
300 # define GPIO_DATA_DIR_MASK (1 << 8)
301 # define GPIO_DATA_DIR_IN (0 << 9)
302 # define GPIO_DATA_DIR_OUT (1 << 9)
303 # define GPIO_DATA_VAL_MASK (1 << 10)
304 # define GPIO_DATA_VAL_OUT (1 << 11)
305 # define GPIO_DATA_VAL_IN (1 << 12)
306 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
308 /* GMBus registers for hardware-assisted (non-bitbanging) I2C access */
309 #define GMBUS0 0x5100
310 #define GMBUS1 0x5104
311 #define GMBUS2 0x5108
312 #define GMBUS3 0x510c
313 #define GMBUS4 0x5110
314 #define GMBUS5 0x5120
318 #define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */
319 #define VCLK2_VCO_N 0x600a
320 #define VCLK2_VCO_DIV_SEL 0x6012
322 #define VCLK_DIVISOR_VGA0 0x6000
323 #define VCLK_DIVISOR_VGA1 0x6004
324 #define VCLK_POST_DIV 0x6010
325 /** Selects a post divisor of 4 instead of 2. */
326 # define VGA1_PD_P2_DIV_4 (1 << 15)
327 /** Overrides the p2 post divisor field */
328 # define VGA1_PD_P1_DIV_2 (1 << 13)
329 # define VGA1_PD_P1_SHIFT 8
330 /** P1 value is 2 greater than this field */
331 # define VGA1_PD_P1_MASK (0x1f << 8)
332 /** Selects a post divisor of 4 instead of 2. */
333 # define VGA0_PD_P2_DIV_4 (1 << 7)
334 /** Overrides the p2 post divisor field */
335 # define VGA0_PD_P1_DIV_2 (1 << 5)
336 # define VGA0_PD_P1_SHIFT 0
337 /** P1 value is 2 greater than this field */
338 # define VGA0_PD_P1_MASK (0x1f << 0)
340 #define POST_DIV_SELECT 0x70
341 #define POST_DIV_1 0x00
342 #define POST_DIV_2 0x10
343 #define POST_DIV_4 0x20
344 #define POST_DIV_8 0x30
345 #define POST_DIV_16 0x40
346 #define POST_DIV_32 0x50
347 #define VCO_LOOP_DIV_BY_4M 0x00
348 #define VCO_LOOP_DIV_BY_16M 0x04
351 /* Instruction Parser Mode Register
355 #define INST_PM 0x20c0
356 #define AGP_SYNC_PACKET_FLUSH_ENABLE 0x20 /* reserved */
357 #define SYNC_PACKET_FLUSH_ENABLE 0x10
358 #define TWO_D_INST_DISABLE 0x08
359 #define THREE_D_INST_DISABLE 0x04
360 #define STATE_VAR_UPDATE_DISABLE 0x02
361 #define PAL_STIP_DISABLE 0x01
362 #define GEN6_GLOBAL_DEBUG_ENABLE 0x10
365 #define MEMMODE 0x20dc
368 /* Instruction parser error register. p279
373 #define INST_DONE 0x2090
374 # define IDCT_DONE (1 << 30)
375 # define IQ_DONE (1 << 29)
376 # define PR_DONE (1 << 28)
377 # define VLD_DONE (1 << 27)
378 # define IP_DONE (1 << 26)
379 # define FBC_DONE (1 << 25)
380 # define BINNER_DONE (1 << 24)
381 # define SF_DONE (1 << 23)
382 # define SE_DONE (1 << 22)
383 # define WM_DONE (1 << 21)
384 # define IZ_DONE (1 << 20)
385 # define PERSPECTIVE_INTERP_DONE (1 << 19)
386 # define DISPATCHER_DONE (1 << 18)
387 # define PROJECTION_DONE (1 << 17)
388 # define DEPENDENT_ADDRESS_DONE (1 << 16)
389 # define QUAD_CACHE_DONE (1 << 15)
390 # define TEXTURE_FETCH_DONE (1 << 14)
391 # define TEXTURE_DECOMPRESS_DONE (1 << 13)
392 # define SAMPLER_CACHE_DONE (1 << 12)
393 # define FILTER_DONE (1 << 11)
394 # define BYPASS_FIFO_DONE (1 << 10)
395 # define PS_DONE (1 << 9)
396 # define CC_DONE (1 << 8)
397 # define MAP_FILTER_DONE (1 << 7)
398 # define MAP_L2_IDLE (1 << 6)
399 # define RING_2_ENABLE (1 << 2)
400 # define RING_1_ENABLE (1 << 1)
401 # define RING_0_ENABLE (1 << 0)
403 # define I830_GMBUS_DONE (1 << 26)
404 # define I830_FBC_DONE (1 << 25)
405 # define I830_BINNER_DONE (1 << 24)
406 # define I830_MPEG_DONE (1 << 23)
407 # define I830_MECO_DONE (1 << 22)
408 # define I830_MCD_DONE (1 << 21)
409 # define I830_MCSTP_DONE (1 << 20)
410 # define I830_CC_DONE (1 << 19)
411 # define I830_DG_DONE (1 << 18)
412 # define I830_DCMP_DONE (1 << 17)
413 # define I830_FTCH_DONE (1 << 16)
414 # define I830_IT_DONE (1 << 15)
415 # define I830_MG_DONE (1 << 14)
416 # define I830_MEC_DONE (1 << 13)
417 # define I830_PC_DONE (1 << 12)
418 # define I830_QCC_DONE (1 << 11)
419 # define I830_TB_DONE (1 << 10)
420 # define I830_WM_DONE (1 << 9)
421 # define I830_EF_DONE (1 << 8)
422 # define I830_BLITTER_DONE (1 << 7)
423 # define I830_MAP_L2_DONE (1 << 6)
424 # define I830_SECONDARY_RING_3_DONE (1 << 5)
425 # define I830_SECONDARY_RING_2_DONE (1 << 4)
426 # define I830_SECONDARY_RING_1_DONE (1 << 3)
427 # define I830_SECONDARY_RING_0_DONE (1 << 2)
428 # define I830_PRIMARY_RING_1_DONE (1 << 1)
429 # define I830_PRIMARY_RING_0_DONE (1 << 0)
431 #define NOP_ID 0x2094
433 #define SCPD0 0x209c /* debug */
434 #define INST_PS 0x20c4
435 #define IPEIR_I965 0x2064 /* i965 */
436 #define IPEHR_I965 0x2068 /* i965 */
437 #define INST_DONE_I965 0x206c
438 # define I965_ROW_0_EU_0_DONE (1 << 31)
439 # define I965_ROW_0_EU_1_DONE (1 << 30)
440 # define I965_ROW_0_EU_2_DONE (1 << 29)
441 # define I965_ROW_0_EU_3_DONE (1 << 28)
442 # define I965_ROW_1_EU_0_DONE (1 << 27)
443 # define I965_ROW_1_EU_1_DONE (1 << 26)
444 # define I965_ROW_1_EU_2_DONE (1 << 25)
445 # define I965_ROW_1_EU_3_DONE (1 << 24)
446 # define I965_SF_DONE (1 << 23)
447 # define I965_SE_DONE (1 << 22)
448 # define I965_WM_DONE (1 << 21)
449 # define I965_DISPATCHER_DONE (1 << 18)
450 # define I965_PROJECTION_DONE (1 << 17)
451 # define I965_DG_DONE (1 << 16)
452 # define I965_QUAD_CACHE_DONE (1 << 15)
453 # define I965_TEXTURE_FETCH_DONE (1 << 14)
454 # define I965_TEXTURE_DECOMPRESS_DONE (1 << 13)
455 # define I965_SAMPLER_CACHE_DONE (1 << 12)
456 # define I965_FILTER_DONE (1 << 11)
457 # define I965_BYPASS_DONE (1 << 10)
458 # define I965_PS_DONE (1 << 9)
459 # define I965_CC_DONE (1 << 8)
460 # define I965_MAP_FILTER_DONE (1 << 7)
461 # define I965_MAP_L2_IDLE (1 << 6)
462 # define I965_MA_ROW_0_DONE (1 << 5)
463 # define I965_MA_ROW_1_DONE (1 << 4)
464 # define I965_IC_ROW_0_DONE (1 << 3)
465 # define I965_IC_ROW_1_DONE (1 << 2)
466 # define I965_CP_DONE (1 << 1)
467 # define I965_RING_0_ENABLE (1 << 0)
469 # define ILK_ROW_0_EU_0_DONE (1 << 31)
470 # define ILK_ROW_0_EU_1_DONE (1 << 30)
471 # define ILK_ROW_0_EU_2_DONE (1 << 29)
472 # define ILK_ROW_0_EU_3_DONE (1 << 28)
473 # define ILK_ROW_1_EU_0_DONE (1 << 27)
474 # define ILK_ROW_1_EU_1_DONE (1 << 26)
475 # define ILK_ROW_1_EU_2_DONE (1 << 25)
476 # define ILK_ROW_1_EU_3_DONE (1 << 24)
477 # define ILK_ROW_2_EU_0_DONE (1 << 23)
478 # define ILK_ROW_2_EU_1_DONE (1 << 22)
479 # define ILK_ROW_2_EU_2_DONE (1 << 21)
480 # define ILK_ROW_2_EU_3_DONE (1 << 20)
481 # define ILK_VCP_DONE (1 << 19)
482 # define ILK_ROW_0_MATH_DONE (1 << 18)
483 # define ILK_ROW_1_MATH_DONE (1 << 17)
484 # define ILK_ROW_2_MATH_DONE (1 << 16)
485 # define ILK_VC1_DONE (1 << 15)
486 # define ILK_ROW_0_MA_DONE (1 << 14)
487 # define ILK_ROW_1_MA_DONE (1 << 13)
488 # define ILK_ROW_2_MA_DONE (1 << 12)
489 # define ILK_ROW_0_ISC_DONE (1 << 11)
490 # define ILK_ROW_1_ISC_DONE (1 << 10)
491 # define ILK_ROW_2_ISC_DONE (1 << 9)
492 # define ILK_VFE_DONE (1 << 8)
493 # define ILK_TD_DONE (1 << 7)
494 # define ILK_SVTS_DONE (1 << 6)
495 # define ILK_TS_DONE (1 << 5)
496 # define ILK_GW_DONE (1 << 4)
497 # define ILK_AI_DONE (1 << 3)
498 # define ILK_AC_DONE (1 << 2)
499 # define ILK_AM_DONE (1 << 1)
501 #define GEN6_INSTDONE_1 0x206c
502 # define GEN6_MA_3_DONE (1 << 31)
503 # define GEN6_EU_32_DONE (1 << 30)
504 # define GEN6_EU_31_DONE (1 << 29)
505 # define GEN6_EU_30_DONE (1 << 28)
506 # define GEN6_MA_2_DONE (1 << 27)
507 # define GEN6_EU_22_DONE (1 << 26)
508 # define GEN6_EU_21_DONE (1 << 25)
509 # define GEN6_EU_20_DONE (1 << 24)
510 # define GEN6_MA_1_DONE (1 << 23)
511 # define GEN6_EU_12_DONE (1 << 22)
512 # define GEN6_EU_11_DONE (1 << 21)
513 # define GEN6_EU_10_DONE (1 << 20)
514 # define GEN6_MA_0_DONE (1 << 19)
515 # define GEN6_EU_02_DONE (1 << 18)
516 # define GEN6_EU_01_DONE (1 << 17)
517 # define GEN6_EU_00_DONE (1 << 16)
518 # define GEN6_IC_3_DONE (1 << 15)
519 # define GEN6_IC_2_DONE (1 << 14)
520 # define GEN6_IC_1_DONE (1 << 13)
521 # define GEN6_IC_0_DONE (1 << 12)
522 # define GEN6_ISC_10_DONE (1 << 11)
523 # define GEN6_ISC_32_DONE (1 << 10)
524 # define GEN6_VSC_DONE (1 << 9)
525 # define GEN6_IEF_DONE (1 << 8)
526 # define GEN6_VFE_DONE (1 << 7)
527 # define GEN6_TD_DONE (1 << 6)
528 # define GEN6_TS_DONE (1 << 4)
529 # define GEN6_GW_DONE (1 << 3)
530 # define GEN6_HIZ_DONE (1 << 2)
531 # define GEN6_AVS_DONE (1 << 1)
533 #define INST_PS_I965 0x2070
535 /* Current active ring head address:
537 #define ACTHD_I965 0x2074
540 /* Current primary/secondary DMA fetch addresses:
542 #define DMA_FADD_P 0x2078
543 #define DMA_FADD_S 0x20d4
544 #define INST_DONE_1 0x207c
545 # define I965_GW_CS_DONE_CR (1 << 19)
546 # define I965_SVSM_CS_DONE_CR (1 << 18)
547 # define I965_SVDW_CS_DONE_CR (1 << 17)
548 # define I965_SVDR_CS_DONE_CR (1 << 16)
549 # define I965_SVRW_CS_DONE_CR (1 << 15)
550 # define I965_SVRR_CS_DONE_CR (1 << 14)
551 # define I965_SVTW_CS_DONE_CR (1 << 13)
552 # define I965_MASM_CS_DONE_CR (1 << 12)
553 # define I965_MASF_CS_DONE_CR (1 << 11)
554 # define I965_MAW_CS_DONE_CR (1 << 10)
555 # define I965_EM1_CS_DONE_CR (1 << 9)
556 # define I965_EM0_CS_DONE_CR (1 << 8)
557 # define I965_UC1_CS_DONE (1 << 7)
558 # define I965_UC0_CS_DONE (1 << 6)
559 # define I965_URB_CS_DONE (1 << 5)
560 # define I965_ISC_CS_DONE (1 << 4)
561 # define I965_CL_CS_DONE (1 << 3)
562 # define I965_GS_CS_DONE (1 << 2)
563 # define I965_VS0_CS_DONE (1 << 1)
564 # define I965_VF_CS_DONE (1 << 0)
566 # define G4X_BCS_DONE (1 << 31)
567 # define G4X_CS_DONE (1 << 30)
568 # define G4X_MASF_DONE (1 << 29)
569 # define G4X_SVDW_DONE (1 << 28)
570 # define G4X_SVDR_DONE (1 << 27)
571 # define G4X_SVRW_DONE (1 << 26)
572 # define G4X_SVRR_DONE (1 << 25)
573 # define G4X_ISC_DONE (1 << 24)
574 # define G4X_MT_DONE (1 << 23)
575 # define G4X_RC_DONE (1 << 22)
576 # define G4X_DAP_DONE (1 << 21)
577 # define G4X_MAWB_DONE (1 << 20)
578 # define G4X_MT_IDLE (1 << 19)
579 # define G4X_GBLT_BUSY (1 << 18)
580 # define G4X_SVSM_DONE (1 << 17)
581 # define G4X_MASM_DONE (1 << 16)
582 # define G4X_QC_DONE (1 << 15)
583 # define G4X_FL_DONE (1 << 14)
584 # define G4X_SC_DONE (1 << 13)
585 # define G4X_DM_DONE (1 << 12)
586 # define G4X_FT_DONE (1 << 11)
587 # define G4X_DG_DONE (1 << 10)
588 # define G4X_SI_DONE (1 << 9)
589 # define G4X_SO_DONE (1 << 8)
590 # define G4X_PL_DONE (1 << 7)
591 # define G4X_WIZ_DONE (1 << 6)
592 # define G4X_URB_DONE (1 << 5)
593 # define G4X_SF_DONE (1 << 4)
594 # define G4X_CL_DONE (1 << 3)
595 # define G4X_GS_DONE (1 << 2)
596 # define G4X_VS0_DONE (1 << 1)
597 # define G4X_VF_DONE (1 << 0)
599 #define GEN6_INSTDONE_2 0x207c
600 # define GEN6_GAM_DONE (1 << 31)
601 # define GEN6_CS_DONE (1 << 30)
602 # define GEN6_WMBE_DONE (1 << 29)
603 # define GEN6_SVRW_DONE (1 << 28)
604 # define GEN6_RCC_DONE (1 << 27)
605 # define GEN6_SVG_DONE (1 << 26)
606 # define GEN6_ISC_DONE (1 << 25)
607 # define GEN6_MT_DONE (1 << 24)
608 # define GEN6_RCPFE_DONE (1 << 23)
609 # define GEN6_RCPBE_DONE (1 << 22)
610 # define GEN6_VDI_DONE (1 << 21)
611 # define GEN6_RCZ_DONE (1 << 20)
612 # define GEN6_DAP_DONE (1 << 19)
613 # define GEN6_PSD_DONE (1 << 18)
614 # define GEN6_IZ_DONE (1 << 17)
615 # define GEN6_WMFE_DONE (1 << 16)
616 # define GEN6_SVSM_DONE (1 << 15)
617 # define GEN6_QC_DONE (1 << 14)
618 # define GEN6_FL_DONE (1 << 13)
619 # define GEN6_SC_DONE (1 << 12)
620 # define GEN6_DM_DONE (1 << 11)
621 # define GEN6_FT_DONE (1 << 10)
622 # define GEN6_DG_DONE (1 << 9)
623 # define GEN6_SI_DONE (1 << 8)
624 # define GEN6_SO_DONE (1 << 7)
625 # define GEN6_PL_DONE (1 << 6)
626 # define GEN6_VME_DONE (1 << 5)
627 # define GEN6_SF_DONE (1 << 4)
628 # define GEN6_CL_DONE (1 << 3)
629 # define GEN6_GS_DONE (1 << 2)
630 # define GEN6_VS0_DONE (1 << 1)
631 # define GEN6_VF_DONE (1 << 0)
633 #define CACHE_MODE_0 0x2120
634 #define CACHE_MODE_1 0x2124
635 #define MI_MODE 0x209c
636 #define MI_DISPLAY_POWER_DOWN 0x20e0
637 #define MI_ARB_STATE 0x20e4
638 #define MI_RDRET_STATE 0x20fc
640 /* Start addresses for each of the primary rings:
642 #define PR0_STR 0x20f0
643 #define PR1_STR 0x20f4
644 #define PR2_STR 0x20f8
646 #define WIZ_CTL 0x7c00
647 #define WIZ_CTL_SINGLE_SUBSPAN (1<<6)
648 #define WIZ_CTL_IGNORE_STALLS (1<<5)
650 #define SVG_WORK_CTL 0x7408
652 #define TS_CTL 0x7e00
653 #define TS_MUX_ERR_CODE (0<<8)
654 #define TS_MUX_URB_0 (1<<8)
655 #define TS_MUX_DISPATCH_ID_0 (10<<8)
656 #define TS_MUX_ERR_CODE_VALID (15<<8)
657 #define TS_MUX_TID_0 (16<<8)
658 #define TS_MUX_EUID_0 (18<<8)
659 #define TS_MUX_FFID_0 (22<<8)
660 #define TS_MUX_EOT (26<<8)
661 #define TS_MUX_SIDEBAND_0 (27<<8)
662 #define TS_SNAP_ALL_CHILD (1<<2)
663 #define TS_SNAP_ALL_ROOT (1<<1)
664 #define TS_SNAP_ENABLE (1<<0)
666 #define TS_DEBUG_DATA 0x7e0c
668 #define TD_CTL 0x8000
669 #define TD_CTL2 0x8004
672 #define ECOSKPD 0x21d0
677 #define IA_VERTICES_COUNT_QW 0x2310
678 #define IA_PRIMITIVES_COUNT_QW 0x2318
679 #define VS_INVOCATION_COUNT_QW 0x2320
680 #define GS_INVOCATION_COUNT_QW 0x2328
681 #define GS_PRIMITIVES_COUNT_QW 0x2330
682 #define CL_INVOCATION_COUNT_QW 0x2338
683 #define CL_PRIMITIVES_COUNT_QW 0x2340
684 #define PS_INVOCATION_COUNT_QW 0x2348
685 #define PS_DEPTH_COUNT_QW 0x2350
686 #define TIMESTAMP_QW 0x2358
687 #define CLKCMP_QW 0x2360
694 /* General error reporting regs, p296
699 # define ERR_VERTEX_MAX (1 << 5) /* lpt/cst */
700 # define ERR_PGTBL_ERROR (1 << 4)
701 # define ERR_DISPLAY_OVERLAY_UNDERRUN (1 << 3)
702 # define ERR_MAIN_MEMORY_REFRESH (1 << 1)
703 # define ERR_INSTRUCTION_ERROR (1 << 0)
706 /* Interrupt Control Registers
707 * - new bits for i810
708 * - new register hwstam (mask)
710 #define HWS_PGA 0x2080
711 #define PWRCTXA 0x2088 /* 965GM+ only */
712 #define PWRCTX_EN (1<<0)
713 #define HWSTAM 0x2098 /* p290 */
714 #define IER 0x20a0 /* p291 */
715 #define IIR 0x20a4 /* p292 */
716 #define IMR 0x20a8 /* p293 */
717 #define ISR 0x20ac /* p294 */
718 #define HW_ERROR 0x8000
719 #define SYNC_STATUS_TOGGLE 0x1000
720 #define DPY_0_FLIP_PENDING 0x0800
721 #define DPY_1_FLIP_PENDING 0x0400 /* not implemented on i810 */
722 #define OVL_0_FLIP_PENDING 0x0200
723 #define OVL_1_FLIP_PENDING 0x0100 /* not implemented on i810 */
724 #define DPY_0_VBLANK 0x0080
725 #define DPY_0_EVENT 0x0040
726 #define DPY_1_VBLANK 0x0020 /* not implemented on i810 */
727 #define DPY_1_EVENT 0x0010 /* not implemented on i810 */
728 #define HOST_PORT_EVENT 0x0008 /* */
729 #define CAPTURE_EVENT 0x0004 /* */
730 #define USER_DEFINED 0x0002
731 #define BREAKPOINT 0x0001
734 #define INTR_RESERVED (0x6000 | \
735 DPY_1_FLIP_PENDING | \
736 OVL_1_FLIP_PENDING | \
742 /* FIFO Watermark and Burst Length Control Register
744 * - different offset and contents on i810 (p299) (fewer bits per field)
745 * - some overlay fields added
746 * - what does it all mean?
748 #define FWATER_BLC 0x20d8
749 #define FWATER_BLC2 0x20dc
750 #define MM_BURST_LENGTH 0x00700000
751 #define MM_FIFO_WATERMARK 0x0001F000
752 #define LM_BURST_LENGTH 0x00000700
753 #define LM_FIFO_WATERMARK 0x0000001F
756 /* Fence/Tiling ranges [0..7]
761 #define FENCE_NEW 0x3000
762 #define FENCE_NEW_NR 16
764 #define FENCE_LINEAR 0
765 #define FENCE_XMAJOR 1
766 #define FENCE_YMAJOR 2
768 #define I915G_FENCE_START_MASK 0x0ff00000
770 #define I830_FENCE_START_MASK 0x07f80000
772 #define FENCE_START_MASK 0x03F80000
773 #define FENCE_X_MAJOR 0x00000000
774 #define FENCE_Y_MAJOR 0x00001000
775 #define FENCE_SIZE_MASK 0x00000700
776 #define FENCE_SIZE_512K 0x00000000
777 #define FENCE_SIZE_1M 0x00000100
778 #define FENCE_SIZE_2M 0x00000200
779 #define FENCE_SIZE_4M 0x00000300
780 #define FENCE_SIZE_8M 0x00000400
781 #define FENCE_SIZE_16M 0x00000500
782 #define FENCE_SIZE_32M 0x00000600
783 #define FENCE_SIZE_64M 0x00000700
784 #define I915G_FENCE_SIZE_1M 0x00000000
785 #define I915G_FENCE_SIZE_2M 0x00000100
786 #define I915G_FENCE_SIZE_4M 0x00000200
787 #define I915G_FENCE_SIZE_8M 0x00000300
788 #define I915G_FENCE_SIZE_16M 0x00000400
789 #define I915G_FENCE_SIZE_32M 0x00000500
790 #define I915G_FENCE_SIZE_64M 0x00000600
791 #define I915G_FENCE_SIZE_128M 0x00000700
792 #define I965_FENCE_X_MAJOR 0x00000000
793 #define I965_FENCE_Y_MAJOR 0x00000002
794 #define FENCE_PITCH_1 0x00000000
795 #define FENCE_PITCH_2 0x00000010
796 #define FENCE_PITCH_4 0x00000020
797 #define FENCE_PITCH_8 0x00000030
798 #define FENCE_PITCH_16 0x00000040
799 #define FENCE_PITCH_32 0x00000050
800 #define FENCE_PITCH_64 0x00000060
801 #define FENCE_VALID 0x00000001
804 /* Registers to control page table, p274
806 #define PGETBL_CTL 0x2020
807 #define PGETBL_ADDR_MASK 0xFFFFF000
808 #define PGETBL_ENABLE_MASK 0x00000001
809 #define PGETBL_ENABLED 0x00000001
810 /** Added in 965G, this field has the actual size of the global GTT */
811 #define PGETBL_SIZE_MASK 0x0000000e
812 #define PGETBL_SIZE_512KB (0 << 1)
813 #define PGETBL_SIZE_256KB (1 << 1)
814 #define PGETBL_SIZE_128KB (2 << 1)
815 #define PGETBL_SIZE_1MB (3 << 1)
816 #define PGETBL_SIZE_2MB (4 << 1)
817 #define PGETBL_SIZE_1_5MB (5 << 1)
818 #define G33_PGETBL_SIZE_MASK (3 << 8)
819 #define G33_PGETBL_SIZE_1M (1 << 8)
820 #define G33_PGETBL_SIZE_2M (2 << 8)
822 #define I830_PTE_BASE 0x10000
823 #define PTE_ADDRESS_MASK 0xfffff000
824 #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
825 #define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
826 #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
827 #define PTE_MAPPING_TYPE_CACHED (3 << 1)
828 #define PTE_MAPPING_TYPE_MASK (3 << 1)
829 #define PTE_VALID (1 << 0)
831 /** @defgroup PGE_ERR
834 /** Page table debug register for i845 */
835 #define PGE_ERR 0x2024
836 #define PGE_ERR_ADDR_MASK 0xFFFFF000
837 #define PGE_ERR_ID_MASK 0x00000038
838 #define PGE_ERR_CAPTURE 0x00000000
839 #define PGE_ERR_OVERLAY 0x00000008
840 #define PGE_ERR_DISPLAY 0x00000010
841 #define PGE_ERR_HOST 0x00000018
842 #define PGE_ERR_RENDER 0x00000020
843 #define PGE_ERR_BLITTER 0x00000028
844 #define PGE_ERR_MAPPING 0x00000030
845 #define PGE_ERR_CMD_PARSER 0x00000038
846 #define PGE_ERR_TYPE_MASK 0x00000007
847 #define PGE_ERR_INV_TABLE 0x00000000
848 #define PGE_ERR_INV_PTE 0x00000001
849 #define PGE_ERR_MIXED_TYPES 0x00000002
850 #define PGE_ERR_PAGE_MISS 0x00000003
851 #define PGE_ERR_ILLEGAL_TRX 0x00000004
852 #define PGE_ERR_LOCAL_MEM 0x00000005
853 #define PGE_ERR_TILED 0x00000006
856 /** @defgroup PGTBL_ER
859 /** Page table debug register for i945 */
860 # define PGTBL_ER 0x2024
861 # define PGTBL_ERR_MT_TILING (1 << 27)
862 # define PGTBL_ERR_MT_GTT_PTE (1 << 26)
863 # define PGTBL_ERR_LC_TILING (1 << 25)
864 # define PGTBL_ERR_LC_GTT_PTE (1 << 24)
865 # define PGTBL_ERR_BIN_VERTEXDATA_GTT_PTE (1 << 23)
866 # define PGTBL_ERR_BIN_INSTRUCTION_GTT_PTE (1 << 22)
867 # define PGTBL_ERR_CS_VERTEXDATA_GTT_PTE (1 << 21)
868 # define PGTBL_ERR_CS_INSTRUCTION_GTT_PTE (1 << 20)
869 # define PGTBL_ERR_CS_GTT (1 << 19)
870 # define PGTBL_ERR_OVERLAY_TILING (1 << 18)
871 # define PGTBL_ERR_OVERLAY_GTT_PTE (1 << 16)
872 # define PGTBL_ERR_DISPC_TILING (1 << 14)
873 # define PGTBL_ERR_DISPC_GTT_PTE (1 << 12)
874 # define PGTBL_ERR_DISPB_TILING (1 << 10)
875 # define PGTBL_ERR_DISPB_GTT_PTE (1 << 8)
876 # define PGTBL_ERR_DISPA_TILING (1 << 6)
877 # define PGTBL_ERR_DISPA_GTT_PTE (1 << 4)
878 # define PGTBL_ERR_HOST_PTE_DATA (1 << 1)
879 # define PGTBL_ERR_HOST_GTT_PTE (1 << 0)
882 /* Ring buffer registers, p277, overview p19
884 #define LP_RING 0x2030
885 #define HP_RING 0x2040
887 #define RING_TAIL 0x00
888 #define TAIL_ADDR 0x000FFFF8
889 #define I830_TAIL_MASK 0x001FFFF8
891 #define RING_HEAD 0x04
892 #define HEAD_WRAP_COUNT 0xFFE00000
893 #define HEAD_WRAP_ONE 0x00200000
894 #define HEAD_ADDR 0x001FFFFC
895 #define I830_HEAD_MASK 0x001FFFFC
897 #define RING_START 0x08
898 #define START_ADDR 0x03FFFFF8
899 #define I830_RING_START_MASK 0xFFFFF000
901 #define RING_LEN 0x0C
902 #define RING_NR_PAGES 0x001FF000
903 #define I830_RING_NR_PAGES 0x001FF000
904 #define RING_REPORT_MASK 0x00000006
905 #define RING_REPORT_64K 0x00000002
906 #define RING_REPORT_128K 0x00000004
907 #define RING_NO_REPORT 0x00000000
908 #define RING_VALID_MASK 0x00000001
909 #define RING_VALID 0x00000001
910 #define RING_INVALID 0x00000000
914 /* BitBlt Instructions
916 * There are many more masks & ranges yet to add.
918 #define BR00_BITBLT_CLIENT 0x40000000
919 #define BR00_OP_COLOR_BLT 0x10000000
920 #define BR00_OP_SRC_COPY_BLT 0x10C00000
921 #define BR00_OP_FULL_BLT 0x11400000
922 #define BR00_OP_MONO_SRC_BLT 0x11800000
923 #define BR00_OP_MONO_SRC_COPY_BLT 0x11000000
924 #define BR00_OP_MONO_PAT_BLT 0x11C00000
925 #define BR00_OP_MONO_SRC_COPY_IMMEDIATE_BLT (0x61 << 22)
926 #define BR00_OP_TEXT_IMMEDIATE_BLT 0xc000000
929 #define BR00_TPCY_DISABLE 0x00000000
930 #define BR00_TPCY_ENABLE 0x00000010
932 #define BR00_TPCY_ROP 0x00000000
933 #define BR00_TPCY_NO_ROP 0x00000020
934 #define BR00_TPCY_EQ 0x00000000
935 #define BR00_TPCY_NOT_EQ 0x00000040
937 #define BR00_PAT_MSB_FIRST 0x00000000 /* ? */
939 #define BR00_PAT_VERT_ALIGN 0x000000e0
941 #define BR00_LENGTH 0x0000000F
943 #define BR09_DEST_ADDR 0x03FFFFFF
945 #define BR11_SOURCE_PITCH 0x00003FFF
947 #define BR12_SOURCE_ADDR 0x03FFFFFF
949 #define BR13_SOLID_PATTERN 0x80000000
950 #define BR13_RIGHT_TO_LEFT 0x40000000
951 #define BR13_LEFT_TO_RIGHT 0x00000000
952 #define BR13_MONO_TRANSPCY 0x20000000
953 #define BR13_MONO_PATN_TRANS 0x10000000
954 #define BR13_USE_DYN_DEPTH 0x04000000
955 #define BR13_DYN_8BPP 0x00000000
956 #define BR13_DYN_16BPP 0x01000000
957 #define BR13_DYN_24BPP 0x02000000
958 #define BR13_ROP_MASK 0x00FF0000
959 #define BR13_DEST_PITCH 0x0000FFFF
960 #define BR13_PITCH_SIGN_BIT 0x00008000
962 #define BR14_DEST_HEIGHT 0xFFFF0000
963 #define BR14_DEST_WIDTH 0x0000FFFF
965 #define BR15_PATTERN_ADDR 0x03FFFFFF
967 #define BR16_SOLID_PAT_COLOR 0x00FFFFFF
968 #define BR16_BACKGND_PAT_CLR 0x00FFFFFF
970 #define BR17_FGND_PAT_CLR 0x00FFFFFF
972 #define BR18_SRC_BGND_CLR 0x00FFFFFF
973 #define BR19_SRC_FGND_CLR 0x00FFFFFF
976 /* Instruction parser instructions
979 #define INST_PARSER_CLIENT 0x00000000
980 #define INST_OP_FLUSH 0x02000000
981 #define INST_FLUSH_MAP_CACHE 0x00000001
984 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
987 /* Registers in the i810 host-pci bridge pci config space which affect
988 * the i810 graphics operations.
990 #define SMRAM_MISCC 0x70
991 #define GMS 0x000000c0
992 #define GMS_DISABLE 0x00000000
993 #define GMS_ENABLE_BARE 0x00000040
994 #define GMS_ENABLE_512K 0x00000080
995 #define GMS_ENABLE_1M 0x000000c0
996 #define USMM 0x00000030
997 #define USMM_DISABLE 0x00000000
998 #define USMM_TSEG_ZERO 0x00000010
999 #define USMM_TSEG_512K 0x00000020
1000 #define USMM_TSEG_1M 0x00000030
1001 #define GFX_MEM_WIN_SIZE 0x00010000
1002 #define GFX_MEM_WIN_32M 0x00010000
1003 #define GFX_MEM_WIN_64M 0x00000000
1005 /* Overkill? I don't know. Need to figure out top of mem to make the
1006 * SMRAM calculations come out. Linux seems to have problems
1007 * detecting it all on its own, so this seems a reasonable double
1008 * check to any user supplied 'mem=...' boot param.
1010 * ... unfortunately this reg doesn't work according to spec on the
1013 #define WHTCFG_PAMR_DRP 0x50
1014 #define SYS_DRAM_ROW_0_SHIFT 16
1015 #define SYS_DRAM_ROW_1_SHIFT 20
1016 #define DRAM_MASK 0x0f
1017 #define DRAM_VALUE_0 0
1018 #define DRAM_VALUE_1 8
1019 /* No 2 value defined */
1020 #define DRAM_VALUE_3 16
1021 #define DRAM_VALUE_4 16
1022 #define DRAM_VALUE_5 24
1023 #define DRAM_VALUE_6 32
1024 #define DRAM_VALUE_7 32
1025 #define DRAM_VALUE_8 48
1026 #define DRAM_VALUE_9 64
1027 #define DRAM_VALUE_A 64
1028 #define DRAM_VALUE_B 96
1029 #define DRAM_VALUE_C 128
1030 #define DRAM_VALUE_D 128
1031 #define DRAM_VALUE_E 192
1032 #define DRAM_VALUE_F 256 /* nice one, geezer */
1033 #define LM_FREQ_MASK 0x10
1034 #define LM_FREQ_133 0x10
1035 #define LM_FREQ_100 0x00
1040 /* These are 3d state registers, but the state is invarient, so we let
1041 * the X server handle it:
1046 /* GFXRENDERSTATE_COLOR_CHROMA_KEY, p135
1048 #define GFX_OP_COLOR_CHROMA_KEY ((0x3<<29)|(0x1d<<24)|(0x2<<16)|0x1)
1049 #define CC1_UPDATE_KILL_WRITE (1<<28)
1050 #define CC1_ENABLE_KILL_WRITE (1<<27)
1051 #define CC1_DISABLE_KILL_WRITE 0
1052 #define CC1_UPDATE_COLOR_IDX (1<<26)
1053 #define CC1_UPDATE_CHROMA_LOW (1<<25)
1054 #define CC1_UPDATE_CHROMA_HI (1<<24)
1055 #define CC1_CHROMA_LOW_MASK ((1<<24)-1)
1056 #define CC2_COLOR_IDX_SHIFT 24
1057 #define CC2_COLOR_IDX_MASK (0xff<<24)
1058 #define CC2_CHROMA_HI_MASK ((1<<24)-1)
1061 #define GFX_CMD_CONTEXT_SEL ((0<<29)|(0x5<<23))
1062 #define CS_UPDATE_LOAD (1<<17)
1063 #define CS_UPDATE_USE (1<<16)
1064 #define CS_UPDATE_LOAD (1<<17)
1065 #define CS_LOAD_CTX0 0
1066 #define CS_LOAD_CTX1 (1<<8)
1067 #define CS_USE_CTX0 0
1068 #define CS_USE_CTX1 (1<<0)
1070 /* I810 LCD/TV registers */
1071 #define LCD_TV_HTOTAL 0x60000
1072 #define LCD_TV_C 0x60018
1073 #define LCD_TV_OVRACT 0x6001C
1075 #define LCD_TV_ENABLE (1 << 31)
1076 #define LCD_TV_VGAMOD (1 << 28)
1078 /* I830 CRTC registers */
1079 #define HTOTAL_A 0x60000
1080 #define HBLANK_A 0x60004
1081 #define HSYNC_A 0x60008
1082 #define VTOTAL_A 0x6000c
1083 #define VBLANK_A 0x60010
1084 #define VSYNC_A 0x60014
1085 #define PIPEASRC 0x6001c
1086 #define BCLRPAT_A 0x60020
1087 #define VSYNCSHIFT_A 0x60028
1089 #define HTOTAL_B 0x61000
1090 #define HBLANK_B 0x61004
1091 #define HSYNC_B 0x61008
1092 #define VTOTAL_B 0x6100c
1093 #define VBLANK_B 0x61010
1094 #define VSYNC_B 0x61014
1095 #define PIPEBSRC 0x6101c
1096 #define BCLRPAT_B 0x61020
1097 #define VSYNCSHIFT_B 0x61028
1099 #define HTOTAL_C 0x62000
1100 #define HBLANK_C 0x62004
1101 #define HSYNC_C 0x62008
1102 #define VTOTAL_C 0x6200c
1103 #define VBLANK_C 0x62010
1104 #define VSYNC_C 0x62014
1105 #define PIPECSRC 0x6201c
1106 #define BCLRPAT_C 0x62020
1107 #define VSYNCSHIFT_C 0x62028
1109 #define PP_STATUS 0x61200
1110 # define PP_ON (1 << 31)
1112 * Indicates that all dependencies of the panel are on:
1116 * - LVDS/DVOB/DVOC on
1118 # define PP_READY (1 << 30)
1119 # define PP_SEQUENCE_NONE (0 << 28)
1120 # define PP_SEQUENCE_ON (1 << 28)
1121 # define PP_SEQUENCE_OFF (2 << 28)
1122 # define PP_SEQUENCE_MASK 0x30000000
1124 #define PP_CONTROL 0x61204
1125 # define POWER_DOWN_ON_RESET (1 << 1)
1126 # define POWER_TARGET_ON (1 << 0)
1128 #define PP_ON_DELAYS 0x61208
1129 #define PP_OFF_DELAYS 0x6120c
1130 #define PP_DIVISOR 0x61210
1132 #define PFIT_CONTROL 0x61230
1133 # define PFIT_ENABLE (1 << 31)
1135 # define VERT_INTERP_DISABLE (0 << 10)
1136 # define VERT_INTERP_BILINEAR (1 << 10)
1137 # define VERT_INTERP_MASK (3 << 10)
1138 # define VERT_AUTO_SCALE (1 << 9)
1139 # define HORIZ_INTERP_DISABLE (0 << 6)
1140 # define HORIZ_INTERP_BILINEAR (1 << 6)
1141 # define HORIZ_INTERP_MASK (3 << 6)
1142 # define HORIZ_AUTO_SCALE (1 << 5)
1143 # define PANEL_8TO6_DITHER_ENABLE (1 << 3)
1145 # define PFIT_PIPE_MASK (3 << 29)
1146 # define PFIT_PIPE_SHIFT 29
1147 # define PFIT_SCALING_MODE_MASK (7 << 26)
1148 # define PFIT_SCALING_AUTO (0 << 26)
1149 # define PFIT_SCALING_PROGRAMMED (1 << 26)
1150 # define PFIT_SCALING_PILLAR (2 << 26)
1151 # define PFIT_SCALING_LETTER (3 << 26)
1152 # define PFIT_FILTER_SELECT_MASK (3 << 24)
1153 # define PFIT_FILTER_FUZZY (0 << 24)
1154 # define PFIT_FILTER_CRISP (1 << 24)
1155 # define PFIT_FILTER_MEDIAN (2 << 24)
1157 #define PFIT_PGM_RATIOS 0x61234
1159 # define PFIT_VERT_SCALE_SHIFT 20
1160 # define PFIT_VERT_SCALE_MASK 0xfff00000
1161 # define PFIT_HORIZ_SCALE_SHIFT 4
1162 # define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1164 # define PFIT_VERT_SCALE_SHIFT_965 16
1165 # define PFIT_VERT_SCALE_MASK_965 0x1fff0000
1166 # define PFIT_HORIZ_SCALE_SHIFT_965 0
1167 # define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
1169 #define DPLL_A 0x06014
1170 #define DPLL_B 0x06018
1171 # define DPLL_VCO_ENABLE (1 << 31)
1172 # define DPLL_DVO_HIGH_SPEED (1 << 30)
1173 # define DPLL_SYNCLOCK_ENABLE (1 << 29)
1174 # define DPLL_VGA_MODE_DIS (1 << 28)
1175 # define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
1176 # define DPLLB_MODE_LVDS (2 << 26) /* i915 */
1177 # define DPLL_MODE_MASK (3 << 26)
1178 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1179 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
1180 # define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
1181 # define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
1182 # define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
1183 # define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
1184 # define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */
1186 * The i830 generation, in DAC/serial mode, defines p1 as two plus this
1187 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
1189 # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
1191 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1192 * this field (only one bit may be set).
1194 # define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
1195 # define DPLL_FPA01_P1_POST_DIV_SHIFT 16
1196 # define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15
1197 # define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */
1198 # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
1199 # define PLL_REF_INPUT_DREFCLK (0 << 13)
1200 # define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
1201 # define PLL_REF_INPUT_SUPER_SSC (1 << 13) /* Ironlake: 120M SSC */
1202 # define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
1203 # define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1204 # define PLL_REF_INPUT_MASK (3 << 13)
1205 # define PLL_REF_INPUT_DMICLK (5 << 13) /* Ironlake: DMI refclk */
1206 # define PLL_LOAD_PULSE_PHASE_SHIFT 9
1208 * Parallel to Serial Load Pulse phase selection.
1209 * Selects the phase for the 10X DPLL clock for the PCIe
1210 * digital display port. The range is 4 to 13; 10 or more
1211 * is just a flip delay. The default is 6
1213 # define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1214 # define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1216 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
1217 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
1218 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1)<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT)
1219 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
1220 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
1223 * SDVO multiplier for 945G/GM. Not used on 965.
1225 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1227 # define SDVO_MULTIPLIER_MASK 0x000000ff
1228 # define SDVO_MULTIPLIER_SHIFT_HIRES 4
1229 # define SDVO_MULTIPLIER_SHIFT_VGA 0
1231 /** @defgroup DPLL_MD
1234 /** Pipe A SDVO/UDI clock multiplier/divider register for G965. */
1235 #define DPLL_A_MD 0x0601c
1236 /** Pipe B SDVO/UDI clock multiplier/divider register for G965. */
1237 #define DPLL_B_MD 0x06020
1239 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1241 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1243 # define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1244 # define DPLL_MD_UDI_DIVIDER_SHIFT 24
1245 /** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1246 # define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1247 # define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1249 * SDVO/UDI pixel multiplier.
1251 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1252 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1253 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1254 * dummy bytes in the datastream at an increased clock rate, with both sides of
1255 * the link knowing how many bytes are fill.
1257 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1258 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1259 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1260 * through an SDVO command.
1262 * This register field has values of multiplication factor minus 1, with
1263 * a maximum multiplier of 5 for SDVO.
1265 # define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1266 # define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1267 /** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1268 * This best be set to the default value (3) or the CRT won't work. No,
1269 * I don't entirely understand what this does...
1271 # define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1272 # define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
1275 #define DPLL_TEST 0x606c
1276 # define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1277 # define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1278 # define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1279 # define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1280 # define DPLLB_TEST_N_BYPASS (1 << 19)
1281 # define DPLLB_TEST_M_BYPASS (1 << 18)
1282 # define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1283 # define DPLLA_TEST_N_BYPASS (1 << 3)
1284 # define DPLLA_TEST_M_BYPASS (1 << 2)
1285 # define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1287 #define D_STATE 0x6104
1288 #define DSPCLK_GATE_D 0x6200
1289 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1290 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1291 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
1292 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
1293 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
1294 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
1295 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
1296 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
1297 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
1298 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
1299 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
1300 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
1301 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
1302 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
1303 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
1304 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
1305 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
1306 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
1307 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
1308 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1309 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
1310 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
1311 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
1312 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
1313 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
1314 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1315 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
1316 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
1318 * This bit must be set on the 830 to prevent hangs when turning off the
1321 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
1322 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
1323 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
1324 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
1325 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
1327 #define RENCLK_GATE_D1 0x6204
1328 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
1329 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
1330 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
1331 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
1332 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
1333 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
1334 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
1335 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
1336 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
1337 /** This bit must be unset on 855,865 */
1338 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
1339 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
1340 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
1341 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
1342 /** This bit must be set on 855,865. */
1343 # define SV_CLOCK_GATE_DISABLE (1 << 0)
1344 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
1345 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
1346 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
1347 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
1348 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
1349 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
1350 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
1351 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1352 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1353 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1354 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1355 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1356 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1357 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1358 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1359 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1360 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1362 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
1363 /** This bit must always be set on 965G/965GM */
1364 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1365 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1366 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1367 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1368 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1369 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
1370 /** This bit must always be set on 965G */
1371 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1372 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1373 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1374 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1375 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1376 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1377 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1378 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1379 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
1380 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
1381 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
1382 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
1383 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
1384 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
1385 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
1386 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
1387 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
1388 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
1389 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
1391 #define RENCLK_GATE_D2 0x6208
1392 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
1393 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
1394 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
1395 #define RAMCLK_GATE_D 0x6210 /* CRL only */
1396 #define DEUC 0x6214 /* CRL only */
1399 * This is a PCI config space register to manipulate backlight brightness
1400 * It is used when the BLM_LEGACY_MODE is turned on. When enabled, the first
1401 * byte of this config register sets brightness within the range from
1404 #define LEGACY_BACKLIGHT_BRIGHTNESS 0xf4
1406 #define BLC_PWM_CTL 0x61254
1407 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
1408 #define BACKLIGHT_MODULATION_FREQ_SHIFT2 (16)
1410 * This is the most significant 15 bits of the number of backlight cycles in a
1411 * complete cycle of the modulated backlight control.
1413 * The actual value is this field multiplied by two.
1415 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
1416 #define BACKLIGHT_MODULATION_FREQ_MASK2 (0xffff << 16)
1417 #define BLM_LEGACY_MODE (1 << 16)
1420 * This is the number of cycles out of the backlight modulation cycle for which
1421 * the backlight is on.
1423 * This field must be no greater than the number of cycles in the complete
1424 * backlight modulation cycle.
1426 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1427 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1429 /* On 965+ backlight control is in another register */
1430 #define BLC_PWM_CTL2 0x61250
1431 #define BLM_LEGACY_MODE2 (1 << 30)
1433 #define BLM_CTL 0x61260
1434 #define BLM_THRESHOLD_0 0x61270
1435 #define BLM_THRESHOLD_1 0x61274
1436 #define BLM_THRESHOLD_2 0x61278
1437 #define BLM_THRESHOLD_3 0x6127c
1438 #define BLM_THRESHOLD_4 0x61280
1439 #define BLM_THRESHOLD_5 0x61284
1441 #define BLM_ACCUMULATOR_0 0x61290
1442 #define BLM_ACCUMULATOR_1 0x61294
1443 #define BLM_ACCUMULATOR_2 0x61298
1444 #define BLM_ACCUMULATOR_3 0x6129c
1445 #define BLM_ACCUMULATOR_4 0x612a0
1446 #define BLM_ACCUMULATOR_5 0x612a4
1448 #define FPA0 0x06040
1449 #define FPA1 0x06044
1450 #define FPB0 0x06048
1451 #define FPB1 0x0604c
1452 # define FP_N_DIV_MASK 0x003f0000
1453 # define FP_N_IGD_DIV_MASK 0x00ff0000
1454 # define FP_N_DIV_SHIFT 16
1455 # define FP_M1_DIV_MASK 0x00003f00
1456 # define FP_M1_DIV_SHIFT 8
1457 # define FP_M2_DIV_MASK 0x0000003f
1458 # define FP_M2_IGD_DIV_MASK 0x000000ff
1459 # define FP_M2_DIV_SHIFT 0
1461 #define PORT_HOTPLUG_EN 0x61110
1462 # define HDMIB_HOTPLUG_INT_EN (1 << 29)
1463 # define HDMIC_HOTPLUG_INT_EN (1 << 28)
1464 # define HDMID_HOTPLUG_INT_EN (1 << 27)
1465 # define SDVOB_HOTPLUG_INT_EN (1 << 26)
1466 # define SDVOC_HOTPLUG_INT_EN (1 << 25)
1467 # define TV_HOTPLUG_INT_EN (1 << 18)
1468 # define CRT_HOTPLUG_INT_EN (1 << 9)
1469 # define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1470 /* must use period 64 on GM45 according to docs */
1471 # define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1472 # define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1473 # define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1474 # define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1475 # define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1476 # define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1477 # define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1478 # define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1479 # define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1480 # define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1481 # define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1482 # define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1483 # define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
1484 # define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */
1486 #define PORT_HOTPLUG_STAT 0x61114
1487 # define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
1488 # define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
1489 # define HDMID_HOTPLUG_INT_STATUS (1 << 27)
1490 # define CRT_HOTPLUG_INT_STATUS (1 << 11)
1491 # define TV_HOTPLUG_INT_STATUS (1 << 10)
1492 # define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1493 # define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1494 # define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1495 # define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1496 # define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
1497 # define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
1499 #define SDVOB 0x61140
1500 #define SDVOC 0x61160
1501 #define SDVO_ENABLE (1 << 31)
1502 #define SDVO_PIPE_B_SELECT (1 << 30)
1503 #define SDVO_STALL_SELECT (1 << 29)
1504 #define SDVO_INTERRUPT_ENABLE (1 << 26)
1506 * 915G/GM SDVO pixel multiplier.
1508 * Programmed value is multiplier - 1, up to 5x.
1510 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1512 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1513 #define SDVO_PORT_MULTIPLY_SHIFT 23
1514 #define SDVO_PHASE_SELECT_MASK (15 << 19)
1515 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1516 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1517 #define SDVOC_GANG_MODE (1 << 16)
1518 #define SDVO_ENCODING_SDVO (0x0 << 10)
1519 #define SDVO_ENCODING_HDMI (0x2 << 10)
1520 /** Requird for HDMI operation */
1521 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
1522 #define SDVO_BORDER_ENABLE (1 << 7)
1523 #define SDVO_AUDIO_ENABLE (1 << 6)
1524 /** New with 965, default is to be set */
1525 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1526 /** New with 965, default is to be set */
1527 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
1528 /** 915/945 only, read-only bit */
1529 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
1530 #define SDVO_DETECTED (1 << 2)
1531 /* Bits to be preserved when writing */
1532 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14))
1533 #define SDVOC_PRESERVE_MASK (1 << 17)
1535 #define UDIB_SVB_SHB_CODES 0x61144
1536 #define UDIB_SHA_BLANK_CODES 0x61148
1537 #define UDIB_START_END_FILL_CODES 0x6114c
1540 #define SDVOUDI 0x61150
1542 #define I830_HTOTAL_MASK 0xfff0000
1543 #define I830_HACTIVE_MASK 0x7ff
1545 #define I830_HBLANKEND_MASK 0xfff0000
1546 #define I830_HBLANKSTART_MASK 0xfff
1548 #define I830_HSYNCEND_MASK 0xfff0000
1549 #define I830_HSYNCSTART_MASK 0xfff
1551 #define I830_VTOTAL_MASK 0xfff0000
1552 #define I830_VACTIVE_MASK 0x7ff
1554 #define I830_VBLANKEND_MASK 0xfff0000
1555 #define I830_VBLANKSTART_MASK 0xfff
1557 #define I830_VSYNCEND_MASK 0xfff0000
1558 #define I830_VSYNCSTART_MASK 0xfff
1560 #define I830_PIPEA_HORZ_MASK 0x7ff0000
1561 #define I830_PIPEA_VERT_MASK 0x7ff
1563 #define ADPA 0x61100
1564 #define ADPA_DAC_ENABLE (1<<31)
1565 #define ADPA_DAC_DISABLE 0
1566 #define ADPA_PIPE_SELECT_MASK (1<<30)
1567 #define ADPA_PIPE_A_SELECT 0
1568 #define ADPA_PIPE_B_SELECT (1<<30)
1569 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
1570 #define ADPA_SETS_HVPOLARITY 0
1571 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1572 #define ADPA_VSYNC_CNTL_ENABLE 0
1573 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1574 #define ADPA_HSYNC_CNTL_ENABLE 0
1575 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1576 #define ADPA_VSYNC_ACTIVE_LOW 0
1577 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1578 #define ADPA_HSYNC_ACTIVE_LOW 0
1580 #define PCH_DSPCLK_GATE_D 0x42020
1581 #define PCH_DSPRAMCLK_GATE_D 0x42024
1582 #define PCH_3DCGDIS0 0x46020
1583 #define PCH_3DCGDIS1 0x46024
1584 #define PCH_3DRAMCGDIS0 0x46028
1585 #define SOUTH_DSPCLK_GATE_D 0xc2020
1587 #define CPU_eDP_A 0x64000
1588 #define PCH_DP_B 0xe4100
1589 #define PCH_DP_C 0xe4200
1590 #define PCH_DP_D 0xe4300
1592 #define DVOA 0x61120
1593 #define DVOB 0x61140
1594 #define DVOC 0x61160
1595 #define DVO_ENABLE (1 << 31)
1596 #define DVO_PIPE_B_SELECT (1 << 30)
1597 #define DVO_PIPE_STALL_UNUSED (0 << 28)
1598 #define DVO_PIPE_STALL (1 << 28)
1599 #define DVO_PIPE_STALL_TV (2 << 28)
1600 #define DVO_PIPE_STALL_MASK (3 << 28)
1601 #define DVO_USE_VGA_SYNC (1 << 15)
1602 #define DVO_DATA_ORDER_I740 (0 << 14)
1603 #define DVO_DATA_ORDER_FP (1 << 14)
1604 #define DVO_VSYNC_DISABLE (1 << 11)
1605 #define DVO_HSYNC_DISABLE (1 << 10)
1606 #define DVO_VSYNC_TRISTATE (1 << 9)
1607 #define DVO_HSYNC_TRISTATE (1 << 8)
1608 #define DVO_BORDER_ENABLE (1 << 7)
1609 #define DVO_DATA_ORDER_GBRG (1 << 6)
1610 #define DVO_DATA_ORDER_RGGB (0 << 6)
1611 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
1612 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
1613 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
1614 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
1615 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
1616 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
1617 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
1618 #define DVO_PRESERVE_MASK (0x7<<24)
1620 #define DVOA_SRCDIM 0x61124
1621 #define DVOB_SRCDIM 0x61144
1622 #define DVOC_SRCDIM 0x61164
1623 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
1624 #define DVO_SRCDIM_VERTICAL_SHIFT 0
1630 * This register controls the LVDS output enable, pipe selection, and data
1633 * All of the clock/data pairs are force powered down by power sequencing.
1635 #define LVDS 0x61180
1637 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1638 * the DPLL semantics change when the LVDS is assigned to that pipe.
1640 # define LVDS_PORT_EN (1 << 31)
1641 /** Selects pipe B for LVDS data. Must be set on pre-965. */
1642 # define LVDS_PIPEB_SELECT (1 << 30)
1644 /* on 965, dithering is enabled in this register, not PFIT_CONTROL */
1645 # define LVDS_DITHER_ENABLE (1 << 25)
1648 * Selects between .0 and .1 formats:
1650 * 0 = 1x18.0, 2x18.0, 1x24.0 or 2x24.0
1651 * 1 = 1x24.1 or 2x24.1
1653 # define LVDS_DATA_FORMAT_DOT_ONE (1 << 24)
1655 /* Using LE instead of HS on second channel control signal */
1656 # define LVDS_LE_CONTROL_ENABLE (1 << 23)
1658 /* Using LF instead of VS on second channel control signal */
1659 # define LVDS_LF_CONTROL_ENABLE (1 << 22)
1661 /* invert vsync signal polarity */
1662 # define LVDS_VSYNC_POLARITY_INVERT (1 << 21)
1664 /* invert hsync signal polarity */
1665 # define LVDS_HSYNC_POLARITY_INVERT (1 << 20)
1667 /* invert display enable signal polarity */
1668 # define LVDS_DE_POLARITY_INVERT (1 << 19)
1671 * Control signals for second channel, ignored in single channel modes
1674 /* send DE, HS, VS on second channel */
1675 # define LVDS_SECOND_CHANNEL_DE_HS_VS (0 << 17)
1677 # define LVDS_SECOND_CHANNEL_RESERVED (1 << 17)
1679 /* Send zeros instead of DE, HS, VS on second channel */
1680 # define LVDS_SECOND_CHANNEL_ZEROS (2 << 17)
1682 /* Set DE=0, HS=LE, VS=LF on second channel */
1683 # define LVDS_SECOND_CHANNEL_HS_VS (3 << 17)
1686 * Send duplicate data for channel reserved bits, otherwise send zeros
1688 # define LVDS_CHANNEL_DUP_RESERVED (1 << 16)
1691 * Enable border for unscaled (or aspect-scaled) display
1693 # define LVDS_BORDER_ENABLE (1 << 15)
1696 * Tri-state the LVDS buffers when powered down, otherwise
1697 * they are set to 0V
1699 # define LVDS_POWER_DOWN_TRI_STATE (1 << 10)
1702 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1705 # define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1706 # define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1707 # define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1709 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1710 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1713 # define LVDS_A3_POWER_MASK (3 << 6)
1714 # define LVDS_A3_POWER_DOWN (0 << 6)
1715 # define LVDS_A3_POWER_UP (3 << 6)
1717 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1720 # define LVDS_CLKB_POWER_MASK (3 << 4)
1721 # define LVDS_CLKB_POWER_DOWN (0 << 4)
1722 # define LVDS_CLKB_POWER_UP (3 << 4)
1725 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1726 * setting for whether we are in dual-channel mode. The B3 pair will
1727 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1729 # define LVDS_B0B3_POWER_MASK (3 << 2)
1730 # define LVDS_B0B3_POWER_DOWN (0 << 2)
1731 # define LVDS_B0B3_POWER_UP (3 << 2)
1735 #define DP_B 0x64100
1736 #define DPB_AUX_CH_CTL 0x64110
1737 #define DPB_AUX_CH_DATA1 0x64114
1738 #define DPB_AUX_CH_DATA2 0x64118
1739 #define DPB_AUX_CH_DATA3 0x6411c
1740 #define DPB_AUX_CH_DATA4 0x64120
1741 #define DPB_AUX_CH_DATA5 0x64124
1743 #define DP_C 0x64200
1744 #define DPC_AUX_CH_CTL 0x64210
1745 #define DPC_AUX_CH_DATA1 0x64214
1746 #define DPC_AUX_CH_DATA2 0x64218
1747 #define DPC_AUX_CH_DATA3 0x6421c
1748 #define DPC_AUX_CH_DATA4 0x64220
1749 #define DPC_AUX_CH_DATA5 0x64224
1751 #define DP_D 0x64300
1752 #define DPD_AUX_CH_CTL 0x64310
1753 #define DPD_AUX_CH_DATA1 0x64314
1754 #define DPD_AUX_CH_DATA2 0x64318
1755 #define DPD_AUX_CH_DATA3 0x6431c
1756 #define DPD_AUX_CH_DATA4 0x64320
1757 #define DPD_AUX_CH_DATA5 0x64324
1760 * Two channel clock control. Turn this on if you need clkb for two channel mode
1761 * Overridden by global LVDS power sequencing
1765 # define LVDS_CLKB_POWER_DOWN (0 << 4)
1767 /* powered up, but clkb forced to 0 */
1768 # define LVDS_CLKB_POWER_PARTIAL (1 << 4)
1770 /* clock B running */
1771 # define LVDS_CLKB_POWER_UP (3 << 4)
1774 * Two channel mode B0-B2 control. Sets state when power is on.
1775 * Set to POWER_DOWN in single channel mode, other settings enable
1776 * two channel mode. The CLKB power control controls whether that clock
1777 * is enabled during two channel mode.
1780 /* Everything is off, including B3 and CLKB */
1781 # define LVDS_B_POWER_DOWN (0 << 2)
1783 /* B0, B1, B2 and data lines forced to 0. timing is active */
1784 # define LVDS_B_POWER_PARTIAL (1 << 2)
1786 /* data lines active (both timing and colour) */
1787 # define LVDS_B_POWER_UP (3 << 2)
1789 /** @defgroup TV_CTL
1792 #define TV_CTL 0x68000
1793 /** Enables the TV encoder */
1794 # define TV_ENC_ENABLE (1 << 31)
1795 /** Sources the TV encoder input from pipe B instead of A. */
1796 # define TV_ENC_PIPEB_SELECT (1 << 30)
1797 /** Outputs composite video (DAC A only) */
1798 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
1799 /** Outputs SVideo video (DAC B/C) */
1800 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
1801 /** Outputs Component video (DAC A/B/C) */
1802 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
1803 /** Outputs Composite and SVideo (DAC A/B/C) */
1804 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
1805 # define TV_TRILEVEL_SYNC (1 << 21)
1806 /** Enables slow sync generation (945GM only) */
1807 # define TV_SLOW_SYNC (1 << 20)
1808 /** Selects 4x oversampling for 480i and 576p */
1809 # define TV_OVERSAMPLE_4X (0 << 18)
1810 /** Selects 2x oversampling for 720p and 1080i */
1811 # define TV_OVERSAMPLE_2X (1 << 18)
1812 /** Selects no oversampling for 1080p */
1813 # define TV_OVERSAMPLE_NONE (2 << 18)
1814 /** Selects 8x oversampling */
1815 # define TV_OVERSAMPLE_8X (3 << 18)
1816 /** Selects progressive mode rather than interlaced */
1817 # define TV_PROGRESSIVE (1 << 17)
1818 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
1819 # define TV_PAL_BURST (1 << 16)
1820 /** Field for setting delay of Y compared to C */
1821 # define TV_YC_SKEW_MASK (7 << 12)
1822 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
1823 # define TV_ENC_SDP_FIX (1 << 11)
1825 * Enables a fix for the 915GM only.
1827 * Not sure what it does.
1829 # define TV_ENC_C0_FIX (1 << 10)
1830 /** Bits that must be preserved by software */
1831 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
1832 # define TV_FUSE_STATE_MASK (3 << 4)
1833 /** Read-only state that reports all features enabled */
1834 # define TV_FUSE_STATE_ENABLED (0 << 4)
1835 /** Read-only state that reports that Macrovision is disabled in hardware*/
1836 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
1837 /** Read-only state that reports that TV-out is disabled in hardware. */
1838 # define TV_FUSE_STATE_DISABLED (2 << 4)
1839 /** Normal operation */
1840 # define TV_TEST_MODE_NORMAL (0 << 0)
1841 /** Encoder test pattern 1 - combo pattern */
1842 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
1843 /** Encoder test pattern 2 - full screen vertical 75% color bars */
1844 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
1845 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
1846 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
1847 /** Encoder test pattern 4 - random noise */
1848 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
1849 /** Encoder test pattern 5 - linear color ramps */
1850 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
1852 * This test mode forces the DACs to 50% of full output.
1854 * This is used for load detection in combination with TVDAC_SENSE_MASK
1856 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
1857 # define TV_TEST_MODE_MASK (7 << 0)
1860 /** @defgroup TV_DAC
1863 #define TV_DAC 0x68004
1865 * Reports that DAC state change logic has reported change (RO).
1867 * This gets cleared when TV_DAC_STATE_EN is cleared
1869 # define TVDAC_STATE_CHG (1 << 31)
1870 # define TVDAC_SENSE_MASK (7 << 28)
1871 /** Reports that DAC A voltage is above the detect threshold */
1872 # define TVDAC_A_SENSE (1 << 30)
1873 /** Reports that DAC B voltage is above the detect threshold */
1874 # define TVDAC_B_SENSE (1 << 29)
1875 /** Reports that DAC C voltage is above the detect threshold */
1876 # define TVDAC_C_SENSE (1 << 28)
1878 * Enables DAC state detection logic, for load-based TV detection.
1880 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
1881 * to off, for load detection to work.
1883 # define TVDAC_STATE_CHG_EN (1 << 27)
1884 /** Sets the DAC A sense value to high */
1885 # define TVDAC_A_SENSE_CTL (1 << 26)
1886 /** Sets the DAC B sense value to high */
1887 # define TVDAC_B_SENSE_CTL (1 << 25)
1888 /** Sets the DAC C sense value to high */
1889 # define TVDAC_C_SENSE_CTL (1 << 24)
1890 /** Overrides the ENC_ENABLE and DAC voltage levels */
1891 # define DAC_CTL_OVERRIDE (1 << 7)
1892 /** Sets the slew rate. Must be preserved in software */
1893 # define ENC_TVDAC_SLEW_FAST (1 << 6)
1894 # define DAC_A_1_3_V (0 << 4)
1895 # define DAC_A_1_1_V (1 << 4)
1896 # define DAC_A_0_7_V (2 << 4)
1897 # define DAC_A_OFF (3 << 4)
1898 # define DAC_B_1_3_V (0 << 2)
1899 # define DAC_B_1_1_V (1 << 2)
1900 # define DAC_B_0_7_V (2 << 2)
1901 # define DAC_B_OFF (3 << 2)
1902 # define DAC_C_1_3_V (0 << 0)
1903 # define DAC_C_1_1_V (1 << 0)
1904 # define DAC_C_0_7_V (2 << 0)
1905 # define DAC_C_OFF (3 << 0)
1909 * CSC coefficients are stored in a floating point format with 9 bits of
1910 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
1911 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
1912 * -1 (0x3) being the only legal negative value.
1914 #define TV_CSC_Y 0x68010
1915 # define TV_RY_MASK 0x07ff0000
1916 # define TV_RY_SHIFT 16
1917 # define TV_GY_MASK 0x00000fff
1918 # define TV_GY_SHIFT 0
1920 #define TV_CSC_Y2 0x68014
1921 # define TV_BY_MASK 0x07ff0000
1922 # define TV_BY_SHIFT 16
1924 * Y attenuation for component video.
1926 * Stored in 1.9 fixed point.
1928 # define TV_AY_MASK 0x000003ff
1929 # define TV_AY_SHIFT 0
1931 #define TV_CSC_U 0x68018
1932 # define TV_RU_MASK 0x07ff0000
1933 # define TV_RU_SHIFT 16
1934 # define TV_GU_MASK 0x000007ff
1935 # define TV_GU_SHIFT 0
1937 #define TV_CSC_U2 0x6801c
1938 # define TV_BU_MASK 0x07ff0000
1939 # define TV_BU_SHIFT 16
1941 * U attenuation for component video.
1943 * Stored in 1.9 fixed point.
1945 # define TV_AU_MASK 0x000003ff
1946 # define TV_AU_SHIFT 0
1948 #define TV_CSC_V 0x68020
1949 # define TV_RV_MASK 0x0fff0000
1950 # define TV_RV_SHIFT 16
1951 # define TV_GV_MASK 0x000007ff
1952 # define TV_GV_SHIFT 0
1954 #define TV_CSC_V2 0x68024
1955 # define TV_BV_MASK 0x07ff0000
1956 # define TV_BV_SHIFT 16
1958 * V attenuation for component video.
1960 * Stored in 1.9 fixed point.
1962 # define TV_AV_MASK 0x000007ff
1963 # define TV_AV_SHIFT 0
1965 /** @defgroup TV_CSC_KNOBS
1968 #define TV_CLR_KNOBS 0x68028
1969 /** 2s-complement brightness adjustment */
1970 # define TV_BRIGHTNESS_MASK 0xff000000
1971 # define TV_BRIGHTNESS_SHIFT 24
1972 /** Contrast adjustment, as a 2.6 unsigned floating point number */
1973 # define TV_CONTRAST_MASK 0x00ff0000
1974 # define TV_CONTRAST_SHIFT 16
1975 /** Saturation adjustment, as a 2.6 unsigned floating point number */
1976 # define TV_SATURATION_MASK 0x0000ff00
1977 # define TV_SATURATION_SHIFT 8
1978 /** Hue adjustment, as an integer phase angle in degrees */
1979 # define TV_HUE_MASK 0x000000ff
1980 # define TV_HUE_SHIFT 0
1983 /** @defgroup TV_CLR_LEVEL
1986 #define TV_CLR_LEVEL 0x6802c
1987 /** Controls the DAC level for black */
1988 # define TV_BLACK_LEVEL_MASK 0x01ff0000
1989 # define TV_BLACK_LEVEL_SHIFT 16
1990 /** Controls the DAC level for blanking */
1991 # define TV_BLANK_LEVEL_MASK 0x000001ff
1992 # define TV_BLANK_LEVEL_SHIFT 0
1995 /** @defgroup TV_H_CTL_1
1998 #define TV_H_CTL_1 0x68030
1999 /** Number of pixels in the hsync. */
2000 # define TV_HSYNC_END_MASK 0x1fff0000
2001 # define TV_HSYNC_END_SHIFT 16
2002 /** Total number of pixels minus one in the line (display and blanking). */
2003 # define TV_HTOTAL_MASK 0x00001fff
2004 # define TV_HTOTAL_SHIFT 0
2007 /** @defgroup TV_H_CTL_2
2010 #define TV_H_CTL_2 0x68034
2011 /** Enables the colorburst (needed for non-component color) */
2012 # define TV_BURST_ENA (1 << 31)
2013 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
2014 # define TV_HBURST_START_SHIFT 16
2015 # define TV_HBURST_START_MASK 0x1fff0000
2016 /** Length of the colorburst */
2017 # define TV_HBURST_LEN_SHIFT 0
2018 # define TV_HBURST_LEN_MASK 0x0001fff
2021 /** @defgroup TV_H_CTL_3
2024 #define TV_H_CTL_3 0x68038
2025 /** End of hblank, measured in pixels minus one from start of hsync */
2026 # define TV_HBLANK_END_SHIFT 16
2027 # define TV_HBLANK_END_MASK 0x1fff0000
2028 /** Start of hblank, measured in pixels minus one from start of hsync */
2029 # define TV_HBLANK_START_SHIFT 0
2030 # define TV_HBLANK_START_MASK 0x0001fff
2033 /** @defgroup TV_V_CTL_1
2036 #define TV_V_CTL_1 0x6803c
2038 # define TV_NBR_END_SHIFT 16
2039 # define TV_NBR_END_MASK 0x07ff0000
2041 # define TV_VI_END_F1_SHIFT 8
2042 # define TV_VI_END_F1_MASK 0x00003f00
2044 # define TV_VI_END_F2_SHIFT 0
2045 # define TV_VI_END_F2_MASK 0x0000003f
2048 /** @defgroup TV_V_CTL_2
2051 #define TV_V_CTL_2 0x68040
2052 /** Length of vsync, in half lines */
2053 # define TV_VSYNC_LEN_MASK 0x07ff0000
2054 # define TV_VSYNC_LEN_SHIFT 16
2055 /** Offset of the start of vsync in field 1, measured in one less than the
2056 * number of half lines.
2058 # define TV_VSYNC_START_F1_MASK 0x00007f00
2059 # define TV_VSYNC_START_F1_SHIFT 8
2061 * Offset of the start of vsync in field 2, measured in one less than the
2062 * number of half lines.
2064 # define TV_VSYNC_START_F2_MASK 0x0000007f
2065 # define TV_VSYNC_START_F2_SHIFT 0
2068 /** @defgroup TV_V_CTL_3
2071 #define TV_V_CTL_3 0x68044
2072 /** Enables generation of the equalization signal */
2073 # define TV_EQUAL_ENA (1 << 31)
2074 /** Length of vsync, in half lines */
2075 # define TV_VEQ_LEN_MASK 0x007f0000
2076 # define TV_VEQ_LEN_SHIFT 16
2077 /** Offset of the start of equalization in field 1, measured in one less than
2078 * the number of half lines.
2080 # define TV_VEQ_START_F1_MASK 0x0007f00
2081 # define TV_VEQ_START_F1_SHIFT 8
2083 * Offset of the start of equalization in field 2, measured in one less than
2084 * the number of half lines.
2086 # define TV_VEQ_START_F2_MASK 0x000007f
2087 # define TV_VEQ_START_F2_SHIFT 0
2090 /** @defgroup TV_V_CTL_4
2093 #define TV_V_CTL_4 0x68048
2095 * Offset to start of vertical colorburst, measured in one less than the
2096 * number of lines from vertical start.
2098 # define TV_VBURST_START_F1_MASK 0x003f0000
2099 # define TV_VBURST_START_F1_SHIFT 16
2101 * Offset to the end of vertical colorburst, measured in one less than the
2102 * number of lines from the start of NBR.
2104 # define TV_VBURST_END_F1_MASK 0x000000ff
2105 # define TV_VBURST_END_F1_SHIFT 0
2108 /** @defgroup TV_V_CTL_5
2111 #define TV_V_CTL_5 0x6804c
2113 * Offset to start of vertical colorburst, measured in one less than the
2114 * number of lines from vertical start.
2116 # define TV_VBURST_START_F2_MASK 0x003f0000
2117 # define TV_VBURST_START_F2_SHIFT 16
2119 * Offset to the end of vertical colorburst, measured in one less than the
2120 * number of lines from the start of NBR.
2122 # define TV_VBURST_END_F2_MASK 0x000000ff
2123 # define TV_VBURST_END_F2_SHIFT 0
2126 /** @defgroup TV_V_CTL_6
2129 #define TV_V_CTL_6 0x68050
2131 * Offset to start of vertical colorburst, measured in one less than the
2132 * number of lines from vertical start.
2134 # define TV_VBURST_START_F3_MASK 0x003f0000
2135 # define TV_VBURST_START_F3_SHIFT 16
2137 * Offset to the end of vertical colorburst, measured in one less than the
2138 * number of lines from the start of NBR.
2140 # define TV_VBURST_END_F3_MASK 0x000000ff
2141 # define TV_VBURST_END_F3_SHIFT 0
2144 /** @defgroup TV_V_CTL_7
2147 #define TV_V_CTL_7 0x68054
2149 * Offset to start of vertical colorburst, measured in one less than the
2150 * number of lines from vertical start.
2152 # define TV_VBURST_START_F4_MASK 0x003f0000
2153 # define TV_VBURST_START_F4_SHIFT 16
2155 * Offset to the end of vertical colorburst, measured in one less than the
2156 * number of lines from the start of NBR.
2158 # define TV_VBURST_END_F4_MASK 0x000000ff
2159 # define TV_VBURST_END_F4_SHIFT 0
2162 /** @defgroup TV_SC_CTL_1
2165 #define TV_SC_CTL_1 0x68060
2166 /** Turns on the first subcarrier phase generation DDA */
2167 # define TV_SC_DDA1_EN (1 << 31)
2168 /** Turns on the first subcarrier phase generation DDA */
2169 # define TV_SC_DDA2_EN (1 << 30)
2170 /** Turns on the first subcarrier phase generation DDA */
2171 # define TV_SC_DDA3_EN (1 << 29)
2172 /** Sets the subcarrier DDA to reset frequency every other field */
2173 # define TV_SC_RESET_EVERY_2 (0 << 24)
2174 /** Sets the subcarrier DDA to reset frequency every fourth field */
2175 # define TV_SC_RESET_EVERY_4 (1 << 24)
2176 /** Sets the subcarrier DDA to reset frequency every eighth field */
2177 # define TV_SC_RESET_EVERY_8 (2 << 24)
2178 /** Sets the subcarrier DDA to never reset the frequency */
2179 # define TV_SC_RESET_NEVER (3 << 24)
2180 /** Sets the peak amplitude of the colorburst.*/
2181 # define TV_BURST_LEVEL_MASK 0x00ff0000
2182 # define TV_BURST_LEVEL_SHIFT 16
2183 /** Sets the increment of the first subcarrier phase generation DDA */
2184 # define TV_SCDDA1_INC_MASK 0x00000fff
2185 # define TV_SCDDA1_INC_SHIFT 0
2188 /** @defgroup TV_SC_CTL_2
2191 #define TV_SC_CTL_2 0x68064
2192 /** Sets the rollover for the second subcarrier phase generation DDA */
2193 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
2194 # define TV_SCDDA2_SIZE_SHIFT 16
2195 /** Sets the increent of the second subcarrier phase generation DDA */
2196 # define TV_SCDDA2_INC_MASK 0x00007fff
2197 # define TV_SCDDA2_INC_SHIFT 0
2200 /** @defgroup TV_SC_CTL_3
2203 #define TV_SC_CTL_3 0x68068
2204 /** Sets the rollover for the third subcarrier phase generation DDA */
2205 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
2206 # define TV_SCDDA3_SIZE_SHIFT 16
2207 /** Sets the increent of the third subcarrier phase generation DDA */
2208 # define TV_SCDDA3_INC_MASK 0x00007fff
2209 # define TV_SCDDA3_INC_SHIFT 0
2212 /** @defgroup TV_WIN_POS
2215 #define TV_WIN_POS 0x68070
2216 /** X coordinate of the display from the start of horizontal active */
2217 # define TV_XPOS_MASK 0x1fff0000
2218 # define TV_XPOS_SHIFT 16
2219 /** Y coordinate of the display from the start of vertical active (NBR) */
2220 # define TV_YPOS_MASK 0x00000fff
2221 # define TV_YPOS_SHIFT 0
2224 /** @defgroup TV_WIN_SIZE
2227 #define TV_WIN_SIZE 0x68074
2228 /** Horizontal size of the display window, measured in pixels*/
2229 # define TV_XSIZE_MASK 0x1fff0000
2230 # define TV_XSIZE_SHIFT 16
2232 * Vertical size of the display window, measured in pixels.
2234 * Must be even for interlaced modes.
2236 # define TV_YSIZE_MASK 0x00000fff
2237 # define TV_YSIZE_SHIFT 0
2240 /** @defgroup TV_FILTER_CTL_1
2243 #define TV_FILTER_CTL_1 0x68080
2245 * Enables automatic scaling calculation.
2247 * If set, the rest of the registers are ignored, and the calculated values can
2248 * be read back from the register.
2250 # define TV_AUTO_SCALE (1 << 31)
2252 * Disables the vertical filter.
2254 * This is required on modes more than 1024 pixels wide */
2255 # define TV_V_FILTER_BYPASS (1 << 29)
2256 /** Enables adaptive vertical filtering */
2257 # define TV_VADAPT (1 << 28)
2258 # define TV_VADAPT_MODE_MASK (3 << 26)
2259 /** Selects the least adaptive vertical filtering mode */
2260 # define TV_VADAPT_MODE_LEAST (0 << 26)
2261 /** Selects the moderately adaptive vertical filtering mode */
2262 # define TV_VADAPT_MODE_MODERATE (1 << 26)
2263 /** Selects the most adaptive vertical filtering mode */
2264 # define TV_VADAPT_MODE_MOST (3 << 26)
2266 * Sets the horizontal scaling factor.
2268 * This should be the fractional part of the horizontal scaling factor divided
2269 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
2271 * (src width - 1) / ((oversample * dest width) - 1)
2273 # define TV_HSCALE_FRAC_MASK 0x00003fff
2274 # define TV_HSCALE_FRAC_SHIFT 0
2277 /** @defgroup TV_FILTER_CTL_2
2280 #define TV_FILTER_CTL_2 0x68084
2282 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2284 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2286 # define TV_VSCALE_INT_MASK 0x00038000
2287 # define TV_VSCALE_INT_SHIFT 15
2289 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2291 * \sa TV_VSCALE_INT_MASK
2293 # define TV_VSCALE_FRAC_MASK 0x00007fff
2294 # define TV_VSCALE_FRAC_SHIFT 0
2297 /** @defgroup TV_FILTER_CTL_3
2300 #define TV_FILTER_CTL_3 0x68088
2302 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2304 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2306 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2308 # define TV_VSCALE_IP_INT_MASK 0x00038000
2309 # define TV_VSCALE_IP_INT_SHIFT 15
2311 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2313 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2315 * \sa TV_VSCALE_IP_INT_MASK
2317 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
2318 # define TV_VSCALE_IP_FRAC_SHIFT 0
2321 /** @defgroup TV_CC_CONTROL
2324 #define TV_CC_CONTROL 0x68090
2325 # define TV_CC_ENABLE (1 << 31)
2327 * Specifies which field to send the CC data in.
2329 * CC data is usually sent in field 0.
2331 # define TV_CC_FID_MASK (1 << 27)
2332 # define TV_CC_FID_SHIFT 27
2333 /** Sets the horizontal position of the CC data. Usually 135. */
2334 # define TV_CC_HOFF_MASK 0x03ff0000
2335 # define TV_CC_HOFF_SHIFT 16
2336 /** Sets the vertical position of the CC data. Usually 21 */
2337 # define TV_CC_LINE_MASK 0x0000003f
2338 # define TV_CC_LINE_SHIFT 0
2341 /** @defgroup TV_CC_DATA
2344 #define TV_CC_DATA 0x68094
2345 # define TV_CC_RDY (1 << 31)
2346 /** Second word of CC data to be transmitted. */
2347 # define TV_CC_DATA_2_MASK 0x007f0000
2348 # define TV_CC_DATA_2_SHIFT 16
2349 /** First word of CC data to be transmitted. */
2350 # define TV_CC_DATA_1_MASK 0x0000007f
2351 # define TV_CC_DATA_1_SHIFT 0
2356 #define TV_H_LUMA_0 0x68100
2357 #define TV_H_LUMA_59 0x681ec
2358 #define TV_H_CHROMA_0 0x68200
2359 #define TV_H_CHROMA_59 0x682ec
2360 #define TV_V_LUMA_0 0x68300
2361 #define TV_V_LUMA_42 0x683a8
2362 #define TV_V_CHROMA_0 0x68400
2363 #define TV_V_CHROMA_42 0x684a8
2366 #define PIPEA_DSL 0x70000
2368 #define PIPEACONF 0x70008
2369 #define PIPEACONF_ENABLE (1<<31)
2370 #define PIPEACONF_DISABLE 0
2371 #define PIPEACONF_DOUBLE_WIDE (1<<30)
2372 #define I965_PIPECONF_ACTIVE (1<<30)
2373 #define PIPEACONF_SINGLE_WIDE 0
2374 #define PIPEACONF_PIPE_UNLOCKED 0
2375 #define PIPEACONF_PIPE_LOCKED (1<<25)
2376 #define PIPEACONF_PALETTE 0
2377 #define PIPEACONF_GAMMA (1<<24)
2378 #define PIPECONF_FORCE_BORDER (1<<25)
2379 #define PIPECONF_PROGRESSIVE (0 << 21)
2380 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2381 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
2382 /* ironlake: gamma */
2383 #define PIPECONF_PALETTE_8BIT (0<<24)
2384 #define PIPECONF_PALETTE_10BIT (1<<24)
2385 #define PIPECONF_PALETTE_12BIT (2<<24)
2386 #define PIPECONF_FORCE_BORDER (1<<25)
2387 #define PIPECONF_PROGRESSIVE (0 << 21)
2388 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2389 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
2391 #define PIPECONF_MSA_TIMING_DELAY (0<<18) /* for eDP */
2392 #define PIPECONF_NO_DYNAMIC_RATE_CHANGE (0 << 16)
2393 #define PIPECONF_NO_ROTATION (0<<14)
2394 #define PIPECONF_FULL_COLOR_RANGE (0<<13)
2395 #define PIPECONF_CE_COLOR_RANGE (1<<13)
2396 #define PIPECONF_COLOR_SPACE_RGB (0<<11)
2397 #define PIPECONF_COLOR_SPACE_YUV601 (1<<11)
2398 #define PIPECONF_COLOR_SPACE_YUV709 (2<<11)
2399 #define PIPECONF_CONNECT_DEFAULT (0<<9)
2400 #define PIPECONF_8BPP (0<<5)
2401 #define PIPECONF_10BPP (1<<5)
2402 #define PIPECONF_6BPP (2<<5)
2403 #define PIPECONF_12BPP (3<<5)
2404 #define PIPECONF_ENABLE_DITHER (1<<4)
2405 #define PIPECONF_DITHER_SPATIAL (0<<2)
2406 #define PIPECONF_DITHER_ST1 (1<<2)
2407 #define PIPECONF_DITHER_ST2 (2<<2)
2408 #define PIPECONF_DITHER_TEMPORAL (3<<2)
2410 #define PIPEAGCMAXRED 0x70010
2411 #define PIPEAGCMAXGREEN 0x70014
2412 #define PIPEAGCMAXBLUE 0x70018
2413 #define PIPEASTAT 0x70024
2414 # define FIFO_UNDERRUN (1 << 31)
2415 # define CRC_ERROR_ENABLE (1 << 29)
2416 # define CRC_DONE_ENABLE (1 << 28)
2417 # define GMBUS_EVENT_ENABLE (1 << 27)
2418 # define VSYNC_INT_ENABLE (1 << 25)
2419 # define DLINE_COMPARE_ENABLE (1 << 24)
2420 # define DPST_EVENT_ENABLE (1 << 23)
2421 # define LBLC_EVENT_ENABLE (1 << 22)
2422 # define OFIELD_INT_ENABLE (1 << 21)
2423 # define EFIELD_INT_ENABLE (1 << 20)
2424 # define SVBLANK_INT_ENABLE (1 << 18)
2425 # define VBLANK_INT_ENABLE (1 << 17)
2426 # define OREG_UPDATE_ENABLE (1 << 16)
2427 # define CRC_ERROR_INT_STATUS (1 << 13)
2428 # define CRC_DONE_INT_STATUS (1 << 12)
2429 # define GMBUS_INT_STATUS (1 << 11)
2430 # define VSYNC_INT_STATUS (1 << 9)
2431 # define DLINE_COMPARE_STATUS (1 << 8)
2432 # define DPST_EVENT_STATUS (1 << 7)
2433 # define LBLC_EVENT_STATUS (1 << 6)
2434 # define OFIELD_INT_STATUS (1 << 5)
2435 # define EFIELD_INT_STATUS (1 << 4)
2436 # define SVBLANK_INT_STATUS (1 << 2)
2437 # define VBLANK_INT_STATUS (1 << 1)
2438 # define OREG_UPDATE_STATUS (1 << 0)
2441 #define DSPARB 0x70030
2442 #define DSPARB_CSTART_SHIFT 7
2443 #define DSPARB_BSTART_SHIFT 0
2444 #define DSPARB_BEND_SHIFT 9 /* on 855 */
2445 #define DSPARB_AEND_SHIFT 0
2446 #define DSPFW1 0x70034
2447 #define DSPFW2 0x70038
2448 #define DSPFW3 0x7003c
2450 * The two pipe frame counter registers are not synchronized, so
2451 * reading a stable value is somewhat tricky. The following code
2455 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> PIPE_FRAME_HIGH_SHIFT;
2456 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> PIPE_FRAME_LOW_SHIFT);
2457 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> PIPE_FRAME_HIGH_SHIFT);
2458 * } while (high1 != high2);
2459 * frame = (high1 << 8) | low1;
2461 #define PIPEAFRAMEHIGH 0x70040
2462 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
2463 #define PIPE_FRAME_HIGH_SHIFT 0
2464 #define PIPEAFRAMEPIXEL 0x70044
2465 #define PIPE_FRAME_LOW_MASK 0xff000000
2466 #define PIPE_FRAME_LOW_SHIFT 24
2468 * Pixel within the current frame is counted in the PIPEAFRAMEPIXEL register
2469 * and is 24 bits wide.
2471 #define PIPE_PIXEL_MASK 0x00ffffff
2472 #define PIPE_PIXEL_SHIFT 0
2475 * Computing GMCH M and N values.
2477 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2479 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2481 * The GMCH value is used internally
2483 #define PIPEA_GMCH_DATA_M 0x70050
2485 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2486 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
2487 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
2489 #define PIPE_GMCH_DATA_M_MASK (0xffffff)
2491 #define PIPEA_GMCH_DATA_N 0x70054
2492 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
2495 * Computing Link M and N values.
2497 * Link M / N = pixel_clock / ls_clk
2499 * (the DP spec calls pixel_clock the 'strm_clk')
2501 * The Link value is transmitted in the Main Stream
2502 * Attributes and VB-ID.
2505 #define PIPEA_DP_LINK_M 0x70060
2506 #define PIPEA_DP_LINK_M_MASK (0xffffff)
2508 #define PIPEA_DP_LINK_N 0x70064
2509 #define PIPEA_DP_LINK_N_MASK (0xffffff)
2511 #define PIPEB_DSL 0x71000
2513 #define PIPEBCONF 0x71008
2515 #define PIPEBGCMAXRED 0x71010
2516 #define PIPEBGCMAXGREEN 0x71014
2517 #define PIPEBGCMAXBLUE 0x71018
2518 #define PIPEBSTAT 0x71024
2519 #define PIPEBFRAMEHIGH 0x71040
2520 #define PIPEBFRAMEPIXEL 0x71044
2522 #define PIPEB_GMCH_DATA_M 0x71050
2523 #define PIPEB_GMCH_DATA_N 0x71054
2524 #define PIPEB_DP_LINK_M 0x71060
2525 #define PIPEB_DP_LINK_N 0x71064
2527 #define PIPECCONF 0x72008
2529 #define PIPECGCMAXRED 0x72010
2530 #define PIPECGCMAXGREEN 0x72014
2531 #define PIPECGCMAXBLUE 0x72018
2532 #define PIPECSTAT 0x72024
2533 #define PIPECFRAMEHIGH 0x72040
2534 #define PIPECFRAMEPIXEL 0x72044
2536 #define PIPEC_GMCH_DATA_M 0x72050
2537 #define PIPEC_GMCH_DATA_N 0x72054
2538 #define PIPEC_DP_LINK_M 0x72060
2539 #define PIPEC_DP_LINK_N 0x72064
2541 #define DSPACNTR 0x70180
2542 #define DSPBCNTR 0x71180
2543 #define DSPCCNTR 0x72180
2544 #define DISPLAY_PLANE_ENABLE (1<<31)
2545 #define DISPLAY_PLANE_DISABLE 0
2546 #define DISPLAY_PLANE_TILED (1<<10)
2547 #define DISPPLANE_GAMMA_ENABLE (1<<30)
2548 #define DISPPLANE_GAMMA_DISABLE 0
2549 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
2550 #define DISPPLANE_8BPP (0x2<<26)
2551 #define DISPPLANE_15_16BPP (0x4<<26)
2552 #define DISPPLANE_16BPP (0x5<<26)
2553 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
2554 #define DISPPLANE_32BPP (0x7<<26)
2555 #define DISPPLANE_STEREO_ENABLE (1<<25)
2556 #define DISPPLANE_STEREO_DISABLE 0
2557 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
2558 #define DISPPLANE_SEL_PIPE_A 0
2559 #define DISPPLANE_SEL_PIPE_B (1<<24)
2560 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
2561 #define DISPPLANE_SRC_KEY_DISABLE 0
2562 #define DISPPLANE_LINE_DOUBLE (1<<20)
2563 #define DISPPLANE_NO_LINE_DOUBLE 0
2564 #define DISPPLANE_STEREO_POLARITY_FIRST 0
2565 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
2567 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
2568 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
2569 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
2570 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
2572 #define DSPABASE 0x70184
2573 #define DSPASTRIDE 0x70188
2575 #define DSPBBASE 0x71184
2576 #define DSPBADDR DSPBBASE
2577 #define DSPBSTRIDE 0x71188
2579 #define DSPCBASE 0x72184
2580 #define DSPCADDR DSPCBASE
2581 #define DSPCSTRIDE 0x72188
2583 #define DSPAKEYVAL 0x70194
2584 #define DSPAKEYMASK 0x70198
2586 #define DSPAPOS 0x7018C /* reserved */
2587 #define DSPASIZE 0x70190
2588 #define DSPBPOS 0x7118C
2589 #define DSPBSIZE 0x71190
2591 #define DSPASURF 0x7019C
2592 #define DSPATILEOFF 0x701A4
2594 #define DSPBSURF 0x7119C
2595 #define DSPBTILEOFF 0x711A4
2597 #define DSPCSURF 0x7219C
2598 #define DSPCTILEOFF 0x721A4
2600 #define VGACNTRL 0x71400
2601 # define VGA_DISP_DISABLE (1 << 31)
2602 # define VGA_2X_MODE (1 << 30)
2603 # define VGA_PIPE_B_SELECT (1 << 29)
2605 /* Various masks for reserved bits, etc. */
2606 #define I830_FWATER1_MASK (~((1<<11)|(1<<10)|(1<<9)| \
2607 (1<<8)|(1<<26)|(1<<25)|(1<<24)|(1<<5)|(1<<4)|(1<<3)| \
2608 (1<<2)|(1<<1)|1|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)))
2609 #define I830_FWATER2_MASK ~(0)
2611 #define DV0A_RESERVED ((1<<26)|(1<<25)|(1<<24)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<16)|(1<<5)|(1<<1)|1)
2612 #define DV0B_RESERVED ((1<<27)|(1<<26)|(1<<25)|(1<<24)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<16)|(1<<5)|(1<<1)|1)
2613 #define VGA0_N_DIVISOR_MASK ((1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16))
2614 #define VGA0_M1_DIVISOR_MASK ((1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8))
2615 #define VGA0_M2_DIVISOR_MASK ((1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|1)
2616 #define VGA0_M1M2N_RESERVED ~(VGA0_N_DIVISOR_MASK|VGA0_M1_DIVISOR_MASK|VGA0_M2_DIVISOR_MASK)
2617 #define VGA0_POSTDIV_MASK ((1<<7)|(1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|1)
2618 #define VGA1_POSTDIV_MASK ((1<<15)|(1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8))
2619 #define VGA_POSTDIV_RESERVED ~(VGA0_POSTDIV_MASK|VGA1_POSTDIV_MASK|(1<<7)|(1<<15))
2620 #define DPLLA_POSTDIV_MASK ((1<<23)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16))
2621 #define DPLLA_RESERVED ((1<<27)|(1<<26)|(1<<25)|(1<<24)|(1<<22)|(1<<15)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8)|(1<<7)|(1<<6)|(1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|1)
2622 #define ADPA_RESERVED ((1<<2)|(1<<1)|1|(1<<9)|(1<<8)|(1<<7)|(1<<6)|(1<<5)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(1<<26)|(1<<25)|(1<<24)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16))
2623 #define SUPER_WORD 32
2624 #define BURST_A_MASK ((1<<11)|(1<<10)|(1<<9)|(1<<8))
2625 #define BURST_B_MASK ((1<<26)|(1<<25)|(1<<24))
2626 #define WATER_A_MASK ((1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|1)
2627 #define WATER_B_MASK ((1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16))
2628 #define WATER_RESERVED ((1<<31)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(1<<23)|(1<<22)|(1<<21)|(1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<7)|(1<<6))
2629 #define PIPEACONF_RESERVED ((1<<29)|(1<<28)|(1<<27)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)|0xffff)
2630 #define PIPEBCONF_RESERVED ((1<<30)|(1<<29)|(1<<28)|(1<<27)|(1<<26)|(1<<25)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)|0xffff)
2631 #define DSPACNTR_RESERVED ((1<<23)|(1<<19)|(1<<17)|(1<<16)|0xffff)
2632 #define DSPBCNTR_RESERVED ((1<<23)|(1<<19)|(1<<17)|(1<<16)|0x7ffe)
2634 #define I830_GMCH_CTRL 0x52
2636 #define I830_GMCH_ENABLED 0x4
2637 #define I830_GMCH_MEM_MASK 0x1
2638 #define I830_GMCH_MEM_64M 0x1
2639 #define I830_GMCH_MEM_128M 0
2641 #define I830_GMCH_GMS_MASK 0x70
2642 #define I830_GMCH_GMS_DISABLED 0x00
2643 #define I830_GMCH_GMS_LOCAL 0x10
2644 #define I830_GMCH_GMS_STOLEN_512 0x20
2645 #define I830_GMCH_GMS_STOLEN_1024 0x30
2646 #define I830_GMCH_GMS_STOLEN_8192 0x40
2648 #define I830_RDRAM_CHANNEL_TYPE 0x03010
2649 #define I830_RDRAM_ND(x) (((x) & 0x20) >> 5)
2650 #define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3)
2652 #define I855_GMCH_GMS_MASK (0xF << 4)
2653 #define I855_GMCH_GMS_DISABLED 0x00
2654 #define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
2655 #define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
2656 #define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
2657 #define I855_GMCH_GMS_STOLEN_16M (0x4 << 4)
2658 #define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
2659 #define I915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
2660 #define I915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
2661 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
2662 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
2663 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
2664 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
2665 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
2666 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
2669 #define I85X_CAPID 0x44
2670 #define I85X_VARIANT_MASK 0x7
2671 #define I85X_VARIANT_SHIFT 5
2672 #define I855_GME 0x0
2674 #define I852_GME 0x2
2677 #define I915_GCFGC 0xf0
2678 #define I915_LOW_FREQUENCY_ENABLE (1 << 7)
2679 #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
2680 #define I915_DISPLAY_CLOCK_333_MHZ (4 << 4)
2681 #define I915_DISPLAY_CLOCK_MASK (7 << 4)
2683 #define I855_HPLLCC 0xc0
2684 #define I855_CLOCK_CONTROL_MASK (3 << 0)
2685 #define I855_CLOCK_133_200 (0 << 0)
2686 #define I855_CLOCK_100_200 (1 << 0)
2687 #define I855_CLOCK_100_133 (2 << 0)
2688 #define I855_CLOCK_166_250 (3 << 0)
2691 #define COLOR_BLT_CMD ((2<<29)|(0x40<<22)|(0x3))
2692 #define COLOR_BLT_WRITE_ALPHA (1<<21)
2693 #define COLOR_BLT_WRITE_RGB (1<<20)
2695 #define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|(0x4))
2696 #define XY_COLOR_BLT_WRITE_ALPHA (1<<21)
2697 #define XY_COLOR_BLT_WRITE_RGB (1<<20)
2698 #define XY_COLOR_BLT_TILED (1<<11)
2700 #define XY_SETUP_CLIP_BLT_CMD ((2<<29)|(3<<22)|1)
2702 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
2703 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
2704 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
2705 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15)
2706 #define XY_SRC_COPY_BLT_DST_TILED (1<<11)
2708 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|0x4)
2709 #define SRC_COPY_BLT_WRITE_ALPHA (1<<21)
2710 #define SRC_COPY_BLT_WRITE_RGB (1<<20)
2712 #define XY_PAT_BLT_IMMEDIATE ((2<<29)|(0x72<<22))
2714 #define XY_MONO_PAT_BLT_CMD ((0x2<<29)|(0x52<<22)|0x7)
2715 #define XY_MONO_PAT_VERT_SEED ((1<<10)|(1<<9)|(1<<8))
2716 #define XY_MONO_PAT_HORT_SEED ((1<<14)|(1<<13)|(1<<12))
2717 #define XY_MONO_PAT_BLT_WRITE_ALPHA (1<<21)
2718 #define XY_MONO_PAT_BLT_WRITE_RGB (1<<20)
2720 #define XY_MONO_SRC_BLT_CMD ((0x2<<29)|(0x54<<22)|(0x6))
2721 #define XY_MONO_SRC_BLT_WRITE_ALPHA (1<<21)
2722 #define XY_MONO_SRC_BLT_WRITE_RGB (1<<20)
2724 #define MI_STORE_DWORD_IMM ((0x20<<23)|2)
2725 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
2727 #define MI_SET_CONTEXT (0x18<<23)
2728 #define CTXT_NO_RESTORE (1)
2729 #define CTXT_PALETTE_SAVE_DISABLE (1<<3)
2730 #define CTXT_PALETTE_RESTORE_DISABLE (1<<2)
2733 #define MI_VERTEX_BUFFER (0x17<<23)
2734 #define MI_VERTEX_BUFFER_IDX(x) (x<<20)
2735 #define MI_VERTEX_BUFFER_PITCH(x) (x<<13)
2736 #define MI_VERTEX_BUFFER_WIDTH(x) (x<<6)
2738 #define MI_VERTEX_BUFFER_DISABLE (1)
2741 #define MI_OVERLAY_FLIP (0x11<<23)
2742 #define MI_OVERLAY_FLIP_CONTINUE (0<<21)
2743 #define MI_OVERLAY_FLIP_ON (1<<21)
2744 #define MI_OVERLAY_FLIP_OFF (2<<21)
2746 /* Wait for Events */
2747 #define MI_WAIT_FOR_EVENT (0x03<<23)
2748 #define MI_WAIT_FOR_PIPEB_SVBLANK (1<<18)
2749 #define MI_WAIT_FOR_PIPEA_SVBLANK (1<<17)
2750 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
2751 #define MI_WAIT_FOR_PIPEB_VBLANK (1<<7)
2752 #define MI_WAIT_FOR_PIPEA_VBLANK (1<<3)
2753 #define MI_WAIT_FOR_PIPEB_SCAN_LINE_WINDOW (1<<5)
2754 #define MI_WAIT_FOR_PIPEA_SCAN_LINE_WINDOW (1<<1)
2756 #define MI_LOAD_SCAN_LINES_INCL (0x12<<23)
2759 #define MI_FLUSH (0x04<<23)
2760 #define MI_WRITE_DIRTY_STATE (1<<4)
2761 #define MI_END_SCENE (1<<3)
2762 #define MI_GLOBAL_SNAPSHOT_COUNT_RESET (1<<3)
2763 #define MI_INHIBIT_RENDER_CACHE_FLUSH (1<<2)
2764 #define MI_STATE_INSTRUCTION_CACHE_FLUSH (1<<1)
2765 #define MI_INVALIDATE_MAP_CACHE (1<<0)
2766 /* broadwater flush bits */
2767 #define BRW_MI_GLOBAL_SNAPSHOT_RESET (1 << 3)
2770 #define MI_NOOP 0x00
2771 #define MI_NOOP_WRITE_ID (1<<22)
2772 #define MI_NOOP_ID_MASK (1<<22 - 1)
2774 #define STATE3D_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x01<<16))
2777 #define MI_BATCH_BUFFER ((0x30 << 23) | 1)
2778 #define MI_BATCH_BUFFER_START (0x31 << 23)
2779 #define MI_BATCH_BUFFER_END (0xA << 23)
2780 #define MI_BATCH_NON_SECURE (1)
2781 #define MI_BATCH_NON_SECURE_I965 (1 << 8)
2783 #define MAX_DISPLAY_PIPES 2
2797 /* What's connected to the pipes (as reported by the BIOS) */
2798 #define PIPE_ACTIVE_MASK 0xff
2799 #define PIPE_CRT_ACTIVE (1 << CrtIndex)
2800 #define PIPE_TV_ACTIVE (1 << TvIndex)
2801 #define PIPE_DFP_ACTIVE (1 << DfpIndex)
2802 #define PIPE_LCD_ACTIVE (1 << LfpIndex)
2803 #define PIPE_CRT2_ACTIVE (1 << Crt2Index)
2804 #define PIPE_TV2_ACTIVE (1 << Tv2Index)
2805 #define PIPE_DFP2_ACTIVE (1 << Dfp2Index)
2806 #define PIPE_LCD2_ACTIVE (1 << Lfp2Index)
2808 #define PIPE_SIZED_DISP_MASK (PIPE_DFP_ACTIVE | \
2812 #define PIPE_A_SHIFT 0
2813 #define PIPE_B_SHIFT 8
2814 #define PIPE_SHIFT(n) ((n) == 0 ? \
2815 PIPE_A_SHIFT : PIPE_B_SHIFT)
2818 * Some BIOS scratch area registers. The 845 (and 830?) store the amount
2819 * of video memory available to the BIOS in SWF1.
2822 #define SWF0 0x71410
2823 #define SWF1 0x71414
2824 #define SWF2 0x71418
2825 #define SWF3 0x7141c
2826 #define SWF4 0x71420
2827 #define SWF5 0x71424
2828 #define SWF6 0x71428
2831 * 855 scratch registers.
2833 #define SWF00 0x70410
2834 #define SWF01 0x70414
2835 #define SWF02 0x70418
2836 #define SWF03 0x7041c
2837 #define SWF04 0x70420
2838 #define SWF05 0x70424
2839 #define SWF06 0x70428
2849 #define SWF30 0x72414
2850 #define SWF31 0x72418
2851 #define SWF32 0x7241c
2854 * Overlay registers. These are overlay registers accessed via MMIO.
2855 * Those loaded via the overlay register page are defined in i830_video.c.
2857 #define OVADD 0x30000
2859 #define DOVSTA 0x30008
2860 #define OC_BUF (0x3<<20)
2862 #define OGAMC5 0x30010
2863 #define OGAMC4 0x30014
2864 #define OGAMC3 0x30018
2865 #define OGAMC2 0x3001c
2866 #define OGAMC1 0x30020
2867 #define OGAMC0 0x30024
2873 #define PALETTE_A 0x0a000
2874 #define PALETTE_B 0x0a800
2876 /* Framebuffer compression */
2877 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
2878 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
2879 #define FBC_CONTROL 0x03208
2880 #define FBC_CTL_EN (1<<31)
2881 #define FBC_CTL_PERIODIC (1<<30)
2882 #define FBC_CTL_INTERVAL_SHIFT (16)
2883 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
2884 #define FBC_CTL_STRIDE_SHIFT (5)
2885 #define FBC_CTL_FENCENO (1<<0)
2886 #define FBC_COMMAND 0x0320c
2887 #define FBC_CMD_COMPRESS (1<<0)
2888 #define FBC_STATUS 0x03210
2889 #define FBC_STAT_COMPRESSING (1<<31)
2890 #define FBC_STAT_COMPRESSED (1<<30)
2891 #define FBC_STAT_MODIFIED (1<<29)
2892 #define FBC_STAT_CURRENT_LINE (1<<0)
2893 #define FBC_CONTROL2 0x03214
2894 #define FBC_CTL_FENCE_DBL (0<<4)
2895 #define FBC_CTL_IDLE_IMM (0<<2)
2896 #define FBC_CTL_IDLE_FULL (1<<2)
2897 #define FBC_CTL_IDLE_LINE (2<<2)
2898 #define FBC_CTL_IDLE_DEBUG (3<<2)
2899 #define FBC_CTL_CPU_FENCE (1<<1)
2900 #define FBC_CTL_PLANEA (0<<0)
2901 #define FBC_CTL_PLANEB (1<<0)
2902 #define FBC_FENCE_OFF 0x0321b
2903 #define FBC_MOD_NUM 0x03220
2904 #define FBC_TAG_DEBUG 0x03300
2906 #define FBC_LL_SIZE (1536)
2907 #define FBC_LL_PAD (32)
2909 /* Framebuffer compression version 2 */
2910 #define DPFC_CB_BASE 0x3200
2911 #define DPFC_CONTROL 0x3208
2912 #define DPFC_CTL_EN (1<<31)
2913 #define DPFC_CTL_PLANEA (0<<30)
2914 #define DPFC_CTL_PLANEB (1<<30)
2915 #define DPFC_CTL_FENCE_EN (1<<29)
2916 #define DPFC_CTL_LIMIT_1X (0<<6)
2917 #define DPFC_CTL_LIMIT_2X (1<<6)
2918 #define DPFC_CTL_LIMIT_4X (2<<6)
2919 #define DPFC_RECOMP_CTL 0x320c
2920 #define DPFC_RECOMP_STALL_EN (1<<27)
2921 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
2922 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
2923 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
2924 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
2925 #define DPFC_STATUS 0x3210
2926 #define DPFC_INVAL_SEG_SHIFT (16)
2927 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
2928 #define DPFC_COMP_SEG_SHIFT (0)
2929 #define DPFC_COMP_SEG_MASK (0x000003ff)
2930 #define DPFC_STATUS2 0x3214
2931 #define DPFC_FENCE_YOFF 0x3218
2933 #define PEG_BAND_GAP_DATA 0x14d68
2935 #define MCHBAR_RENDER_STANDBY 0x111B8
2936 #define RENDER_STANDBY_ENABLE (1 << 30)
2941 /* warmup time in us */
2942 #define WARMUP_PCH_REF_CLK_SSC_MOD 1
2943 #define WARMUP_PCH_FDI_RECEIVER_PLL 25
2944 #define WARMUP_PCH_DPLL 50
2945 #define WARMUP_CPU_DP_PLL 20
2946 #define WARMUP_CPU_FDI_TRANSMITTER_PLL 10
2947 #define WARMUP_DMI_LATENCY 20
2948 #define FDI_TRAIN_PATTERN_1_TIME 0.5
2949 #define FDI_TRAIN_PATTERN_2_TIME 1.5
2950 #define FDI_ONE_IDLE_PATTERN_TIME 31
2952 #define CPU_VGACNTRL 0x41000
2954 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
2955 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
2956 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
2957 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
2958 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
2959 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
2960 #define DIGITAL_PORTA_NO_DETECT (0 << 0)
2961 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
2962 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
2964 /* refresh rate hardware control */
2965 #define RR_HW_CTL 0x45300
2966 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
2967 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
2969 #define FDI_PLL_BIOS_0 0x46000
2970 #define FDI_PLL_BIOS_1 0x46004
2971 #define FDI_PLL_BIOS_2 0x46008
2972 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
2973 #define DISPLAY_PORT_PLL_BIOS_1 0x46010
2974 #define DISPLAY_PORT_PLL_BIOS_2 0x46014
2976 #define FDI_PLL_FREQ_CTL 0x46030
2977 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
2978 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
2979 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
2981 #define PIPEA_DATA_M1 0x60030
2982 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
2983 #define TU_SIZE_MASK 0x7e000000
2984 #define PIPEA_DATA_M1_OFFSET 0
2985 #define PIPEA_DATA_N1 0x60034
2986 #define PIPEA_DATA_N1_OFFSET 0
2988 #define PIPEA_DATA_M2 0x60038
2989 #define PIPEA_DATA_M2_OFFSET 0
2990 #define PIPEA_DATA_N2 0x6003c
2991 #define PIPEA_DATA_N2_OFFSET 0
2993 #define PIPEA_LINK_M1 0x60040
2994 #define PIPEA_LINK_M1_OFFSET 0
2995 #define PIPEA_LINK_N1 0x60044
2996 #define PIPEA_LINK_N1_OFFSET 0
2998 #define PIPEA_LINK_M2 0x60048
2999 #define PIPEA_LINK_M2_OFFSET 0
3000 #define PIPEA_LINK_N2 0x6004c
3001 #define PIPEA_LINK_N2_OFFSET 0
3003 /* PIPEB timing regs are same start from 0x61000 */
3005 #define PIPEB_DATA_M1 0x61030
3006 #define PIPEB_DATA_N1 0x61034
3008 #define PIPEB_DATA_M2 0x61038
3009 #define PIPEB_DATA_N2 0x6103c
3011 #define PIPEB_LINK_M1 0x61040
3012 #define PIPEB_LINK_N1 0x61044
3014 #define PIPEB_LINK_M2 0x61048
3015 #define PIPEB_LINK_N2 0x6104c
3017 /* PIPEC timing regs */
3019 #define PIPEC_DATA_M1 0x62030
3020 #define PIPEC_DATA_N1 0x62034
3022 #define PIPEC_DATA_M2 0x62038
3023 #define PIPEC_DATA_N2 0x6203c
3025 #define PIPEC_LINK_M1 0x62040
3026 #define PIPEC_LINK_N1 0x62044
3028 #define PIPEC_LINK_M2 0x62048
3029 #define PIPEC_LINK_N2 0x6204c
3031 /* PIPECONF for pipe A/B addr is same */
3033 /* cusor A is only connected to pipe A,
3034 cursor B is connected to pipe B. Otherwise no change. */
3036 /* Plane A/B, DSPACNTR/DSPBCNTR addr not changed */
3038 /* CPU panel fitter */
3039 #define PFA_CTL_1 0x68080
3040 #define PFB_CTL_1 0x68880
3041 #define PFC_CTL_1 0x69080
3042 #define PF_ENABLE (1<<31)
3043 #define PFA_CTL_2 0x68084
3044 #define PFB_CTL_2 0x68884
3045 #define PFC_CTL_2 0x69084
3046 #define PFA_CTL_3 0x68088
3047 #define PFB_CTL_3 0x68888
3048 #define PFC_CTL_3 0x69088
3049 #define PFA_CTL_4 0x68090
3050 #define PFB_CTL_4 0x68890
3051 #define PFC_CTL_4 0x69090
3053 #define PFA_WIN_POS 0x68070
3054 #define PFB_WIN_POS 0x68870
3055 #define PFC_WIN_POS 0x69070
3056 #define PFA_WIN_SIZE 0x68074
3057 #define PFB_WIN_SIZE 0x68874
3058 #define PFC_WIN_SIZE 0x69074
3060 /* legacy palette */
3061 #define LGC_PALETTE_A 0x4a000
3062 #define LGC_PALETTE_B 0x4a800
3065 #define DE_MASTER_IRQ_CONTROL (1 << 31)
3066 #define DE_SPRITEB_FLIP_DONE (1 << 29)
3067 #define DE_SPRITEA_FLIP_DONE (1 << 28)
3068 #define DE_PLANEB_FLIP_DONE (1 << 27)
3069 #define DE_PLANEA_FLIP_DONE (1 << 26)
3070 #define DE_PCU_EVENT (1 << 25)
3071 #define DE_GTT_FAULT (1 << 24)
3072 #define DE_POISON (1 << 23)
3073 #define DE_PERFORM_COUNTER (1 << 22)
3074 #define DE_PCH_EVENT (1 << 21)
3075 #define DE_AUX_CHANNEL_A (1 << 20)
3076 #define DE_DP_A_HOTPLUG (1 << 19)
3077 #define DE_GSE (1 << 18)
3078 #define DE_PIPEB_VBLANK (1 << 15)
3079 #define DE_PIPEB_EVEN_FIELD (1 << 14)
3080 #define DE_PIPEB_ODD_FIELD (1 << 13)
3081 #define DE_PIPEB_LINE_COMPARE (1 << 12)
3082 #define DE_PIPEB_VSYNC (1 << 11)
3083 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
3084 #define DE_PIPEA_VBLANK (1 << 7)
3085 #define DE_PIPEA_EVEN_FIELD (1 << 6)
3086 #define DE_PIPEA_ODD_FIELD (1 << 5)
3087 #define DE_PIPEA_LINE_COMPARE (1 << 4)
3088 #define DE_PIPEA_VSYNC (1 << 3)
3089 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
3091 #define DEISR 0x44000
3092 #define DEIMR 0x44004
3093 #define DEIIR 0x44008
3094 #define DEIER 0x4400c
3097 #define GT_SYNC_STATUS (1 << 2)
3098 #define GT_USER_INTERRUPT (1 << 0)
3100 #define GTISR 0x44010
3101 #define GTIMR 0x44014
3102 #define GTIIR 0x44018
3103 #define GTIER 0x4401c
3107 /* south display engine interrupt */
3108 #define SDE_CRT_HOTPLUG (1 << 11)
3109 #define SDE_PORTD_HOTPLUG (1 << 10)
3110 #define SDE_PORTC_HOTPLUG (1 << 9)
3111 #define SDE_PORTB_HOTPLUG (1 << 8)
3112 #define SDE_SDVOB_HOTPLUG (1 << 6)
3114 #define SDEISR 0xc4000
3115 #define SDEIMR 0xc4004
3116 #define SDEIIR 0xc4008
3117 #define SDEIER 0xc400c
3119 /* digital port hotplug */
3120 #define PCH_PORT_HOTPLUG 0xc4030
3121 #define PORTD_HOTPLUG_ENABLE (1 << 20)
3122 #define PORTD_PULSE_DURATION_2ms (0)
3123 #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
3124 #define PORTD_PULSE_DURATION_6ms (2 << 18)
3125 #define PORTD_PULSE_DURATION_100ms (3 << 18)
3126 #define PORTD_HOTPLUG_NO_DETECT (0)
3127 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
3128 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
3129 #define PORTC_HOTPLUG_ENABLE (1 << 12)
3130 #define PORTC_PULSE_DURATION_2ms (0)
3131 #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
3132 #define PORTC_PULSE_DURATION_6ms (2 << 10)
3133 #define PORTC_PULSE_DURATION_100ms (3 << 10)
3134 #define PORTC_HOTPLUG_NO_DETECT (0)
3135 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
3136 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
3137 #define PORTB_HOTPLUG_ENABLE (1 << 4)
3138 #define PORTB_PULSE_DURATION_2ms (0)
3139 #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
3140 #define PORTB_PULSE_DURATION_6ms (2 << 2)
3141 #define PORTB_PULSE_DURATION_100ms (3 << 2)
3142 #define PORTB_HOTPLUG_NO_DETECT (0)
3143 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
3144 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
3146 #define PCH_GPIOA 0xc5010
3147 #define PCH_GPIOB 0xc5014
3148 #define PCH_GPIOC 0xc5018
3149 #define PCH_GPIOD 0xc501c
3150 #define PCH_GPIOE 0xc5020
3151 #define PCH_GPIOF 0xc5024
3152 #define PCH_GMBUS0 0xc5100
3153 #define PCH_GMBUS1 0xc5104
3154 #define PCH_GMBUS2 0xc5108
3155 #define PCH_GMBUS3 0xc510c
3156 #define PCH_GMBUS4 0xc5110
3157 #define PCH_GMBUS5 0xc5120
3159 #define PCH_DPLL_A 0xc6014
3160 #define PCH_DPLL_B 0xc6018
3162 #define PCH_FPA0 0xc6040
3163 #define PCH_FPA1 0xc6044
3164 #define PCH_FPB0 0xc6048
3165 #define PCH_FPB1 0xc604c
3167 #define PCH_DPLL_TEST 0xc606c
3169 #define PCH_DREF_CONTROL 0xC6200
3170 #define DREF_CONTROL_MASK 0x7fc3
3171 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
3172 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
3173 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
3174 #define DREF_SSC_SOURCE_DISABLE (0<<11)
3175 #define DREF_SSC_SOURCE_ENABLE (2<<11)
3176 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
3177 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
3178 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
3179 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
3180 #define DREF_SSC4_DOWNSPREAD (0<<6)
3181 #define DREF_SSC4_CENTERSPREAD (1<<6)
3182 #define DREF_SSC1_DISABLE (0<<1)
3183 #define DREF_SSC1_ENABLE (1<<1)
3184 #define DREF_SSC4_DISABLE (0)
3185 #define DREF_SSC4_ENABLE (1)
3187 #define PCH_RAWCLK_FREQ 0xc6204
3188 #define FDL_TP1_TIMER_SHIFT 12
3189 #define FDL_TP1_TIMER_MASK (3<<12)
3190 #define FDL_TP2_TIMER_SHIFT 10
3191 #define FDL_TP2_TIMER_MASK (3<<10)
3192 #define RAWCLK_FREQ_MASK 0x3ff
3194 #define PCH_DPLL_TMR_CFG 0xc6208
3196 #define PCH_SSC4_PARMS 0xc6210
3197 #define PCH_SSC4_AUX_PARMS 0xc6214
3200 #define PCH_DPLL_ANALOG_CTL 0xc6300
3202 #define PCH_DPLL_SEL 0xc7000
3203 #define TRANSA_DPLL_ENABLE (1<<3)
3204 #define TRANSA_DPLLA_SEL (0)
3205 #define TRANSA_DPLLB_SEL (1<<0)
3206 #define TRANSB_DPLL_ENABLE (1<<7)
3207 #define TRANSB_DPLLA_SEL (0<<4)
3208 #define TRANSB_DPLLB_SEL (1<<4)
3209 #define TRANSC_DPLL_ENABLE (1<<11)
3210 #define TRANSC_DPLLA_SEL (0<<8)
3211 #define TRANSC_DPLLB_SEL (1<<8)
3215 #define TRANS_HTOTAL_A 0xe0000
3216 #define TRANS_HTOTAL_SHIFT 16
3217 #define TRANS_HACTIVE_SHIFT 0
3218 #define TRANS_HBLANK_A 0xe0004
3219 #define TRANS_HBLANK_END_SHIFT 16
3220 #define TRANS_HBLANK_START_SHIFT 0
3221 #define TRANS_HSYNC_A 0xe0008
3222 #define TRANS_HSYNC_END_SHIFT 16
3223 #define TRANS_HSYNC_START_SHIFT 0
3224 #define TRANS_VTOTAL_A 0xe000c
3225 #define TRANS_VTOTAL_SHIFT 16
3226 #define TRANS_VACTIVE_SHIFT 0
3227 #define TRANS_VBLANK_A 0xe0010
3228 #define TRANS_VBLANK_END_SHIFT 16
3229 #define TRANS_VBLANK_START_SHIFT 0
3230 #define TRANS_VSYNC_A 0xe0014
3231 #define TRANS_VSYNC_END_SHIFT 16
3232 #define TRANS_VSYNC_START_SHIFT 0
3233 #define TRANS_VSYNCSHIFT_A 0xe0028
3235 #define TRANSA_DATA_M1 0xe0030
3236 #define TRANSA_DATA_N1 0xe0034
3237 #define TRANSA_DATA_M2 0xe0038
3238 #define TRANSA_DATA_N2 0xe003c
3239 #define TRANSA_DP_LINK_M1 0xe0040
3240 #define TRANSA_DP_LINK_N1 0xe0044
3241 #define TRANSA_DP_LINK_M2 0xe0048
3242 #define TRANSA_DP_LINK_N2 0xe004c
3244 #define TRANS_HTOTAL_B 0xe1000
3245 #define TRANS_HBLANK_B 0xe1004
3246 #define TRANS_HSYNC_B 0xe1008
3247 #define TRANS_VTOTAL_B 0xe100c
3248 #define TRANS_VBLANK_B 0xe1010
3249 #define TRANS_VSYNC_B 0xe1014
3250 #define TRANS_VSYNCSHIFT_B 0xe1028
3252 #define TRANSB_DATA_M1 0xe1030
3253 #define TRANSB_DATA_N1 0xe1034
3254 #define TRANSB_DATA_M2 0xe1038
3255 #define TRANSB_DATA_N2 0xe103c
3256 #define TRANSB_DP_LINK_M1 0xe1040
3257 #define TRANSB_DP_LINK_N1 0xe1044
3258 #define TRANSB_DP_LINK_M2 0xe1048
3259 #define TRANSB_DP_LINK_N2 0xe104c
3261 #define TRANS_HTOTAL_C 0xe2000
3262 #define TRANS_HBLANK_C 0xe2004
3263 #define TRANS_HSYNC_C 0xe2008
3264 #define TRANS_VTOTAL_C 0xe200c
3265 #define TRANS_VBLANK_C 0xe2010
3266 #define TRANS_VSYNC_C 0xe2014
3267 #define TRANS_VSYNCSHIFT_C 0xe2028
3269 #define TRANSC_DATA_M1 0xe2030
3270 #define TRANSC_DATA_N1 0xe2034
3271 #define TRANSC_DATA_M2 0xe2038
3272 #define TRANSC_DATA_N2 0xe203c
3273 #define TRANSC_DP_LINK_M1 0xe2040
3274 #define TRANSC_DP_LINK_N1 0xe2044
3275 #define TRANSC_DP_LINK_M2 0xe2048
3276 #define TRANSC_DP_LINK_N2 0xe204c
3278 #define TRANSACONF 0xf0008
3279 #define TRANSBCONF 0xf1008
3280 #define TRANSCCONF 0xf2008
3281 #define TRANS_DISABLE (0<<31)
3282 #define TRANS_ENABLE (1<<31)
3283 #define TRANS_STATE_MASK (1<<30)
3284 #define TRANS_STATE_DISABLE (0<<30)
3285 #define TRANS_STATE_ENABLE (1<<30)
3286 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
3287 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
3288 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
3289 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
3290 #define TRANS_DP_AUDIO_ONLY (1<<26)
3291 #define TRANS_DP_VIDEO_AUDIO (0<<26)
3292 #define TRANS_PROGRESSIVE (0<<21)
3293 #define TRANS_8BPC (0<<5)
3294 #define TRANS_10BPC (1<<5)
3295 #define TRANS_6BPC (2<<5)
3296 #define TRANS_12BPC (3<<5)
3298 #define FDI_RXA_CHICKEN 0xc200c
3299 #define FDI_RXB_CHICKEN 0xc2010
3300 #define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1)
3303 #define FDI_TXA_CTL 0x60100
3304 #define FDI_TXB_CTL 0x61100
3305 #define FDI_TXC_CTL 0x62100
3306 #define FDI_TX_DISABLE (0<<31)
3307 #define FDI_TX_ENABLE (1<<31)
3308 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
3309 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
3310 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
3311 #define FDI_LINK_TRAIN_NONE (3<<28)
3312 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
3313 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
3314 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
3315 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
3316 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
3317 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
3318 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
3319 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
3320 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
3321 SNB has different settings. */
3322 /* SNB A-stepping */
3323 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3324 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3325 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3326 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3327 /* SNB B-stepping */
3328 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
3329 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
3330 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
3331 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
3332 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
3333 #define FDI_DP_PORT_WIDTH_X1 (0<<19)
3334 #define FDI_DP_PORT_WIDTH_X2 (1<<19)
3335 #define FDI_DP_PORT_WIDTH_X3 (2<<19)
3336 #define FDI_DP_PORT_WIDTH_X4 (3<<19)
3337 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
3338 /* Ironlake: hardwired to 1 */
3339 #define FDI_TX_PLL_ENABLE (1<<14)
3340 /* both Tx and Rx */
3341 #define FDI_SCRAMBLING_ENABLE (0<<7)
3342 #define FDI_SCRAMBLING_DISABLE (1<<7)
3344 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
3345 #define FDI_RXA_CTL 0xf000c
3346 #define FDI_RXB_CTL 0xf100c
3347 #define FDI_RXC_CTL 0xf200c
3348 #define FDI_RX_ENABLE (1<<31)
3349 #define FDI_RX_DISABLE (0<<31)
3350 /* train, dp width same as FDI_TX */
3351 #define FDI_DP_PORT_WIDTH_X8 (7<<19)
3352 #define FDI_8BPC (0<<16)
3353 #define FDI_10BPC (1<<16)
3354 #define FDI_6BPC (2<<16)
3355 #define FDI_12BPC (3<<16)
3356 #define FDI_LINK_REVERSE_OVERWRITE (1<<15)
3357 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
3358 #define FDI_RX_PLL_ENABLE (1<<13)
3359 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
3360 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
3361 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
3362 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
3363 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
3364 #define FDI_SEL_RAWCLK (0<<4)
3365 #define FDI_SEL_PCDCLK (1<<4)
3367 #define FDI_AUTO_TRAINING (1<<10)
3368 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
3369 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
3370 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
3371 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
3372 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
3374 #define FDI_RXA_MISC 0xf0010
3375 #define FDI_RXB_MISC 0xf1010
3376 #define FDI_RXC_MISC 0xf2010
3377 #define FDI_RXA_TUSIZE1 0xf0030
3378 #define FDI_RXA_TUSIZE2 0xf0038
3379 #define FDI_RXB_TUSIZE1 0xf1030
3380 #define FDI_RXB_TUSIZE2 0xf1038
3381 #define FDI_RXC_TUSIZE1 0xf2030
3382 #define FDI_RXC_TUSIZE2 0xf2038
3384 /* FDI_RX interrupt register format */
3385 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
3386 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
3387 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
3388 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
3389 #define FDI_RX_FS_CODE_ERR (1<<6)
3390 #define FDI_RX_FE_CODE_ERR (1<<5)
3391 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
3392 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
3393 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
3394 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
3395 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
3397 #define FDI_RXA_IIR 0xf0014
3398 #define FDI_RXA_IMR 0xf0018
3399 #define FDI_RXB_IIR 0xf1014
3400 #define FDI_RXB_IMR 0xf1018
3402 #define FDI_PLL_CTL_1 0xfe000
3403 #define FDI_PLL_CTL_2 0xfe004
3406 #define PCH_ADPA 0xe1100
3407 #define ADPA_TRANS_SELECT_MASK (1<<30)
3408 #define ADPA_TRANS_A_SELECT 0
3409 #define ADPA_TRANS_B_SELECT (1<<30)
3411 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
3412 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
3413 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
3414 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3415 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
3416 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
3417 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
3418 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
3419 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
3420 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
3421 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
3422 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
3423 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
3424 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
3425 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
3426 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
3427 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
3428 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
3429 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
3430 /* polarity control not changed */
3433 #define HDMIB 0xe1140
3434 #define PORT_ENABLE (1 << 31)
3435 #define TRANSCODER_A (0)
3436 #define TRANSCODER_B (1 << 30)
3437 #define COLOR_FORMAT_8bpc (0)
3438 #define COLOR_FORMAT_12bpc (3 << 26)
3439 #define SDVOB_HOTPLUG_ENABLE (1 << 23)
3440 #define SDVO_ENCODING (0)
3441 #define TMDS_ENCODING (2 << 10)
3442 #define NULL_PACKET_VSYNC_ENABLE (1 << 9)
3443 #define SDVOB_BORDER_ENABLE (1 << 7)
3444 #define AUDIO_ENABLE (1 << 6)
3445 #define VSYNC_ACTIVE_HIGH (1 << 4)
3446 #define HSYNC_ACTIVE_HIGH (1 << 3)
3447 #define PORT_DETECTED (1 << 2)
3449 #define HDMIC 0xe1150
3450 #define HDMID 0xe1160
3451 #define PCH_LVDS 0xe1180
3453 #define BLC_PWM_CPU_CTL2 0x48250
3454 #define PWM_ENABLE (1 << 31)
3455 #define PWM_PIPE_A (0 << 29)
3456 #define PWM_PIPE_B (1 << 29)
3457 #define BLC_PWM_CPU_CTL 0x48254
3459 #define BLC_PWM_PCH_CTL1 0xc8250
3460 #define PWM_PCH_ENABLE (1 << 31)
3461 #define PWM_POLARITY_ACTIVE_LOW (1 << 29)
3462 #define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
3463 #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
3464 #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
3466 #define BLC_PWM_PCH_CTL2 0xc8254
3468 #define PCH_PP_STATUS 0xc7200
3469 #define PCH_PP_CONTROL 0xc7204
3470 #define EDP_FORCE_VDD (1 << 3)
3471 #define EDP_BLC_ENABLE (1 << 2)
3472 #define PANEL_POWER_RESET (1 << 1)
3473 #define PANEL_POWER_OFF (0 << 0)
3474 #define PANEL_POWER_ON (1 << 0)
3475 #define PCH_PP_ON_DELAYS 0xc7208
3476 #define EDP_PANEL (1 << 30)
3477 #define PCH_PP_OFF_DELAYS 0xc720c
3478 #define PCH_PP_DIVISOR 0xc7210
3480 #define AUD_CONFIG 0x62000
3481 #define AUD_DEBUG 0x62010
3482 #define AUD_VID_DID 0x62020
3483 #define AUD_RID 0x62024
3484 #define AUD_SUBN_CNT 0x62028
3485 #define AUD_FUNC_GRP 0x62040
3486 #define AUD_SUBN_CNT2 0x62044
3487 #define AUD_GRP_CAP 0x62048
3488 #define AUD_PWRST 0x6204c
3489 #define AUD_SUPPWR 0x62050
3490 #define AUD_SID 0x62054
3491 #define AUD_OUT_CWCAP 0x62070
3492 #define AUD_OUT_PCMSIZE 0x62074
3493 #define AUD_OUT_STR 0x62078
3494 #define AUD_OUT_DIG_CNVT 0x6207c
3495 #define AUD_OUT_CH_STR 0x62080
3496 #define AUD_OUT_STR_DESC 0x62084
3497 #define AUD_PINW_CAP 0x620a0
3498 #define AUD_PIN_CAP 0x620a4
3499 #define AUD_PINW_CONNLNG 0x620a8
3500 #define AUD_PINW_CONNLST 0x620ac
3501 #define AUD_PINW_CNTR 0x620b0
3502 #define AUD_PINW_UNSOLRESP 0x620b8
3503 #define AUD_CNTL_ST 0x620b4
3504 #define AUD_PINW_CONFIG 0x620bc
3505 #define AUD_HDMIW_STATUS 0x620d4
3506 #define AUD_HDMIW_HDMIEDID 0x6210c
3507 #define AUD_HDMIW_INFOFR 0x62118
3508 #define AUD_CONV_CHCNT 0x62120
3509 #define AUD_CTS_ENABLE 0x62128
3511 #define VIDEO_DIP_CTL 0x61170
3512 #define VIDEO_DIP_DATA 0x61178
3515 #define TRANS_DP_CTL_A 0xe0300
3516 #define TRANS_DP_CTL_B 0xe1300
3517 #define TRANS_DP_CTL_C 0xe2300
3518 #define TRANS_DP_OUTPUT_ENABLE (1<<31)
3519 #define TRANS_DP_PORT_SEL_B (0<<29)
3520 #define TRANS_DP_PORT_SEL_C (1<<29)
3521 #define TRANS_DP_PORT_SEL_D (2<<29)
3522 #define TRANS_DP_PORT_SEL_MASK (3<<29)
3523 #define TRANS_DP_AUDIO_ONLY (1<<26)
3524 #define TRANS_DP_ENH_FRAMING (1<<18)
3525 #define TRANS_DP_8BPC (0<<9)
3526 #define TRANS_DP_10BPC (1<<9)
3527 #define TRANS_DP_6BPC (2<<9)
3528 #define TRANS_DP_12BPC (3<<9)
3529 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
3530 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
3531 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
3532 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
3535 #define GEN6_TD_CTL 0x7000 /* <= GEN5 was at 0x8000 */
3536 #define GEN6_TD_CTL_FORCE_TD_BKPT (1<<4)
3541 #define PORT_DBG 0x42308
3542 #define PORT_DBG_DRRS_HW_STATE_OFF (0<<30)
3543 #define PORT_DBG_DRRS_HW_STATE_LOW (1<<30)
3544 #define PORT_DBG_DRRS_HW_STATE_HIGH (2<<30)
3546 /* RC6 residence counters
3548 #define RC6_RESIDENCY_TIME 0x138108
3549 #define RC6p_RESIDENCY_TIME 0x13810C
3550 #define RC6pp_RESIDENCY_TIME 0x138110
3552 #define GEN6_RPNSWREQ 0xA008
3553 #define GEN6_RC_VIDEO_FREQ 0xA00C
3554 #define GEN6_RC_CONTROL 0xA090
3555 #define GEN6_RP_DOWN_TIMEOUT 0xA010
3556 #define GEN6_RP_INTERRUPT_LIMITS 0xA014
3557 #define GEN6_RPSTAT1 0xA01C
3558 #define GEN6_RP_CONTROL 0xA024
3559 #define GEN6_RP_UP_THRESHOLD 0xA02C
3560 #define GEN6_RP_DOWN_THRESHOLD 0xA030
3561 #define GEN6_RP_CUR_UP_EI 0xA050
3562 #define GEN6_RP_CUR_UP 0xA054
3563 #define GEN6_RP_PREV_UP 0xA058
3564 #define GEN6_RP_CUR_DOWN_EI 0xA05C
3565 #define GEN6_RP_CUR_DOWN 0xA060
3566 #define GEN6_RP_PREV_DOWN 0xA064
3567 #define GEN6_RP_UP_EI 0xA068
3568 #define GEN6_RP_DOWN_EI 0xA06C
3569 #define GEN6_RP_IDLE_HYSTERSIS 0xA070
3570 #define GEN6_RC_STATE 0xA094
3571 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
3572 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
3573 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
3574 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
3575 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
3576 #define GEN6_RC_SLEEP 0xA0B0
3577 #define GEN6_RC1e_THRESHOLD 0xA0B4
3578 #define GEN6_RC6_THRESHOLD 0xA0B8
3579 #define GEN6_RC6p_THRESHOLD 0xA0BC
3580 #define GEN6_RC6pp_THRESHOLD 0xA0C0
3581 #define GEN6_PMINTRMSK 0xA168
3582 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
3583 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
3584 #define GEN6_PMIER 0x4402C
3585 #define GEN6_PMIMR 0x44024 /* rps_lock */
3586 #define GEN6_PMINTRMSK 0xA168
3588 /* Haswell-related items */
3590 /* HSW Power Wells */
3591 #define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */
3592 #define HSW_PWR_WELL_CTL2 0x45404 /* Driver */
3593 #define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */
3594 #define HSW_PWR_WELL_CTL4 0x4540C /* Debug */
3595 #define HSW_PWR_WELL_ENABLE (1<<31)
3596 #define HSW_PWR_WELL_STATE (1<<30)
3597 #define HSW_PWR_WELL_CTL5 0x45410
3598 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
3599 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
3600 #define HSW_PWR_WELL_FORCE_ON (1<<19)
3601 #define HSW_PWR_WELL_CTL6 0x45414
3603 /* Per-pipe DDI Function Control */
3604 #define PIPE_DDI_FUNC_CTL_A 0x60400
3605 #define PIPE_DDI_FUNC_CTL_B 0x61400
3606 #define PIPE_DDI_FUNC_CTL_C 0x62400
3607 #define PIPE_DDI_FUNC_CTL_EDP 0x6F400
3608 #define DDI_FUNC_CTL(pipe) _PIPE(pipe, \
3609 PIPE_DDI_FUNC_CTL_A, \
3610 PIPE_DDI_FUNC_CTL_B)
3611 #define PIPE_DDI_FUNC_ENABLE (1<<31)
3612 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
3613 #define PIPE_DDI_PORT_MASK (0xf<<28)
3614 #define PIPE_DDI_SELECT_PORT(x) ((x)<<28)
3615 #define PIPE_DDI_MODE_SELECT_HDMI (0<<24)
3616 #define PIPE_DDI_MODE_SELECT_DVI (1<<24)
3617 #define PIPE_DDI_MODE_SELECT_DP_SST (2<<24)
3618 #define PIPE_DDI_MODE_SELECT_DP_MST (3<<24)
3619 #define PIPE_DDI_MODE_SELECT_FDI (4<<24)
3620 #define PIPE_DDI_BPC_8 (0<<20)
3621 #define PIPE_DDI_BPC_10 (1<<20)
3622 #define PIPE_DDI_BPC_6 (2<<20)
3623 #define PIPE_DDI_BPC_12 (3<<20)
3624 #define PIPE_DDI_BFI_ENABLE (1<<4)
3625 #define PIPE_DDI_PORT_WIDTH_X1 (0<<1)
3626 #define PIPE_DDI_PORT_WIDTH_X2 (1<<1)
3627 #define PIPE_DDI_PORT_WIDTH_X4 (3<<1)
3629 /* DisplayPort Transport Control */
3630 #define DP_TP_CTL_A 0x64040
3631 #define DP_TP_CTL_B 0x64140
3632 #define DP_TP_CTL_C 0x64240
3633 #define DP_TP_CTL_D 0x64340
3634 #define DP_TP_CTL_E 0x64440
3635 #define DP_TP_CTL_ENABLE (1<<31)
3636 #define DP_TP_CTL_MODE_SST (0<<27)
3637 #define DP_TP_CTL_MODE_MST (1<<27)
3638 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
3639 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
3640 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
3641 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
3642 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
3643 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
3645 /* DisplayPort Transport Status */
3646 #define DP_TP_STATUS_A 0x64044
3647 #define DP_TP_STATUS_B 0x64144
3648 #define DP_TP_STATUS_C 0x64244
3649 #define DP_TP_STATUS_D 0x64344
3650 #define DP_TP_STATUS_E 0x64444
3651 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
3653 /* DDI Buffer Control */
3654 #define DDI_BUF_CTL_A 0x64000
3655 #define DDI_BUF_CTL_B 0x64100
3656 #define DDI_BUF_CTL_C 0x64200
3657 #define DDI_BUF_CTL_D 0x64300
3658 #define DDI_BUF_CTL_E 0x64400
3659 #define DDI_BUF_CTL_ENABLE (1<<31)
3660 #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */
3661 #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
3662 #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */
3663 #define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */
3664 #define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */
3665 #define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */
3666 #define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */
3667 #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */
3668 #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
3669 #define DDI_BUF_EMP_MASK (0xf<<24)
3670 #define DDI_BUF_IS_IDLE (1<<7)
3671 #define DDI_PORT_WIDTH_X1 (0<<1)
3672 #define DDI_PORT_WIDTH_X2 (1<<1)
3673 #define DDI_PORT_WIDTH_X4 (3<<1)
3674 #define DDI_INIT_DISPLAY_DETECTED (1<<0)
3676 /* LPT PIXCLK_GATE */
3677 #define PIXCLK_GATE 0xC6020
3678 #define PIXCLK_GATE_UNGATE 1<<0
3679 #define PIXCLK_GATE_GATE 0<<0
3682 #define SPLL_CTL 0x46020
3683 #define SPLL_PLL_ENABLE (1<<31)
3684 #define SPLL_PLL_SCC (1<<28)
3685 #define SPLL_PLL_NON_SCC (2<<28)
3686 #define SPLL_PLL_FREQ_810MHz (0<<26)
3687 #define SPLL_PLL_FREQ_1350MHz (1<<26)
3690 #define WRPLL_CTL1 0x46040
3691 #define WRPLL_CTL2 0x46060
3692 #define WRPLL_PLL_ENABLE (1<<31)
3693 #define WRPLL_PLL_SELECT_SSC (0x01<<28)
3694 #define WRPLL_PLL_SELECT_NON_SCC (0x02<<28)
3695 #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
3696 /* WRPLL divider programming */
3697 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
3698 #define WRPLL_DIVIDER_POST(x) ((x)<<8)
3699 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
3701 /* Port clock selection */
3702 #define PORT_CLK_SEL_A 0x46100
3703 #define PORT_CLK_SEL_B 0x46104
3704 #define PORT_CLK_SEL_C 0x46108
3705 #define PORT_CLK_SEL_D 0x4610C
3706 #define PORT_CLK_SEL_E 0x46110
3707 #define PORT_CLK_SEL_LCPLL_2700 (0<<29)
3708 #define PORT_CLK_SEL_LCPLL_1350 (1<<29)
3709 #define PORT_CLK_SEL_LCPLL_810 (2<<29)
3710 #define PORT_CLK_SEL_SPLL (3<<29)
3711 #define PORT_CLK_SEL_WRPLL1 (4<<29)
3712 #define PORT_CLK_SEL_WRPLL2 (5<<29)
3714 /* Pipe clock selection */
3715 #define PIPE_CLK_SEL_A 0x46140
3716 #define PIPE_CLK_SEL_B 0x46144
3717 #define PIPE_CLK_SEL_C 0x46148
3718 /* For each pipe, we need to select the corresponding port clock */
3719 #define PIPE_CLK_SEL_DISABLED (0x0<<29)
3720 #define PIPE_CLK_SEL_PORT(x) ((x+1)<<29)
3723 #define LCPLL_CTL 0x130040
3724 #define LCPLL_PLL_DISABLE (1<<31)
3725 #define LCPLL_PLL_LOCK (1<<30)
3726 #define LCPLL_CD_CLOCK_DISABLE (1<<25)
3727 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
3729 /* Pipe WM_LINETIME - watermark line time */
3730 #define PIPE_WM_LINETIME_A 0x45270
3731 #define PIPE_WM_LINETIME_B 0x45274
3732 #define PIPE_WM_LINETIME_C 0x45278
3733 #define PIPE_WM_LINETIME_MASK (0x1ff)
3734 #define PIPE_WM_LINETIME_TIME(x) ((x))
3735 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
3736 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
3739 #define SFUSE_STRAP 0xc2014
3740 #define SFUSE_STRAP_DDIB_DETECTED (1<<2)
3741 #define SFUSE_STRAP_DDIC_DETECTED (1<<1)
3742 #define SFUSE_STRAP_DDID_DETECTED (1<<0)
3744 /* Valleyview related items */
3746 /* Valleyview DPIO registers */
3747 #define VLV_DISPLAY_BASE 0x180000
3748 #define DPIO_PKT 0x2100
3749 #define DPIO_RID (0 << 24)
3750 #define DPIO_OP_WRITE (1 << 16)
3751 #define DPIO_OP_READ (0 << 16)
3752 #define DPIO_PORTID (0x12 << 8)
3753 #define DPIO_BYTE (0xf << 4)
3754 #define DPIO_BUSY (1 << 0)
3755 #define DPIO_DATA 0x2104
3756 #define DPIO_REG 0x2108
3758 #endif /* _I810_REG_H */