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3 Copyright (c) 2001-2012, Intel Corporation
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32 ******************************************************************************/
35 #ifndef _IGB_H_DEFINED_
36 #define _IGB_H_DEFINED_
43 /* datastructure used to transmit a timed packet */
44 #define IGB_PACKET_LAUNCHTIME 1 /* control when packet transmitted */
45 #define IGB_PACKET_LATCHTIME 2 /* grab a timestamp of transmission */
48 struct resource map; /* bus_dma map for packet */
49 unsigned int offset; /* offset into physical page */
53 u_int64_t attime; /* launchtime */
54 u_int64_t dmatime; /* when dma tx desc wb*/
55 struct igb_packet *next; /* used in the clean routine */
58 typedef struct _device_t {
60 u_int16_t pci_vendor_id;
61 u_int16_t pci_device_id;
69 * Bus dma allocation structure used by
70 * e1000_dma_malloc_page and e1000_dma_free_page.
72 struct igb_dma_alloc {
75 unsigned int mmap_size;
78 int igb_probe( device_t *dev );
79 int igb_attach(char *dev_path, device_t *pdev);
80 int igb_detach(device_t *dev);
81 int igb_suspend(device_t *dev);
82 int igb_resume(device_t *dev);
83 int igb_init(device_t *dev);
84 int igb_dma_malloc_page(device_t *dev, struct igb_dma_alloc *page);
85 void igb_dma_free_page(device_t *dev, struct igb_dma_alloc *page);
86 int igb_xmit(device_t *dev, unsigned int queue_index, struct igb_packet *packet);
87 void igb_clean(device_t *dev, struct igb_packet **cleaned_packets);
88 int igb_get_wallclock(device_t *dev, u_int64_t *curtime, u_int64_t *rdtsc);
89 int igb_set_class_bandwidth(device_t *dev, u_int32_t class_a, u_int32_t class_b, u_int32_t tpktsz);
91 void igb_trigger(device_t *dev, u_int32_t data);
92 void igb_readreg(device_t *dev, u_int32_t reg, u_int32_t *data);
93 void igb_writereg(device_t *dev, u_int32_t reg, u_int32_t data);
95 #endif /* _IGB_H_DEFINED_ */